1/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h 2 * 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * S3C64XX - IRQ support 9 */ 10 11#ifndef __ASM_MACH_S3C64XX_IRQS_H 12#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ 13 14/* we keep the first set of CPU IRQs out of the range of 15 * the ISA space, so that the PC104 has them to itself 16 * and we don't end up having to do horrible things to the 17 * standard ISA drivers.... 18 * 19 * note, since we're using the VICs, our start must be a 20 * mulitple of 32 to allow the common code to work 21 */ 22 23#define S3C_IRQ_OFFSET (32) 24 25#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) 26 27#define IRQ_VIC0_BASE S3C_IRQ(0) 28#define IRQ_VIC1_BASE S3C_IRQ(32) 29 30/* VIC based IRQs */ 31 32#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) 33#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) 34 35/* VIC0 */ 36 37#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) 38#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) 39#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) 40#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) 41#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) 42#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) 43#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) 44#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) 45#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) 46#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) 47#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) 48#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) 49#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) 50#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) 51#define IRQ_2D S3C64XX_IRQ_VIC0(11) 52#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) 53#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) 54#define IRQ_BATF S3C64XX_IRQ_VIC0(14) 55#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) 56#define IRQ_MFC S3C64XX_IRQ_VIC0(16) 57#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) 58#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) 59#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) 60#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) 61#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) 62#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) 63#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) 64#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) 65#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) 66#define IRQ_WDT S3C64XX_IRQ_VIC0(26) 67#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) 68#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) 69#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) 70#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) 71#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) 72 73/* VIC1 */ 74 75#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) 76#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) 77#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) 78#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) 79#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) 80#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) 81#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) 82#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) 83#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) 84#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) 85#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) 86#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) 87#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) 88#define IRQ_NFC S3C64XX_IRQ_VIC1(13) 89#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) 90#define IRQ_USBH S3C64XX_IRQ_VIC1(15) 91#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) 92#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) 93#define IRQ_IIC S3C64XX_IRQ_VIC1(18) 94#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) 95#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) 96#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) 97#define IRQ_MSM S3C64XX_IRQ_VIC1(22) 98#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) 99#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) 100#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) 101#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ 102#define IRQ_OTG S3C64XX_IRQ_VIC1(26) 103#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) 104#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) 105#define IRQ_SEC S3C64XX_IRQ_VIC1(29) 106#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) 107#define IRQ_TC IRQ_PENDN 108#define IRQ_ADC S3C64XX_IRQ_VIC1(31) 109 110#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) 111 112#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) 113#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) 114#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) 115#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) 116#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) 117 118/* compatibility for device defines */ 119 120#define IRQ_IIC1 IRQ_S3C6410_IIC1 121 122/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series 123 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE 124 * which we place after the pair of VICs. */ 125 126#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) 127 128#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) 129#define IRQ_EINT(x) S3C_EINT(x) 130#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) 131 132/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) 133 * that they are sourced from the GPIO pins but with a different scheme for 134 * priority and source indication. 135 * 136 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO 137 * interrupts, but for historical reasons they are kept apart from these 138 * next interrupts. 139 * 140 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the 141 * machine specific support files. 142 */ 143 144#define IRQ_EINT_GROUP1_NR (15) 145#define IRQ_EINT_GROUP2_NR (8) 146#define IRQ_EINT_GROUP3_NR (5) 147#define IRQ_EINT_GROUP4_NR (14) 148#define IRQ_EINT_GROUP5_NR (7) 149#define IRQ_EINT_GROUP6_NR (10) 150#define IRQ_EINT_GROUP7_NR (16) 151#define IRQ_EINT_GROUP8_NR (15) 152#define IRQ_EINT_GROUP9_NR (9) 153 154#define IRQ_EINT_GROUP_BASE S3C_EINT(28) 155#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) 156#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) 157#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) 158#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) 159#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) 160#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) 161#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) 162#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) 163#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) 164 165#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) 166 167/* Define a group of interrupts for board-specific use (eg, for MFD 168 * interrupt controllers). */ 169#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) 170 171#ifdef CONFIG_MACH_WLF_CRAGG_6410 172#define IRQ_BOARD_NR 160 173#elif defined(CONFIG_SMDK6410_WM1190_EV1) 174#define IRQ_BOARD_NR 64 175#elif defined(CONFIG_SMDK6410_WM1192_EV1) 176#define IRQ_BOARD_NR 64 177#else 178#define IRQ_BOARD_NR 16 179#endif 180 181#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) 182 183/* Set the default NR_IRQS */ 184 185#define NR_IRQS (IRQ_BOARD_END + 1) 186 187/* Compatibility */ 188 189#define IRQ_ONENAND IRQ_ONENAND0 190#define IRQ_I2S0 IRQ_S3C6410_IIS 191 192#endif /* __ASM_MACH_S3C64XX_IRQS_H */ 193 194