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12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/mtd/physmap.h>
19
20#include <asm/reboot.h>
21#include <asm/io.h>
22#include <asm/txx9/generic.h>
23#include <asm/txx9/pci.h>
24#include <asm/txx9/rbtx4938.h>
25#include <linux/spi/spi.h>
26#include <asm/txx9/spi.h>
27#include <asm/txx9pio.h>
28
29static void rbtx4938_machine_restart(char *command)
30{
31 local_irq_disable();
32 writeb(1, rbtx4938_softresetlock_addr);
33 writeb(1, rbtx4938_sfvol_addr);
34 writeb(1, rbtx4938_softreset_addr);
35
36 (*_machine_halt)();
37}
38
39static void __init rbtx4938_pci_setup(void)
40{
41#ifdef CONFIG_PCI
42 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
43 struct pci_controller *c = &txx9_primary_pcic;
44
45 register_pci_controller(c);
46
47 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
48 txx9_pci_option =
49 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
50 TXX9_PCI_OPT_CLK_66;
51
52
53 writeb(0, rbtx4938_pcireset_addr);
54
55 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
56 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
57 TXX9_PCI_OPT_CLK_66)
58 tx4938_pciclk66_setup();
59 mdelay(10);
60
61 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
62 writeb(1, rbtx4938_pcireset_addr);
63 iob();
64
65 tx4938_report_pciclk();
66 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
67 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
68 TXX9_PCI_OPT_CLK_AUTO &&
69 txx9_pci66_check(c, 0, 0)) {
70
71 writeb(0, rbtx4938_pcireset_addr);
72
73 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
74 tx4938_pciclk66_setup();
75 mdelay(10);
76
77 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
78 writeb(1, rbtx4938_pcireset_addr);
79 iob();
80
81 tx4938_report_pciclk();
82 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
83 }
84
85 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
86 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
87
88 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
89
90 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
91 & TX4938_CCFG_PCI1DMD))
92 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
93 mdelay(10);
94
95 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
96 tx4938_report_pci1clk();
97
98
99 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
100 register_pci_controller(c);
101 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
102 }
103 tx4938_setup_pcierr_irq();
104#endif
105}
106
107
108
109
110#define SEEPROM1_CS 7
111#define SEEPROM2_CS 0
112#define SEEPROM3_CS 1
113#define SRTC_CS 2
114#define SPI_BUSNO 0
115
116static int __init rbtx4938_ethaddr_init(void)
117{
118#ifdef CONFIG_PCI
119 unsigned char dat[17];
120 unsigned char sum;
121 int i;
122
123
124 if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
125 printk(KERN_ERR "seeprom: read error.\n");
126 return -ENODEV;
127 } else {
128 if (strcmp(dat, "MAC") != 0)
129 printk(KERN_WARNING "seeprom: bad signature.\n");
130 for (i = 0, sum = 0; i < sizeof(dat); i++)
131 sum += dat[i];
132 if (sum)
133 printk(KERN_WARNING "seeprom: bad checksum.\n");
134 }
135 tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
136#endif
137 return 0;
138}
139
140static void __init rbtx4938_spi_setup(void)
141{
142
143 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
144}
145
146static struct resource rbtx4938_fpga_resource;
147
148static void __init rbtx4938_time_init(void)
149{
150 tx4938_time_init(0);
151}
152
153static void __init rbtx4938_mem_setup(void)
154{
155 unsigned long long pcfg;
156
157 if (txx9_master_clock == 0)
158 txx9_master_clock = 25000000;
159
160 tx4938_setup();
161
162#ifdef CONFIG_PCI
163 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
164 txx9_board_pcibios_setup = tx4927_pcibios_setup;
165#else
166 set_io_port_base(RBTX4938_ETHER_BASE);
167#endif
168
169 tx4938_sio_init(7372800, 0);
170
171#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
172 pr_info("PIOSEL: disabling both ATA and NAND selection\n");
173 txx9_clear64(&tx4938_ccfgptr->pcfg,
174 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
175#endif
176
177#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
178 pr_info("PIOSEL: enabling NAND selection\n");
179 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
180 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
181#endif
182
183#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
184 pr_info("PIOSEL: enabling ATA selection\n");
185 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
186 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
187#endif
188
189#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
190 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
191 pr_info("PIOSEL: NAND %s, ATA %s\n",
192 (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
193 (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
194#endif
195
196 rbtx4938_spi_setup();
197 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198
199 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
200 TX4938_PCFG_ATA_SEL)
201 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
202 rbtx4938_piosel_addr);
203 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
204 TX4938_PCFG_NDF_SEL)
205 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
206 rbtx4938_piosel_addr);
207 else
208 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
209 rbtx4938_piosel_addr);
210
211 rbtx4938_fpga_resource.name = "FPGA Registers";
212 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
213 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
214 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
215 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
216 printk(KERN_ERR "request resource for fpga failed\n");
217
218 _machine_restart = rbtx4938_machine_restart;
219
220 writeb(0xff, rbtx4938_led_addr);
221 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
222 readb(rbtx4938_fpga_rev_addr),
223 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
224}
225
226static void __init rbtx4938_ne_init(void)
227{
228 struct resource res[] = {
229 {
230 .start = RBTX4938_RTL_8019_BASE,
231 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
232 .flags = IORESOURCE_IO,
233 }, {
234 .start = RBTX4938_RTL_8019_IRQ,
235 .flags = IORESOURCE_IRQ,
236 }
237 };
238 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
239}
240
241static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
242
243static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
244 int value)
245{
246 u8 val;
247 unsigned long flags;
248 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
249 val = readb(rbtx4938_spics_addr);
250 if (value)
251 val |= 1 << offset;
252 else
253 val &= ~(1 << offset);
254 writeb(val, rbtx4938_spics_addr);
255 mmiowb();
256 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
257}
258
259static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
260 unsigned int offset, int value)
261{
262 rbtx4938_spi_gpio_set(chip, offset, value);
263 return 0;
264}
265
266static struct gpio_chip rbtx4938_spi_gpio_chip = {
267 .set = rbtx4938_spi_gpio_set,
268 .direction_output = rbtx4938_spi_gpio_dir_out,
269 .label = "RBTX4938-SPICS",
270 .base = 16,
271 .ngpio = 3,
272};
273
274static int __init rbtx4938_spi_init(void)
275{
276 struct spi_board_info srtc_info = {
277 .modalias = "rtc-rs5c348",
278 .max_speed_hz = 1000000,
279 .bus_num = 0,
280 .chip_select = 16 + SRTC_CS,
281
282 .mode = SPI_MODE_1 | SPI_CS_HIGH,
283 };
284 spi_register_board_info(&srtc_info, 1);
285 spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
286 spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
287 spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
288 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
289 gpio_direction_output(16 + SRTC_CS, 0);
290 gpio_request(SEEPROM1_CS, "seeprom1");
291 gpio_direction_output(SEEPROM1_CS, 1);
292 gpio_request(16 + SEEPROM2_CS, "seeprom2");
293 gpio_direction_output(16 + SEEPROM2_CS, 1);
294 gpio_request(16 + SEEPROM3_CS, "seeprom3");
295 gpio_direction_output(16 + SEEPROM3_CS, 1);
296 tx4938_spi_init(SPI_BUSNO);
297 return 0;
298}
299
300static void __init rbtx4938_mtd_init(void)
301{
302 struct physmap_flash_data pdata = {
303 .width = 4,
304 };
305
306 switch (readb(rbtx4938_bdipsw_addr) & 7) {
307 case 0:
308
309 txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
310
311 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
312 break;
313 case 1:
314
315 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
316
317 txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
318 break;
319 case 2:
320
321 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
322
323 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
324
325 txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
326 break;
327 case 3:
328
329 txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
330
331 txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
332 break;
333 }
334}
335
336static void __init rbtx4938_arch_init(void)
337{
338 gpiochip_add(&rbtx4938_spi_gpio_chip);
339 rbtx4938_pci_setup();
340 rbtx4938_spi_init();
341}
342
343static void __init rbtx4938_device_init(void)
344{
345 rbtx4938_ethaddr_init();
346 rbtx4938_ne_init();
347 tx4938_wdt_init();
348 rbtx4938_mtd_init();
349
350 tx4938_ndfmc_init(10, 35);
351 tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
352 tx4938_dmac_init(0, 2);
353 tx4938_aclc_init();
354 platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
355 tx4938_sramc_init();
356 txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
357}
358
359struct txx9_board_vec rbtx4938_vec __initdata = {
360 .system = "Toshiba RBTX4938",
361 .prom_init = rbtx4938_prom_init,
362 .mem_setup = rbtx4938_mem_setup,
363 .irq_setup = rbtx4938_irq_setup,
364 .time_init = rbtx4938_time_init,
365 .device_init = rbtx4938_device_init,
366 .arch_init = rbtx4938_arch_init,
367#ifdef CONFIG_PCI
368 .pci_map_irq = rbtx4938_pci_map_irq,
369#endif
370};
371
