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15#include <linux/fs.h>
16#include <linux/proc_fs.h>
17#include <linux/seq_file.h>
18#include <linux/rwsem.h>
19#include <linux/kprobes.h>
20#include <linux/sched.h>
21#include <linux/hardirq.h>
22#include <linux/uaccess.h>
23#include <linux/smp.h>
24#include <linux/cdev.h>
25#include <linux/compat.h>
26#include <asm/hardwall.h>
27#include <asm/traps.h>
28#include <asm/siginfo.h>
29#include <asm/irq_regs.h>
30
31#include <arch/interrupts.h>
32#include <arch/spr_def.h>
33
34
35
36
37
38
39
40
41struct hardwall_type {
42 int index;
43 int is_xdn;
44 int is_idn;
45 int disabled;
46 const char *name;
47 struct list_head list;
48 spinlock_t lock;
49 struct proc_dir_entry *proc_dir;
50};
51
52enum hardwall_index {
53 HARDWALL_UDN = 0,
54#ifndef __tilepro__
55 HARDWALL_IDN = 1,
56 HARDWALL_IPI = 2,
57#endif
58 _HARDWALL_TYPES
59};
60
61static struct hardwall_type hardwall_types[] = {
62 {
63 0,
64 1,
65 0,
66 0,
67 "udn",
68 LIST_HEAD_INIT(hardwall_types[HARDWALL_UDN].list),
69 __SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_UDN].lock),
70 NULL
71 },
72#ifndef __tilepro__
73 {
74 1,
75 1,
76 1,
77 1,
78 "idn",
79 LIST_HEAD_INIT(hardwall_types[HARDWALL_IDN].list),
80 __SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_IDN].lock),
81 NULL
82 },
83 {
84 2,
85 0,
86 0,
87 0,
88 "ipi",
89 LIST_HEAD_INIT(hardwall_types[HARDWALL_IPI].list),
90 __SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_IPI].lock),
91 NULL
92 },
93#endif
94};
95
96
97
98
99
100
101struct hardwall_info {
102 struct list_head list;
103 struct list_head task_head;
104 struct hardwall_type *type;
105 struct cpumask cpumask;
106 int id;
107 int teardown_in_progress;
108
109
110 int ulhc_x;
111 int ulhc_y;
112 int width;
113 int height;
114#if CHIP_HAS_REV1_XDN()
115 atomic_t xdn_pending_count;
116#endif
117};
118
119
120
121static struct proc_dir_entry *hardwall_proc_dir;
122
123
124static void hardwall_add_proc(struct hardwall_info *);
125static void hardwall_remove_proc(struct hardwall_info *);
126
127
128static int __init noudn(char *str)
129{
130 pr_info("User-space UDN access is disabled\n");
131 hardwall_types[HARDWALL_UDN].disabled = 1;
132 return 0;
133}
134early_param("noudn", noudn);
135
136#ifndef __tilepro__
137
138static int __init noidn(char *str)
139{
140 pr_info("User-space IDN access is disabled\n");
141 hardwall_types[HARDWALL_IDN].disabled = 1;
142 return 0;
143}
144early_param("noidn", noidn);
145
146
147static int __init noipi(char *str)
148{
149 pr_info("User-space IPI access is disabled\n");
150 hardwall_types[HARDWALL_IPI].disabled = 1;
151 return 0;
152}
153early_param("noipi", noipi);
154#endif
155
156
157
158
159
160
161#ifdef __tilepro__
162#define mtspr_XDN(hwt, name, val) \
163 do { (void)(hwt); __insn_mtspr(SPR_UDN_##name, (val)); } while (0)
164#define mtspr_MPL_XDN(hwt, name, val) \
165 do { (void)(hwt); __insn_mtspr(SPR_MPL_UDN_##name, (val)); } while (0)
166#define mfspr_XDN(hwt, name) \
167 ((void)(hwt), __insn_mfspr(SPR_UDN_##name))
168#else
169#define mtspr_XDN(hwt, name, val) \
170 do { \
171 if ((hwt)->is_idn) \
172 __insn_mtspr(SPR_IDN_##name, (val)); \
173 else \
174 __insn_mtspr(SPR_UDN_##name, (val)); \
175 } while (0)
176#define mtspr_MPL_XDN(hwt, name, val) \
177 do { \
178 if ((hwt)->is_idn) \
179 __insn_mtspr(SPR_MPL_IDN_##name, (val)); \
180 else \
181 __insn_mtspr(SPR_MPL_UDN_##name, (val)); \
182 } while (0)
183#define mfspr_XDN(hwt, name) \
184 ((hwt)->is_idn ? __insn_mfspr(SPR_IDN_##name) : __insn_mfspr(SPR_UDN_##name))
185#endif
186
187
188#define cpu_online_set(cpu, dst) do { \
189 if (cpu_online(cpu)) \
190 cpumask_set_cpu(cpu, dst); \
191} while (0)
192
193
194
195static int contains(struct hardwall_info *r, int x, int y)
196{
197 return (x >= r->ulhc_x && x < r->ulhc_x + r->width) &&
198 (y >= r->ulhc_y && y < r->ulhc_y + r->height);
199}
200
201
202static int check_rectangle(struct hardwall_info *r, struct cpumask *mask)
203{
204 int x, y, cpu, ulhc, lrhc;
205
206
207 ulhc = find_first_bit(cpumask_bits(mask), nr_cpumask_bits);
208 lrhc = find_last_bit(cpumask_bits(mask), nr_cpumask_bits);
209
210
211 r->ulhc_x = cpu_x(ulhc);
212 r->ulhc_y = cpu_y(ulhc);
213 r->width = cpu_x(lrhc) - r->ulhc_x + 1;
214 r->height = cpu_y(lrhc) - r->ulhc_y + 1;
215
216
217 if (r->width <= 0 || r->height <= 0)
218 return -EINVAL;
219
220
221 for (y = 0, cpu = 0; y < smp_height; ++y)
222 for (x = 0; x < smp_width; ++x, ++cpu)
223 if (cpumask_test_cpu(cpu, mask) != contains(r, x, y))
224 return -EINVAL;
225
226
227
228
229
230
231
232
233 return 0;
234}
235
236
237
238
239
240
241
242enum direction_protect {
243 N_PROTECT = (1 << 0),
244 E_PROTECT = (1 << 1),
245 S_PROTECT = (1 << 2),
246 W_PROTECT = (1 << 3),
247 C_PROTECT = (1 << 4),
248};
249
250static inline int xdn_which_interrupt(struct hardwall_type *hwt)
251{
252#ifndef __tilepro__
253 if (hwt->is_idn)
254 return INT_IDN_FIREWALL;
255#endif
256 return INT_UDN_FIREWALL;
257}
258
259static void enable_firewall_interrupts(struct hardwall_type *hwt)
260{
261 arch_local_irq_unmask_now(xdn_which_interrupt(hwt));
262}
263
264static void disable_firewall_interrupts(struct hardwall_type *hwt)
265{
266 arch_local_irq_mask_now(xdn_which_interrupt(hwt));
267}
268
269
270static void hardwall_setup_func(void *info)
271{
272 struct hardwall_info *r = info;
273 struct hardwall_type *hwt = r->type;
274
275 int cpu = smp_processor_id();
276 int x = cpu % smp_width;
277 int y = cpu / smp_width;
278 int bits = 0;
279 if (x == r->ulhc_x)
280 bits |= W_PROTECT;
281 if (x == r->ulhc_x + r->width - 1)
282 bits |= E_PROTECT;
283 if (y == r->ulhc_y)
284 bits |= N_PROTECT;
285 if (y == r->ulhc_y + r->height - 1)
286 bits |= S_PROTECT;
287 BUG_ON(bits == 0);
288 mtspr_XDN(hwt, DIRECTION_PROTECT, bits);
289 enable_firewall_interrupts(hwt);
290}
291
292
293static void hardwall_protect_rectangle(struct hardwall_info *r)
294{
295 int x, y, cpu, delta;
296 struct cpumask rect_cpus;
297
298 cpumask_clear(&rect_cpus);
299
300
301 cpu = r->ulhc_y * smp_width + r->ulhc_x;
302 delta = (r->height - 1) * smp_width;
303 for (x = 0; x < r->width; ++x, ++cpu) {
304 cpu_online_set(cpu, &rect_cpus);
305 cpu_online_set(cpu + delta, &rect_cpus);
306 }
307
308
309 cpu -= r->width;
310 delta = r->width - 1;
311 for (y = 0; y < r->height; ++y, cpu += smp_width) {
312 cpu_online_set(cpu, &rect_cpus);
313 cpu_online_set(cpu + delta, &rect_cpus);
314 }
315
316
317 on_each_cpu_mask(&rect_cpus, hardwall_setup_func, r, 1);
318}
319
320void __kprobes do_hardwall_trap(struct pt_regs* regs, int fault_num)
321{
322 struct hardwall_info *rect;
323 struct hardwall_type *hwt;
324 struct task_struct *p;
325 struct siginfo info;
326 int cpu = smp_processor_id();
327 int found_processes;
328 unsigned long flags;
329 struct pt_regs *old_regs = set_irq_regs(regs);
330
331 irq_enter();
332
333
334 switch (fault_num) {
335#ifndef __tilepro__
336 case INT_IDN_FIREWALL:
337 hwt = &hardwall_types[HARDWALL_IDN];
338 break;
339#endif
340 case INT_UDN_FIREWALL:
341 hwt = &hardwall_types[HARDWALL_UDN];
342 break;
343 default:
344 BUG();
345 }
346 BUG_ON(hwt->disabled);
347
348
349 spin_lock_irqsave(&hwt->lock, flags);
350 list_for_each_entry(rect, &hwt->list, list) {
351 if (cpumask_test_cpu(cpu, &rect->cpumask))
352 break;
353 }
354
355
356
357
358
359
360 BUG_ON(&rect->list == &hwt->list);
361
362
363
364
365
366
367 if (rect->teardown_in_progress) {
368 pr_notice("cpu %d: detected %s hardwall violation %#lx"
369 " while teardown already in progress\n",
370 cpu, hwt->name,
371 (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
372 goto done;
373 }
374
375
376
377
378
379
380
381
382
383 rect->teardown_in_progress = 1;
384 wmb();
385 pr_notice("cpu %d: detected %s hardwall violation %#lx...\n",
386 cpu, hwt->name, (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
387 info.si_signo = SIGILL;
388 info.si_errno = 0;
389 info.si_code = ILL_HARDWALL;
390 found_processes = 0;
391 list_for_each_entry(p, &rect->task_head,
392 thread.hardwall[hwt->index].list) {
393 BUG_ON(p->thread.hardwall[hwt->index].info != rect);
394 if (!(p->flags & PF_EXITING)) {
395 found_processes = 1;
396 pr_notice("hardwall: killing %d\n", p->pid);
397 do_send_sig_info(info.si_signo, &info, p, false);
398 }
399 }
400 if (!found_processes)
401 pr_notice("hardwall: no associated processes!\n");
402
403 done:
404 spin_unlock_irqrestore(&hwt->lock, flags);
405
406
407
408
409
410
411
412
413 disable_firewall_interrupts(hwt);
414
415 irq_exit();
416 set_irq_regs(old_regs);
417}
418
419
420void grant_hardwall_mpls(struct hardwall_type *hwt)
421{
422#ifndef __tilepro__
423 if (!hwt->is_xdn) {
424 __insn_mtspr(SPR_MPL_IPI_0_SET_0, 1);
425 return;
426 }
427#endif
428 mtspr_MPL_XDN(hwt, ACCESS_SET_0, 1);
429 mtspr_MPL_XDN(hwt, AVAIL_SET_0, 1);
430 mtspr_MPL_XDN(hwt, COMPLETE_SET_0, 1);
431 mtspr_MPL_XDN(hwt, TIMER_SET_0, 1);
432#if !CHIP_HAS_REV1_XDN()
433 mtspr_MPL_XDN(hwt, REFILL_SET_0, 1);
434 mtspr_MPL_XDN(hwt, CA_SET_0, 1);
435#endif
436}
437
438
439void restrict_hardwall_mpls(struct hardwall_type *hwt)
440{
441#ifndef __tilepro__
442 if (!hwt->is_xdn) {
443 __insn_mtspr(SPR_MPL_IPI_0_SET_1, 1);
444 return;
445 }
446#endif
447 mtspr_MPL_XDN(hwt, ACCESS_SET_1, 1);
448 mtspr_MPL_XDN(hwt, AVAIL_SET_1, 1);
449 mtspr_MPL_XDN(hwt, COMPLETE_SET_1, 1);
450 mtspr_MPL_XDN(hwt, TIMER_SET_1, 1);
451#if !CHIP_HAS_REV1_XDN()
452 mtspr_MPL_XDN(hwt, REFILL_SET_1, 1);
453 mtspr_MPL_XDN(hwt, CA_SET_1, 1);
454#endif
455}
456
457
458void hardwall_switch_tasks(struct task_struct *prev,
459 struct task_struct *next)
460{
461 int i;
462 for (i = 0; i < HARDWALL_TYPES; ++i) {
463 if (prev->thread.hardwall[i].info != NULL) {
464 if (next->thread.hardwall[i].info == NULL)
465 restrict_hardwall_mpls(&hardwall_types[i]);
466 } else if (next->thread.hardwall[i].info != NULL) {
467 grant_hardwall_mpls(&hardwall_types[i]);
468 }
469 }
470}
471
472
473int hardwall_ipi_valid(int cpu)
474{
475#ifdef __tilegx__
476 struct hardwall_info *info =
477 current->thread.hardwall[HARDWALL_IPI].info;
478 return info && cpumask_test_cpu(cpu, &info->cpumask);
479#else
480 return 0;
481#endif
482}
483
484
485
486
487
488
489static struct hardwall_info *hardwall_create(struct hardwall_type *hwt,
490 size_t size,
491 const unsigned char __user *bits)
492{
493 struct hardwall_info *iter, *info;
494 struct cpumask mask;
495 unsigned long flags;
496 int rc;
497
498
499 if (size > PAGE_SIZE)
500 return ERR_PTR(-EINVAL);
501
502
503 if (copy_from_user(&mask, bits, min(sizeof(struct cpumask), size)))
504 return ERR_PTR(-EFAULT);
505
506
507
508
509
510
511 if (size < sizeof(struct cpumask)) {
512 memset((char *)&mask + size, 0, sizeof(struct cpumask) - size);
513 } else if (size > sizeof(struct cpumask)) {
514 size_t i;
515 for (i = sizeof(struct cpumask); i < size; ++i) {
516 char c;
517 if (get_user(c, &bits[i]))
518 return ERR_PTR(-EFAULT);
519 if (c)
520 return ERR_PTR(-EINVAL);
521 }
522 }
523
524
525 info = kmalloc(sizeof(struct hardwall_info),
526 GFP_KERNEL | __GFP_ZERO);
527 if (info == NULL)
528 return ERR_PTR(-ENOMEM);
529 INIT_LIST_HEAD(&info->task_head);
530 info->type = hwt;
531
532
533 cpumask_copy(&info->cpumask, &mask);
534 info->id = find_first_bit(cpumask_bits(&mask), nr_cpumask_bits);
535 if (hwt->is_xdn) {
536 rc = check_rectangle(info, &mask);
537 if (rc != 0) {
538 kfree(info);
539 return ERR_PTR(rc);
540 }
541 }
542
543
544 spin_lock_irqsave(&hwt->lock, flags);
545 list_for_each_entry(iter, &hwt->list, list) {
546 if (cpumask_intersects(&iter->cpumask, &info->cpumask)) {
547 spin_unlock_irqrestore(&hwt->lock, flags);
548 kfree(info);
549 return ERR_PTR(-EBUSY);
550 }
551 }
552 list_add_tail(&info->list, &hwt->list);
553 spin_unlock_irqrestore(&hwt->lock, flags);
554
555
556 if (hwt->is_xdn)
557 hardwall_protect_rectangle(info);
558
559
560 hardwall_add_proc(info);
561
562 return info;
563}
564
565
566static int hardwall_activate(struct hardwall_info *info)
567{
568 int cpu;
569 unsigned long flags;
570 struct task_struct *p = current;
571 struct thread_struct *ts = &p->thread;
572 struct hardwall_type *hwt;
573
574
575 if (info == NULL)
576 return -ENODATA;
577
578
579 if (info->teardown_in_progress)
580 return -EINVAL;
581
582
583
584
585
586 if (cpumask_weight(&p->cpus_allowed) != 1)
587 return -EPERM;
588
589
590 cpu = smp_processor_id();
591 BUG_ON(cpumask_first(&p->cpus_allowed) != cpu);
592 if (!cpumask_test_cpu(cpu, &info->cpumask))
593 return -EINVAL;
594
595
596 hwt = info->type;
597 if (ts->hardwall[hwt->index].info) {
598 BUG_ON(ts->hardwall[hwt->index].info != info);
599 return 0;
600 }
601
602
603 ts->hardwall[hwt->index].info = info;
604 spin_lock_irqsave(&hwt->lock, flags);
605 list_add(&ts->hardwall[hwt->index].list, &info->task_head);
606 spin_unlock_irqrestore(&hwt->lock, flags);
607 grant_hardwall_mpls(hwt);
608 printk(KERN_DEBUG "Pid %d (%s) activated for %s hardwall: cpu %d\n",
609 p->pid, p->comm, hwt->name, cpu);
610 return 0;
611}
612
613
614
615
616
617
618
619static void _hardwall_deactivate(struct hardwall_type *hwt,
620 struct task_struct *task)
621{
622 struct thread_struct *ts = &task->thread;
623
624 if (cpumask_weight(&task->cpus_allowed) != 1) {
625 pr_err("pid %d (%s) releasing %s hardwall with"
626 " an affinity mask containing %d cpus!\n",
627 task->pid, task->comm, hwt->name,
628 cpumask_weight(&task->cpus_allowed));
629 BUG();
630 }
631
632 BUG_ON(ts->hardwall[hwt->index].info == NULL);
633 ts->hardwall[hwt->index].info = NULL;
634 list_del(&ts->hardwall[hwt->index].list);
635 if (task == current)
636 restrict_hardwall_mpls(hwt);
637}
638
639
640static int hardwall_deactivate(struct hardwall_type *hwt,
641 struct task_struct *task)
642{
643 unsigned long flags;
644 int activated;
645
646 spin_lock_irqsave(&hwt->lock, flags);
647 activated = (task->thread.hardwall[hwt->index].info != NULL);
648 if (activated)
649 _hardwall_deactivate(hwt, task);
650 spin_unlock_irqrestore(&hwt->lock, flags);
651
652 if (!activated)
653 return -EINVAL;
654
655 printk(KERN_DEBUG "Pid %d (%s) deactivated for %s hardwall: cpu %d\n",
656 task->pid, task->comm, hwt->name, smp_processor_id());
657 return 0;
658}
659
660void hardwall_deactivate_all(struct task_struct *task)
661{
662 int i;
663 for (i = 0; i < HARDWALL_TYPES; ++i)
664 if (task->thread.hardwall[i].info)
665 hardwall_deactivate(&hardwall_types[i], task);
666}
667
668
669static void stop_xdn_switch(void *arg)
670{
671#if !CHIP_HAS_REV1_XDN()
672
673 __insn_mtspr(SPR_UDN_SP_FREEZE,
674 SPR_UDN_SP_FREEZE__SP_FRZ_MASK |
675 SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK |
676 SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK);
677#else
678
679
680
681
682
683
684
685
686
687
688
689 struct hardwall_type *hwt = arg;
690 unsigned long protect = mfspr_XDN(hwt, DIRECTION_PROTECT);
691 mtspr_XDN(hwt, DIRECTION_PROTECT, (protect | C_PROTECT) << 5);
692#endif
693}
694
695static void empty_xdn_demuxes(struct hardwall_type *hwt)
696{
697#ifndef __tilepro__
698 if (hwt->is_idn) {
699 while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 0))
700 (void) __tile_idn0_receive();
701 while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 1))
702 (void) __tile_idn1_receive();
703 return;
704 }
705#endif
706 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 0))
707 (void) __tile_udn0_receive();
708 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 1))
709 (void) __tile_udn1_receive();
710 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 2))
711 (void) __tile_udn2_receive();
712 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 3))
713 (void) __tile_udn3_receive();
714}
715
716
717static void drain_xdn_switch(void *arg)
718{
719 struct hardwall_info *info = arg;
720 struct hardwall_type *hwt = info->type;
721
722#if CHIP_HAS_REV1_XDN()
723
724
725
726
727
728
729
730 int pending = mfspr_XDN(hwt, PENDING);
731 while (pending--) {
732 empty_xdn_demuxes(hwt);
733 if (hwt->is_idn)
734 __tile_idn_send(0);
735 else
736 __tile_udn_send(0);
737 }
738 atomic_dec(&info->xdn_pending_count);
739 while (atomic_read(&info->xdn_pending_count))
740 empty_xdn_demuxes(hwt);
741#else
742 int i;
743 int from_tile_words, ca_count;
744
745
746 for (i = 0; i < 5; i++) {
747 int words, j;
748 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
749 words = __insn_mfspr(SPR_UDN_SP_STATE) & 0xF;
750 for (j = 0; j < words; j++)
751 (void) __insn_mfspr(SPR_UDN_SP_FIFO_DATA);
752 BUG_ON((__insn_mfspr(SPR_UDN_SP_STATE) & 0xF) != 0);
753 }
754
755
756 from_tile_words = (__insn_mfspr(SPR_UDN_DEMUX_STATUS) >> 10) & 0x3;
757 for (i = 0; i < from_tile_words; i++)
758 (void) __insn_mfspr(SPR_UDN_DEMUX_WRITE_FIFO);
759
760
761 empty_xdn_demuxes(hwt);
762
763
764 ca_count = __insn_mfspr(SPR_UDN_DEMUX_CA_COUNT);
765 for (i = 0; i < ca_count; i++)
766 (void) __insn_mfspr(SPR_UDN_CA_DATA);
767 BUG_ON(__insn_mfspr(SPR_UDN_DEMUX_CA_COUNT) != 0);
768
769
770 __insn_mtspr(SPR_UDN_DEMUX_CTL, 1);
771
772
773
774
775
776 for (i = 0; i < 5; i++) {
777 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
778 __insn_mtspr(SPR_UDN_SP_STATE, 0xc3000);
779 }
780#endif
781}
782
783
784static void reset_xdn_network_state(struct hardwall_type *hwt)
785{
786 if (hwt->disabled)
787 return;
788
789
790 mtspr_XDN(hwt, DIRECTION_PROTECT, 0);
791 mtspr_XDN(hwt, AVAIL_EN, 0);
792 mtspr_XDN(hwt, DEADLOCK_TIMEOUT, 0);
793
794#if !CHIP_HAS_REV1_XDN()
795
796 {
797 unsigned int cpu = smp_processor_id();
798 unsigned int x = cpu % smp_width;
799 unsigned int y = cpu / smp_width;
800 __insn_mtspr(SPR_UDN_TILE_COORD, (x << 18) | (y << 7));
801 }
802
803
804 __insn_mtspr(SPR_UDN_TAG_VALID, 0xf);
805 __insn_mtspr(SPR_UDN_TAG_0, (1 << 0));
806 __insn_mtspr(SPR_UDN_TAG_1, (1 << 1));
807 __insn_mtspr(SPR_UDN_TAG_2, (1 << 2));
808 __insn_mtspr(SPR_UDN_TAG_3, (1 << 3));
809
810
811 __insn_mtspr(SPR_UDN_REFILL_EN, 0);
812 __insn_mtspr(SPR_UDN_DEMUX_QUEUE_SEL, 0);
813 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, 0);
814
815
816 __insn_mtspr(SPR_UDN_SP_FREEZE, 0);
817#endif
818}
819
820void reset_network_state(void)
821{
822 reset_xdn_network_state(&hardwall_types[HARDWALL_UDN]);
823#ifndef __tilepro__
824 reset_xdn_network_state(&hardwall_types[HARDWALL_IDN]);
825#endif
826}
827
828
829static void restart_xdn_switch(void *arg)
830{
831 struct hardwall_type *hwt = arg;
832
833#if CHIP_HAS_REV1_XDN()
834
835 empty_xdn_demuxes(hwt);
836#endif
837
838 reset_xdn_network_state(hwt);
839
840
841 disable_firewall_interrupts(hwt);
842}
843
844
845static void hardwall_destroy(struct hardwall_info *info)
846{
847 struct task_struct *task;
848 struct hardwall_type *hwt;
849 unsigned long flags;
850
851
852 if (info == NULL)
853 return;
854
855
856
857
858
859
860
861
862 hwt = info->type;
863 info->teardown_in_progress = 1;
864 spin_lock_irqsave(&hwt->lock, flags);
865 list_for_each_entry(task, &info->task_head,
866 thread.hardwall[hwt->index].list)
867 _hardwall_deactivate(hwt, task);
868 spin_unlock_irqrestore(&hwt->lock, flags);
869
870 if (hwt->is_xdn) {
871
872 printk(KERN_DEBUG
873 "Clearing %s hardwall rectangle %dx%d %d,%d\n",
874 hwt->name, info->width, info->height,
875 info->ulhc_x, info->ulhc_y);
876 on_each_cpu_mask(&info->cpumask, stop_xdn_switch, hwt, 1);
877
878
879#if CHIP_HAS_REV1_XDN()
880 atomic_set(&info->xdn_pending_count,
881 cpumask_weight(&info->cpumask));
882 on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 0);
883#else
884 on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 1);
885#endif
886
887
888 on_each_cpu_mask(&info->cpumask, restart_xdn_switch, hwt, 1);
889 }
890
891
892 hardwall_remove_proc(info);
893
894
895 spin_lock_irqsave(&hwt->lock, flags);
896 BUG_ON(!list_empty(&info->task_head));
897 list_del(&info->list);
898 spin_unlock_irqrestore(&hwt->lock, flags);
899 kfree(info);
900}
901
902
903static int hardwall_proc_show(struct seq_file *sf, void *v)
904{
905 struct hardwall_info *info = sf->private;
906 char buf[256];
907
908 int rc = cpulist_scnprintf(buf, sizeof(buf), &info->cpumask);
909 buf[rc++] = '\n';
910 seq_write(sf, buf, rc);
911 return 0;
912}
913
914static int hardwall_proc_open(struct inode *inode,
915 struct file *file)
916{
917 return single_open(file, hardwall_proc_show, PDE_DATA(inode));
918}
919
920static const struct file_operations hardwall_proc_fops = {
921 .open = hardwall_proc_open,
922 .read = seq_read,
923 .llseek = seq_lseek,
924 .release = single_release,
925};
926
927static void hardwall_add_proc(struct hardwall_info *info)
928{
929 char buf[64];
930 snprintf(buf, sizeof(buf), "%d", info->id);
931 proc_create_data(buf, 0444, info->type->proc_dir,
932 &hardwall_proc_fops, info);
933}
934
935static void hardwall_remove_proc(struct hardwall_info *info)
936{
937 char buf[64];
938 snprintf(buf, sizeof(buf), "%d", info->id);
939 remove_proc_entry(buf, info->type->proc_dir);
940}
941
942int proc_pid_hardwall(struct task_struct *task, char *buffer)
943{
944 int i;
945 int n = 0;
946 for (i = 0; i < HARDWALL_TYPES; ++i) {
947 struct hardwall_info *info = task->thread.hardwall[i].info;
948 if (info)
949 n += sprintf(&buffer[n], "%s: %d\n",
950 info->type->name, info->id);
951 }
952 return n;
953}
954
955void proc_tile_hardwall_init(struct proc_dir_entry *root)
956{
957 int i;
958 for (i = 0; i < HARDWALL_TYPES; ++i) {
959 struct hardwall_type *hwt = &hardwall_types[i];
960 if (hwt->disabled)
961 continue;
962 if (hardwall_proc_dir == NULL)
963 hardwall_proc_dir = proc_mkdir("hardwall", root);
964 hwt->proc_dir = proc_mkdir(hwt->name, hardwall_proc_dir);
965 }
966}
967
968
969
970
971
972
973static long hardwall_ioctl(struct file *file, unsigned int a, unsigned long b)
974{
975 struct hardwall_info *info = file->private_data;
976 int minor = iminor(file->f_mapping->host);
977 struct hardwall_type* hwt;
978
979 if (_IOC_TYPE(a) != HARDWALL_IOCTL_BASE)
980 return -EINVAL;
981
982 BUILD_BUG_ON(HARDWALL_TYPES != _HARDWALL_TYPES);
983 BUILD_BUG_ON(HARDWALL_TYPES !=
984 sizeof(hardwall_types)/sizeof(hardwall_types[0]));
985
986 if (minor < 0 || minor >= HARDWALL_TYPES)
987 return -EINVAL;
988 hwt = &hardwall_types[minor];
989 WARN_ON(info && hwt != info->type);
990
991 switch (_IOC_NR(a)) {
992 case _HARDWALL_CREATE:
993 if (hwt->disabled)
994 return -ENOSYS;
995 if (info != NULL)
996 return -EALREADY;
997 info = hardwall_create(hwt, _IOC_SIZE(a),
998 (const unsigned char __user *)b);
999 if (IS_ERR(info))
1000 return PTR_ERR(info);
1001 file->private_data = info;
1002 return 0;
1003
1004 case _HARDWALL_ACTIVATE:
1005 return hardwall_activate(info);
1006
1007 case _HARDWALL_DEACTIVATE:
1008 if (current->thread.hardwall[hwt->index].info != info)
1009 return -EINVAL;
1010 return hardwall_deactivate(hwt, current);
1011
1012 case _HARDWALL_GET_ID:
1013 return info ? info->id : -EINVAL;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018}
1019
1020#ifdef CONFIG_COMPAT
1021static long hardwall_compat_ioctl(struct file *file,
1022 unsigned int a, unsigned long b)
1023{
1024
1025 return hardwall_ioctl(file, a, (unsigned long)compat_ptr(b));
1026}
1027#endif
1028
1029
1030static int hardwall_flush(struct file *file, fl_owner_t owner)
1031{
1032 struct hardwall_info *info = file->private_data;
1033 struct task_struct *task, *tmp;
1034 unsigned long flags;
1035
1036 if (info) {
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046 struct hardwall_type *hwt = info->type;
1047 spin_lock_irqsave(&hwt->lock, flags);
1048 list_for_each_entry_safe(task, tmp, &info->task_head,
1049 thread.hardwall[hwt->index].list) {
1050 if (task->files == owner || task->files == NULL)
1051 _hardwall_deactivate(hwt, task);
1052 }
1053 spin_unlock_irqrestore(&hwt->lock, flags);
1054 }
1055
1056 return 0;
1057}
1058
1059
1060static int hardwall_release(struct inode *inode, struct file *file)
1061{
1062 hardwall_destroy(file->private_data);
1063 return 0;
1064}
1065
1066static const struct file_operations dev_hardwall_fops = {
1067 .open = nonseekable_open,
1068 .unlocked_ioctl = hardwall_ioctl,
1069#ifdef CONFIG_COMPAT
1070 .compat_ioctl = hardwall_compat_ioctl,
1071#endif
1072 .flush = hardwall_flush,
1073 .release = hardwall_release,
1074};
1075
1076static struct cdev hardwall_dev;
1077
1078static int __init dev_hardwall_init(void)
1079{
1080 int rc;
1081 dev_t dev;
1082
1083 rc = alloc_chrdev_region(&dev, 0, HARDWALL_TYPES, "hardwall");
1084 if (rc < 0)
1085 return rc;
1086 cdev_init(&hardwall_dev, &dev_hardwall_fops);
1087 rc = cdev_add(&hardwall_dev, dev, HARDWALL_TYPES);
1088 if (rc < 0)
1089 return rc;
1090
1091 return 0;
1092}
1093late_initcall(dev_hardwall_init);
1094