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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/random.h>
38#include <linux/highmem.h>
39#include <linux/time.h>
40#include <linux/hugetlb.h>
41#include <linux/irq.h>
42#include <asm/byteorder.h>
43#include <net/ip.h>
44#include <rdma/ib_verbs.h>
45#include <rdma/iw_cm.h>
46#include <rdma/ib_user_verbs.h>
47#include <rdma/ib_umem.h>
48#include "i40iw.h"
49
50
51
52
53
54
55
56static int i40iw_query_device(struct ib_device *ibdev,
57 struct ib_device_attr *props,
58 struct ib_udata *udata)
59{
60 struct i40iw_device *iwdev = to_iwdev(ibdev);
61
62 if (udata->inlen || udata->outlen)
63 return -EINVAL;
64 memset(props, 0, sizeof(*props));
65 ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
66 props->fw_ver = I40IW_FW_VERSION;
67 props->device_cap_flags = iwdev->device_cap_flags;
68 props->vendor_id = iwdev->ldev->pcidev->vendor;
69 props->vendor_part_id = iwdev->ldev->pcidev->device;
70 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
71 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
72 props->max_qp = iwdev->max_qp - iwdev->used_qps;
73 props->max_qp_wr = I40IW_MAX_QP_WRS;
74 props->max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
75 props->max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
76 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
77 props->max_cqe = iwdev->max_cqe;
78 props->max_mr = iwdev->max_mr - iwdev->used_mrs;
79 props->max_pd = iwdev->max_pd - iwdev->used_pds;
80 props->max_sge_rd = I40IW_MAX_SGE_RD;
81 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
82 props->max_qp_init_rd_atom = props->max_qp_rd_atom;
83 props->atomic_cap = IB_ATOMIC_NONE;
84 props->max_map_per_fmr = 1;
85 props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
86 return 0;
87}
88
89
90
91
92
93
94
95static int i40iw_query_port(struct ib_device *ibdev,
96 u8 port,
97 struct ib_port_attr *props)
98{
99 struct i40iw_device *iwdev = to_iwdev(ibdev);
100 struct net_device *netdev = iwdev->netdev;
101
102
103 props->max_mtu = IB_MTU_4096;
104 props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
105
106 props->lid = 1;
107 if (netif_carrier_ok(iwdev->netdev))
108 props->state = IB_PORT_ACTIVE;
109 else
110 props->state = IB_PORT_DOWN;
111 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
112 IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
113 props->gid_tbl_len = 1;
114 props->pkey_tbl_len = 1;
115 props->active_width = IB_WIDTH_4X;
116 props->active_speed = 1;
117 props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
118 return 0;
119}
120
121
122
123
124
125
126
127
128
129static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
130 struct ib_udata *udata)
131{
132 struct i40iw_device *iwdev = to_iwdev(ibdev);
133 struct i40iw_alloc_ucontext_req req;
134 struct i40iw_alloc_ucontext_resp uresp;
135 struct i40iw_ucontext *ucontext;
136
137 if (ib_copy_from_udata(&req, udata, sizeof(req)))
138 return ERR_PTR(-EINVAL);
139
140 if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
141 i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
142 return ERR_PTR(-EINVAL);
143 }
144
145 memset(&uresp, 0, sizeof(uresp));
146 uresp.max_qps = iwdev->max_qp;
147 uresp.max_pds = iwdev->max_pd;
148 uresp.wq_size = iwdev->max_qp_wr * 2;
149 uresp.kernel_ver = req.userspace_ver;
150
151 ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
152 if (!ucontext)
153 return ERR_PTR(-ENOMEM);
154
155 ucontext->iwdev = iwdev;
156 ucontext->abi_ver = req.userspace_ver;
157
158 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
159 kfree(ucontext);
160 return ERR_PTR(-EFAULT);
161 }
162
163 INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
164 spin_lock_init(&ucontext->cq_reg_mem_list_lock);
165 INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
166 spin_lock_init(&ucontext->qp_reg_mem_list_lock);
167
168 return &ucontext->ibucontext;
169}
170
171
172
173
174
175static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
176{
177 struct i40iw_ucontext *ucontext = to_ucontext(context);
178 unsigned long flags;
179
180 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
181 if (!list_empty(&ucontext->cq_reg_mem_list)) {
182 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
183 return -EBUSY;
184 }
185 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
186 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
187 if (!list_empty(&ucontext->qp_reg_mem_list)) {
188 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
189 return -EBUSY;
190 }
191 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
192
193 kfree(ucontext);
194 return 0;
195}
196
197
198
199
200
201
202static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
203{
204 struct i40iw_ucontext *ucontext;
205 u64 db_addr_offset;
206 u64 push_offset;
207
208 ucontext = to_ucontext(context);
209 if (ucontext->iwdev->sc_dev.is_pf) {
210 db_addr_offset = I40IW_DB_ADDR_OFFSET;
211 push_offset = I40IW_PUSH_OFFSET;
212 if (vma->vm_pgoff)
213 vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
214 } else {
215 db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
216 push_offset = I40IW_VF_PUSH_OFFSET;
217 if (vma->vm_pgoff)
218 vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
219 }
220
221 vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
222
223 if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
224 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
225 vma->vm_private_data = ucontext;
226 } else {
227 if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
228 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
229 else
230 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
231 }
232
233 if (io_remap_pfn_range(vma, vma->vm_start,
234 vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
235 PAGE_SIZE, vma->vm_page_prot))
236 return -EAGAIN;
237
238 return 0;
239}
240
241
242
243
244
245
246static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
247{
248 struct i40iw_cqp_request *cqp_request;
249 struct cqp_commands_info *cqp_info;
250 enum i40iw_status_code status;
251
252 if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
253 return;
254
255 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
256 if (!cqp_request)
257 return;
258
259 atomic_inc(&cqp_request->refcount);
260
261 cqp_info = &cqp_request->info;
262 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
263 cqp_info->post_sq = 1;
264
265 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
266 cqp_info->in.u.manage_push_page.info.free_page = 0;
267 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
268 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
269
270 status = i40iw_handle_cqp_op(iwdev, cqp_request);
271 if (!status)
272 qp->push_idx = cqp_request->compl_info.op_ret_val;
273 else
274 i40iw_pr_err("CQP-OP Push page fail");
275 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
276}
277
278
279
280
281
282
283static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
284{
285 struct i40iw_cqp_request *cqp_request;
286 struct cqp_commands_info *cqp_info;
287 enum i40iw_status_code status;
288
289 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
290 return;
291
292 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
293 if (!cqp_request)
294 return;
295
296 cqp_info = &cqp_request->info;
297 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
298 cqp_info->post_sq = 1;
299
300 cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
301 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
302 cqp_info->in.u.manage_push_page.info.free_page = 1;
303 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
304 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
305
306 status = i40iw_handle_cqp_op(iwdev, cqp_request);
307 if (!status)
308 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
309 else
310 i40iw_pr_err("CQP-OP Push page fail");
311}
312
313
314
315
316
317
318
319static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
320 struct ib_ucontext *context,
321 struct ib_udata *udata)
322{
323 struct i40iw_pd *iwpd;
324 struct i40iw_device *iwdev = to_iwdev(ibdev);
325 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
326 struct i40iw_alloc_pd_resp uresp;
327 struct i40iw_sc_pd *sc_pd;
328 struct i40iw_ucontext *ucontext;
329 u32 pd_id = 0;
330 int err;
331
332 if (iwdev->closing)
333 return ERR_PTR(-ENODEV);
334
335 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
336 iwdev->max_pd, &pd_id, &iwdev->next_pd);
337 if (err) {
338 i40iw_pr_err("alloc resource failed\n");
339 return ERR_PTR(err);
340 }
341
342 iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
343 if (!iwpd) {
344 err = -ENOMEM;
345 goto free_res;
346 }
347
348 sc_pd = &iwpd->sc_pd;
349
350 if (context) {
351 ucontext = to_ucontext(context);
352 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
353 memset(&uresp, 0, sizeof(uresp));
354 uresp.pd_id = pd_id;
355 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
356 err = -EFAULT;
357 goto error;
358 }
359 } else {
360 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
361 }
362
363 i40iw_add_pdusecount(iwpd);
364 return &iwpd->ibpd;
365error:
366 kfree(iwpd);
367free_res:
368 i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
369 return ERR_PTR(err);
370}
371
372
373
374
375
376static int i40iw_dealloc_pd(struct ib_pd *ibpd)
377{
378 struct i40iw_pd *iwpd = to_iwpd(ibpd);
379 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
380
381 i40iw_rem_pdusecount(iwpd, iwdev);
382 return 0;
383}
384
385
386
387
388
389
390
391static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
392 struct list_head *pbl_list)
393{
394 struct i40iw_pbl *iwpbl;
395
396 list_for_each_entry(iwpbl, pbl_list, list) {
397 if (iwpbl->user_base == va) {
398 iwpbl->on_list = false;
399 list_del(&iwpbl->list);
400 return iwpbl;
401 }
402 }
403 return NULL;
404}
405
406
407
408
409
410
411
412void i40iw_free_qp_resources(struct i40iw_device *iwdev,
413 struct i40iw_qp *iwqp,
414 u32 qp_num)
415{
416 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
417
418 i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
419 i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
420 if (qp_num)
421 i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
422 if (iwpbl->pbl_allocated)
423 i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc);
424 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
425 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
426 kfree(iwqp->kqp.wrid_mem);
427 iwqp->kqp.wrid_mem = NULL;
428 kfree(iwqp->allocated_buffer);
429}
430
431
432
433
434
435
436static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
437{
438 struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
439
440 ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
441}
442
443
444
445
446
447static int i40iw_destroy_qp(struct ib_qp *ibqp)
448{
449 struct i40iw_qp *iwqp = to_iwqp(ibqp);
450
451 iwqp->destroyed = 1;
452
453 if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
454 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
455
456 if (!iwqp->user_mode) {
457 if (iwqp->iwscq) {
458 i40iw_clean_cqes(iwqp, iwqp->iwscq);
459 if (iwqp->iwrcq != iwqp->iwscq)
460 i40iw_clean_cqes(iwqp, iwqp->iwrcq);
461 }
462 }
463
464 i40iw_rem_ref(&iwqp->ibqp);
465 return 0;
466}
467
468
469
470
471
472
473
474static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
475 struct i40iw_qp *iwqp,
476 struct i40iw_qp_init_info *init_info)
477{
478 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
479 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
480
481 iwqp->page = qpmr->sq_page;
482 init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
483 if (iwpbl->pbl_allocated) {
484 init_info->virtual_map = true;
485 init_info->sq_pa = qpmr->sq_pbl.idx;
486 init_info->rq_pa = qpmr->rq_pbl.idx;
487 } else {
488 init_info->sq_pa = qpmr->sq_pbl.addr;
489 init_info->rq_pa = qpmr->rq_pbl.addr;
490 }
491 return 0;
492}
493
494
495
496
497
498
499
500static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
501 struct i40iw_qp *iwqp,
502 struct i40iw_qp_init_info *info)
503{
504 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
505 u32 sqdepth, rqdepth;
506 u8 sqshift;
507 u32 size;
508 enum i40iw_status_code status;
509 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
510
511 i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
512 status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth);
513 if (status)
514 return -ENOMEM;
515
516 status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth);
517 if (status)
518 return -ENOMEM;
519
520 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
521 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
522
523 ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
524 if (!ukinfo->sq_wrtrk_array)
525 return -ENOMEM;
526
527 ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
528
529 size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
530 size += (I40IW_SHADOW_AREA_SIZE << 3);
531
532 status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
533 if (status) {
534 kfree(ukinfo->sq_wrtrk_array);
535 ukinfo->sq_wrtrk_array = NULL;
536 return -ENOMEM;
537 }
538
539 ukinfo->sq = mem->va;
540 info->sq_pa = mem->pa;
541
542 ukinfo->rq = &ukinfo->sq[sqdepth];
543 info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
544
545 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
546 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
547
548 ukinfo->sq_size = sqdepth >> sqshift;
549 ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT;
550 ukinfo->qp_id = iwqp->ibqp.qp_num;
551 return 0;
552}
553
554
555
556
557
558
559
560static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
561 struct ib_qp_init_attr *init_attr,
562 struct ib_udata *udata)
563{
564 struct i40iw_pd *iwpd = to_iwpd(ibpd);
565 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
566 struct i40iw_cqp *iwcqp = &iwdev->cqp;
567 struct i40iw_qp *iwqp;
568 struct i40iw_ucontext *ucontext;
569 struct i40iw_create_qp_req req;
570 struct i40iw_create_qp_resp uresp;
571 u32 qp_num = 0;
572 void *mem;
573 enum i40iw_status_code ret;
574 int err_code;
575 int sq_size;
576 int rq_size;
577 struct i40iw_sc_qp *qp;
578 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
579 struct i40iw_qp_init_info init_info;
580 struct i40iw_create_qp_info *qp_info;
581 struct i40iw_cqp_request *cqp_request;
582 struct cqp_commands_info *cqp_info;
583
584 struct i40iw_qp_host_ctx_info *ctx_info;
585 struct i40iwarp_offload_info *iwarp_info;
586 unsigned long flags;
587
588 if (iwdev->closing)
589 return ERR_PTR(-ENODEV);
590
591 if (init_attr->create_flags)
592 return ERR_PTR(-EINVAL);
593 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
594 init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
595
596 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
597 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
598
599 if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
600 init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
601
602 memset(&init_info, 0, sizeof(init_info));
603
604 sq_size = init_attr->cap.max_send_wr;
605 rq_size = init_attr->cap.max_recv_wr;
606
607 init_info.vsi = &iwdev->vsi;
608 init_info.qp_uk_init_info.sq_size = sq_size;
609 init_info.qp_uk_init_info.rq_size = rq_size;
610 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
611 init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
612 init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
613
614 mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
615 if (!mem)
616 return ERR_PTR(-ENOMEM);
617
618 iwqp = (struct i40iw_qp *)mem;
619 iwqp->allocated_buffer = mem;
620 qp = &iwqp->sc_qp;
621 qp->back_qp = (void *)iwqp;
622 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
623
624 iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
625
626 if (i40iw_allocate_dma_mem(dev->hw,
627 &iwqp->q2_ctx_mem,
628 I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
629 256)) {
630 i40iw_pr_err("dma_mem failed\n");
631 err_code = -ENOMEM;
632 goto error;
633 }
634
635 init_info.q2 = iwqp->q2_ctx_mem.va;
636 init_info.q2_pa = iwqp->q2_ctx_mem.pa;
637
638 init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
639 init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
640
641 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
642 &qp_num, &iwdev->next_qp);
643 if (err_code) {
644 i40iw_pr_err("qp resource\n");
645 goto error;
646 }
647
648 iwqp->iwdev = iwdev;
649 iwqp->iwpd = iwpd;
650 iwqp->ibqp.qp_num = qp_num;
651 qp = &iwqp->sc_qp;
652 iwqp->iwscq = to_iwcq(init_attr->send_cq);
653 iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
654
655 iwqp->host_ctx.va = init_info.host_ctx;
656 iwqp->host_ctx.pa = init_info.host_ctx_pa;
657 iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
658
659 init_info.pd = &iwpd->sc_pd;
660 init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
661 iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
662
663 if (init_attr->qp_type != IB_QPT_RC) {
664 err_code = -EINVAL;
665 goto error;
666 }
667 if (iwdev->push_mode)
668 i40iw_alloc_push_page(iwdev, qp);
669 if (udata) {
670 err_code = ib_copy_from_udata(&req, udata, sizeof(req));
671 if (err_code) {
672 i40iw_pr_err("ib_copy_from_data\n");
673 goto error;
674 }
675 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
676 iwqp->user_mode = 1;
677 ucontext = to_ucontext(ibpd->uobject->context);
678
679 if (req.user_wqe_buffers) {
680 struct i40iw_pbl *iwpbl;
681
682 spin_lock_irqsave(
683 &ucontext->qp_reg_mem_list_lock, flags);
684 iwpbl = i40iw_get_pbl(
685 (unsigned long)req.user_wqe_buffers,
686 &ucontext->qp_reg_mem_list);
687 spin_unlock_irqrestore(
688 &ucontext->qp_reg_mem_list_lock, flags);
689
690 if (!iwpbl) {
691 err_code = -ENODATA;
692 i40iw_pr_err("no pbl info\n");
693 goto error;
694 }
695 memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl));
696 }
697 err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
698 } else {
699 err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
700 }
701
702 if (err_code) {
703 i40iw_pr_err("setup qp failed\n");
704 goto error;
705 }
706
707 init_info.type = I40IW_QP_TYPE_IWARP;
708 ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
709 if (ret) {
710 err_code = -EPROTO;
711 i40iw_pr_err("qp_init fail\n");
712 goto error;
713 }
714 ctx_info = &iwqp->ctx_info;
715 iwarp_info = &iwqp->iwarp_info;
716 iwarp_info->rd_enable = true;
717 iwarp_info->wr_rdresp_en = true;
718 if (!iwqp->user_mode) {
719 iwarp_info->fast_reg_en = true;
720 iwarp_info->priv_mode_en = true;
721 }
722 iwarp_info->ddp_ver = 1;
723 iwarp_info->rdmap_ver = 1;
724
725 ctx_info->iwarp_info_valid = true;
726 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
727 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
728 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
729 ctx_info->push_mode_en = false;
730 } else {
731 ctx_info->push_mode_en = true;
732 ctx_info->push_idx = qp->push_idx;
733 }
734
735 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
736 (u64 *)iwqp->host_ctx.va,
737 ctx_info);
738 ctx_info->iwarp_info_valid = false;
739 cqp_request = i40iw_get_cqp_request(iwcqp, true);
740 if (!cqp_request) {
741 err_code = -ENOMEM;
742 goto error;
743 }
744 cqp_info = &cqp_request->info;
745 qp_info = &cqp_request->info.in.u.qp_create.info;
746
747 memset(qp_info, 0, sizeof(*qp_info));
748
749 qp_info->cq_num_valid = true;
750 qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
751
752 cqp_info->cqp_cmd = OP_QP_CREATE;
753 cqp_info->post_sq = 1;
754 cqp_info->in.u.qp_create.qp = qp;
755 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
756 ret = i40iw_handle_cqp_op(iwdev, cqp_request);
757 if (ret) {
758 i40iw_pr_err("CQP-OP QP create fail");
759 err_code = -EACCES;
760 goto error;
761 }
762
763 i40iw_add_ref(&iwqp->ibqp);
764 spin_lock_init(&iwqp->lock);
765 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
766 iwdev->qp_table[qp_num] = iwqp;
767 i40iw_add_pdusecount(iwqp->iwpd);
768 i40iw_add_devusecount(iwdev);
769 if (udata) {
770 memset(&uresp, 0, sizeof(uresp));
771 uresp.actual_sq_size = sq_size;
772 uresp.actual_rq_size = rq_size;
773 uresp.qp_id = qp_num;
774 uresp.push_idx = qp->push_idx;
775 err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
776 if (err_code) {
777 i40iw_pr_err("copy_to_udata failed\n");
778 i40iw_destroy_qp(&iwqp->ibqp);
779
780 return ERR_PTR(err_code);
781 }
782 }
783 init_completion(&iwqp->sq_drained);
784 init_completion(&iwqp->rq_drained);
785
786 return &iwqp->ibqp;
787error:
788 i40iw_free_qp_resources(iwdev, iwqp, qp_num);
789 return ERR_PTR(err_code);
790}
791
792
793
794
795
796
797
798
799static int i40iw_query_qp(struct ib_qp *ibqp,
800 struct ib_qp_attr *attr,
801 int attr_mask,
802 struct ib_qp_init_attr *init_attr)
803{
804 struct i40iw_qp *iwqp = to_iwqp(ibqp);
805 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
806
807 attr->qp_access_flags = 0;
808 attr->cap.max_send_wr = qp->qp_uk.sq_size;
809 attr->cap.max_recv_wr = qp->qp_uk.rq_size;
810 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
811 attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
812 attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
813 attr->port_num = 1;
814 init_attr->event_handler = iwqp->ibqp.event_handler;
815 init_attr->qp_context = iwqp->ibqp.qp_context;
816 init_attr->send_cq = iwqp->ibqp.send_cq;
817 init_attr->recv_cq = iwqp->ibqp.recv_cq;
818 init_attr->srq = iwqp->ibqp.srq;
819 init_attr->cap = attr->cap;
820 init_attr->port_num = 1;
821 return 0;
822}
823
824
825
826
827
828
829
830
831void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
832 struct i40iw_modify_qp_info *info, bool wait)
833{
834 struct i40iw_cqp_request *cqp_request;
835 struct cqp_commands_info *cqp_info;
836 struct i40iw_modify_qp_info *m_info;
837 struct i40iw_gen_ae_info ae_info;
838
839 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
840 if (!cqp_request)
841 return;
842
843 cqp_info = &cqp_request->info;
844 m_info = &cqp_info->in.u.qp_modify.info;
845 memcpy(m_info, info, sizeof(*m_info));
846 cqp_info->cqp_cmd = OP_QP_MODIFY;
847 cqp_info->post_sq = 1;
848 cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
849 cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
850 if (!i40iw_handle_cqp_op(iwdev, cqp_request))
851 return;
852
853 switch (m_info->next_iwarp_state) {
854 case I40IW_QP_STATE_RTS:
855 if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE)
856 i40iw_send_reset(iwqp->cm_node);
857
858 case I40IW_QP_STATE_IDLE:
859 case I40IW_QP_STATE_TERMINATE:
860 case I40IW_QP_STATE_CLOSING:
861 ae_info.ae_code = I40IW_AE_BAD_CLOSE;
862 ae_info.ae_source = 0;
863 i40iw_gen_ae(iwdev, &iwqp->sc_qp, &ae_info, false);
864 break;
865 case I40IW_QP_STATE_ERROR:
866 default:
867 break;
868 }
869}
870
871
872
873
874
875
876
877
878int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
879 int attr_mask, struct ib_udata *udata)
880{
881 struct i40iw_qp *iwqp = to_iwqp(ibqp);
882 struct i40iw_device *iwdev = iwqp->iwdev;
883 struct i40iw_qp_host_ctx_info *ctx_info;
884 struct i40iwarp_offload_info *iwarp_info;
885 struct i40iw_modify_qp_info info;
886 u8 issue_modify_qp = 0;
887 u8 dont_wait = 0;
888 u32 err;
889 unsigned long flags;
890
891 memset(&info, 0, sizeof(info));
892 ctx_info = &iwqp->ctx_info;
893 iwarp_info = &iwqp->iwarp_info;
894
895 spin_lock_irqsave(&iwqp->lock, flags);
896
897 if (attr_mask & IB_QP_STATE) {
898 if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
899 err = -EINVAL;
900 goto exit;
901 }
902
903 switch (attr->qp_state) {
904 case IB_QPS_INIT:
905 case IB_QPS_RTR:
906 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
907 err = -EINVAL;
908 goto exit;
909 }
910 if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
911 info.next_iwarp_state = I40IW_QP_STATE_IDLE;
912 issue_modify_qp = 1;
913 }
914 break;
915 case IB_QPS_RTS:
916 if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
917 (!iwqp->cm_id)) {
918 err = -EINVAL;
919 goto exit;
920 }
921
922 issue_modify_qp = 1;
923 iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
924 iwqp->hte_added = 1;
925 info.next_iwarp_state = I40IW_QP_STATE_RTS;
926 info.tcp_ctx_valid = true;
927 info.ord_valid = true;
928 info.arp_cache_idx_valid = true;
929 info.cq_num_valid = true;
930 break;
931 case IB_QPS_SQD:
932 if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
933 err = 0;
934 goto exit;
935 }
936 if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
937 (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
938 err = 0;
939 goto exit;
940 }
941 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
942 err = -EINVAL;
943 goto exit;
944 }
945 info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
946 issue_modify_qp = 1;
947 break;
948 case IB_QPS_SQE:
949 if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
950 err = -EINVAL;
951 goto exit;
952 }
953 info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
954 issue_modify_qp = 1;
955 break;
956 case IB_QPS_ERR:
957 case IB_QPS_RESET:
958 if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
959 err = -EINVAL;
960 goto exit;
961 }
962 if (iwqp->sc_qp.term_flags)
963 i40iw_terminate_del_timer(&iwqp->sc_qp);
964 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
965 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
966 iwdev->iw_status &&
967 (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
968 info.reset_tcp_conn = true;
969 else
970 dont_wait = 1;
971 issue_modify_qp = 1;
972 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
973 break;
974 default:
975 err = -EINVAL;
976 goto exit;
977 }
978
979 iwqp->ibqp_state = attr->qp_state;
980
981 }
982 if (attr_mask & IB_QP_ACCESS_FLAGS) {
983 ctx_info->iwarp_info_valid = true;
984 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
985 iwarp_info->wr_rdresp_en = true;
986 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
987 iwarp_info->wr_rdresp_en = true;
988 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
989 iwarp_info->rd_enable = true;
990 if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
991 iwarp_info->bind_en = true;
992
993 if (iwqp->user_mode) {
994 iwarp_info->rd_enable = true;
995 iwarp_info->wr_rdresp_en = true;
996 iwarp_info->priv_mode_en = false;
997 }
998 }
999
1000 if (ctx_info->iwarp_info_valid) {
1001 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1002 int ret;
1003
1004 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1005 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1006 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
1007 (u64 *)iwqp->host_ctx.va,
1008 ctx_info);
1009 if (ret) {
1010 i40iw_pr_err("setting QP context\n");
1011 err = -EINVAL;
1012 goto exit;
1013 }
1014 }
1015
1016 spin_unlock_irqrestore(&iwqp->lock, flags);
1017
1018 if (issue_modify_qp) {
1019 i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
1020
1021 spin_lock_irqsave(&iwqp->lock, flags);
1022 iwqp->iwarp_state = info.next_iwarp_state;
1023 spin_unlock_irqrestore(&iwqp->lock, flags);
1024 }
1025
1026 if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
1027 if (dont_wait) {
1028 if (iwqp->cm_id && iwqp->hw_tcp_state) {
1029 spin_lock_irqsave(&iwqp->lock, flags);
1030 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
1031 iwqp->last_aeq = I40IW_AE_RESET_SENT;
1032 spin_unlock_irqrestore(&iwqp->lock, flags);
1033 i40iw_cm_disconn(iwqp);
1034 }
1035 } else {
1036 spin_lock_irqsave(&iwqp->lock, flags);
1037 if (iwqp->cm_id) {
1038 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
1039 iwqp->cm_id->add_ref(iwqp->cm_id);
1040 i40iw_schedule_cm_timer(iwqp->cm_node,
1041 (struct i40iw_puda_buf *)iwqp,
1042 I40IW_TIMER_TYPE_CLOSE, 1, 0);
1043 }
1044 }
1045 spin_unlock_irqrestore(&iwqp->lock, flags);
1046 }
1047 }
1048 return 0;
1049exit:
1050 spin_unlock_irqrestore(&iwqp->lock, flags);
1051 return err;
1052}
1053
1054
1055
1056
1057
1058
1059static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
1060{
1061 struct i40iw_sc_cq *cq = &iwcq->sc_cq;
1062
1063 if (!iwcq->user_mode)
1064 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
1065 i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
1066}
1067
1068
1069
1070
1071
1072
1073void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
1074{
1075 enum i40iw_status_code status;
1076 struct i40iw_cqp_request *cqp_request;
1077 struct cqp_commands_info *cqp_info;
1078
1079 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1080 if (!cqp_request)
1081 return;
1082
1083 cqp_info = &cqp_request->info;
1084
1085 cqp_info->cqp_cmd = OP_CQ_DESTROY;
1086 cqp_info->post_sq = 1;
1087 cqp_info->in.u.cq_destroy.cq = cq;
1088 cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
1089 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1090 if (status)
1091 i40iw_pr_err("CQP-OP Destroy QP fail");
1092}
1093
1094
1095
1096
1097
1098static int i40iw_destroy_cq(struct ib_cq *ib_cq)
1099{
1100 struct i40iw_cq *iwcq;
1101 struct i40iw_device *iwdev;
1102 struct i40iw_sc_cq *cq;
1103
1104 if (!ib_cq) {
1105 i40iw_pr_err("ib_cq == NULL\n");
1106 return 0;
1107 }
1108
1109 iwcq = to_iwcq(ib_cq);
1110 iwdev = to_iwdev(ib_cq->device);
1111 cq = &iwcq->sc_cq;
1112 i40iw_cq_wq_destroy(iwdev, cq);
1113 cq_free_resources(iwdev, iwcq);
1114 kfree(iwcq);
1115 i40iw_rem_devusecount(iwdev);
1116 return 0;
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1127 const struct ib_cq_init_attr *attr,
1128 struct ib_ucontext *context,
1129 struct ib_udata *udata)
1130{
1131 struct i40iw_device *iwdev = to_iwdev(ibdev);
1132 struct i40iw_cq *iwcq;
1133 struct i40iw_pbl *iwpbl;
1134 u32 cq_num = 0;
1135 struct i40iw_sc_cq *cq;
1136 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1137 struct i40iw_cq_init_info info;
1138 enum i40iw_status_code status;
1139 struct i40iw_cqp_request *cqp_request;
1140 struct cqp_commands_info *cqp_info;
1141 struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
1142 unsigned long flags;
1143 int err_code;
1144 int entries = attr->cqe;
1145
1146 if (iwdev->closing)
1147 return ERR_PTR(-ENODEV);
1148
1149 if (entries > iwdev->max_cqe)
1150 return ERR_PTR(-EINVAL);
1151
1152 iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
1153 if (!iwcq)
1154 return ERR_PTR(-ENOMEM);
1155
1156 memset(&info, 0, sizeof(info));
1157
1158 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
1159 iwdev->max_cq, &cq_num,
1160 &iwdev->next_cq);
1161 if (err_code)
1162 goto error;
1163
1164 cq = &iwcq->sc_cq;
1165 cq->back_cq = (void *)iwcq;
1166 spin_lock_init(&iwcq->lock);
1167
1168 info.dev = dev;
1169 ukinfo->cq_size = max(entries, 4);
1170 ukinfo->cq_id = cq_num;
1171 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
1172 info.ceqe_mask = 0;
1173 if (attr->comp_vector < iwdev->ceqs_count)
1174 info.ceq_id = attr->comp_vector;
1175 info.ceq_id_valid = true;
1176 info.ceqe_mask = 1;
1177 info.type = I40IW_CQ_TYPE_IWARP;
1178 if (context) {
1179 struct i40iw_ucontext *ucontext;
1180 struct i40iw_create_cq_req req;
1181 struct i40iw_cq_mr *cqmr;
1182
1183 memset(&req, 0, sizeof(req));
1184 iwcq->user_mode = true;
1185 ucontext = to_ucontext(context);
1186 if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) {
1187 err_code = -EFAULT;
1188 goto cq_free_resources;
1189 }
1190
1191 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1192 iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
1193 &ucontext->cq_reg_mem_list);
1194 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1195 if (!iwpbl) {
1196 err_code = -EPROTO;
1197 goto cq_free_resources;
1198 }
1199
1200 iwcq->iwpbl = iwpbl;
1201 iwcq->cq_mem_size = 0;
1202 cqmr = &iwpbl->cq_mr;
1203 info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
1204 if (iwpbl->pbl_allocated) {
1205 info.virtual_map = true;
1206 info.pbl_chunk_size = 1;
1207 info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
1208 } else {
1209 info.cq_base_pa = cqmr->cq_pbl.addr;
1210 }
1211 } else {
1212
1213 int rsize;
1214 int shadow;
1215
1216 rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
1217 rsize = round_up(rsize, 256);
1218 shadow = I40IW_SHADOW_AREA_SIZE << 3;
1219 status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
1220 rsize + shadow, 256);
1221 if (status) {
1222 err_code = -ENOMEM;
1223 goto cq_free_resources;
1224 }
1225 ukinfo->cq_base = iwcq->kmem.va;
1226 info.cq_base_pa = iwcq->kmem.pa;
1227 info.shadow_area_pa = info.cq_base_pa + rsize;
1228 ukinfo->shadow_area = iwcq->kmem.va + rsize;
1229 }
1230
1231 if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
1232 i40iw_pr_err("init cq fail\n");
1233 err_code = -EPROTO;
1234 goto cq_free_resources;
1235 }
1236
1237 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1238 if (!cqp_request) {
1239 err_code = -ENOMEM;
1240 goto cq_free_resources;
1241 }
1242
1243 cqp_info = &cqp_request->info;
1244 cqp_info->cqp_cmd = OP_CQ_CREATE;
1245 cqp_info->post_sq = 1;
1246 cqp_info->in.u.cq_create.cq = cq;
1247 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
1248 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1249 if (status) {
1250 i40iw_pr_err("CQP-OP Create QP fail");
1251 err_code = -EPROTO;
1252 goto cq_free_resources;
1253 }
1254
1255 if (context) {
1256 struct i40iw_create_cq_resp resp;
1257
1258 memset(&resp, 0, sizeof(resp));
1259 resp.cq_id = info.cq_uk_init_info.cq_id;
1260 resp.cq_size = info.cq_uk_init_info.cq_size;
1261 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1262 i40iw_pr_err("copy to user data\n");
1263 err_code = -EPROTO;
1264 goto cq_destroy;
1265 }
1266 }
1267
1268 i40iw_add_devusecount(iwdev);
1269 return (struct ib_cq *)iwcq;
1270
1271cq_destroy:
1272 i40iw_cq_wq_destroy(iwdev, cq);
1273cq_free_resources:
1274 cq_free_resources(iwdev, iwcq);
1275error:
1276 kfree(iwcq);
1277 return ERR_PTR(err_code);
1278}
1279
1280
1281
1282
1283
1284static inline u16 i40iw_get_user_access(int acc)
1285{
1286 u16 access = 0;
1287
1288 access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
1289 access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
1290 access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
1291 access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
1292 return access;
1293}
1294
1295
1296
1297
1298
1299
1300static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
1301{
1302 u32 stag_idx;
1303
1304 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1305 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
1306 i40iw_rem_devusecount(iwdev);
1307}
1308
1309
1310
1311
1312
1313static u32 i40iw_create_stag(struct i40iw_device *iwdev)
1314{
1315 u32 stag = 0;
1316 u32 stag_index = 0;
1317 u32 next_stag_index;
1318 u32 driver_key;
1319 u32 random;
1320 u8 consumer_key;
1321 int ret;
1322
1323 get_random_bytes(&random, sizeof(random));
1324 consumer_key = (u8)random;
1325
1326 driver_key = random & ~iwdev->mr_stagmask;
1327 next_stag_index = (random & iwdev->mr_stagmask) >> 8;
1328 next_stag_index %= iwdev->max_mr;
1329
1330 ret = i40iw_alloc_resource(iwdev,
1331 iwdev->allocated_mrs, iwdev->max_mr,
1332 &stag_index, &next_stag_index);
1333 if (!ret) {
1334 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
1335 stag |= driver_key;
1336 stag += (u32)consumer_key;
1337 i40iw_add_devusecount(iwdev);
1338 }
1339 return stag;
1340}
1341
1342
1343
1344
1345
1346
1347
1348static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
1349 struct i40iw_pble_info **pinfo,
1350 u32 *idx)
1351{
1352 *idx += 1;
1353 if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
1354 return ++pbl;
1355 *idx = 0;
1356 (*pinfo)++;
1357 return (u64 *)(*pinfo)->addr;
1358}
1359
1360
1361
1362
1363
1364
1365
1366static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1367 u64 *pbl,
1368 enum i40iw_pble_level level)
1369{
1370 struct ib_umem *region = iwmr->region;
1371 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1372 int chunk_pages, entry, i;
1373 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1374 struct i40iw_pble_info *pinfo;
1375 struct scatterlist *sg;
1376 u64 pg_addr = 0;
1377 u32 idx = 0;
1378
1379 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
1380
1381 for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
1382 chunk_pages = sg_dma_len(sg) >> region->page_shift;
1383 if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
1384 !iwpbl->qp_mr.sq_page)
1385 iwpbl->qp_mr.sq_page = sg_page(sg);
1386 for (i = 0; i < chunk_pages; i++) {
1387 pg_addr = sg_dma_address(sg) +
1388 (i << region->page_shift);
1389
1390 if ((entry + i) == 0)
1391 *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
1392 else if (!(pg_addr & ~iwmr->page_msk))
1393 *pbl = cpu_to_le64(pg_addr);
1394 else
1395 continue;
1396 pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
1397 }
1398 }
1399}
1400
1401
1402
1403
1404
1405
1406static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
1407{
1408 struct vm_area_struct *vma;
1409 struct hstate *h;
1410
1411 down_read(¤t->mm->mmap_sem);
1412 vma = find_vma(current->mm, addr);
1413 if (vma && is_vm_hugetlb_page(vma)) {
1414 h = hstate_vma(vma);
1415 if (huge_page_size(h) == 0x200000) {
1416 iwmr->page_size = huge_page_size(h);
1417 iwmr->page_msk = huge_page_mask(h);
1418 }
1419 }
1420 up_read(¤t->mm->mmap_sem);
1421}
1422
1423
1424
1425
1426
1427
1428
1429
1430static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1431{
1432 u32 pg_idx;
1433
1434 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1435 if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
1436 return false;
1437 }
1438 return true;
1439}
1440
1441
1442
1443
1444
1445
1446static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
1447{
1448 struct i40iw_pble_level2 *lvl2 = &palloc->level2;
1449 struct i40iw_pble_info *leaf = lvl2->leaf;
1450 u64 *arr = NULL;
1451 u64 *start_addr = NULL;
1452 int i;
1453 bool ret;
1454
1455 if (palloc->level == I40IW_LEVEL_1) {
1456 arr = (u64 *)palloc->level1.addr;
1457 ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
1458 return ret;
1459 }
1460
1461 start_addr = (u64 *)leaf->addr;
1462
1463 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1464 arr = (u64 *)leaf->addr;
1465 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1466 return false;
1467 ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
1468 if (!ret)
1469 return false;
1470 }
1471
1472 return true;
1473}
1474
1475
1476
1477
1478
1479
1480
1481static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1482 struct i40iw_mr *iwmr,
1483 bool use_pbles)
1484{
1485 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1486 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1487 struct i40iw_pble_info *pinfo;
1488 u64 *pbl;
1489 enum i40iw_status_code status;
1490 enum i40iw_pble_level level = I40IW_LEVEL_1;
1491
1492 if (use_pbles) {
1493 mutex_lock(&iwdev->pbl_mutex);
1494 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1495 mutex_unlock(&iwdev->pbl_mutex);
1496 if (status)
1497 return -ENOMEM;
1498
1499 iwpbl->pbl_allocated = true;
1500 level = palloc->level;
1501 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
1502 pbl = (u64 *)pinfo->addr;
1503 } else {
1504 pbl = iwmr->pgaddrmem;
1505 }
1506
1507 i40iw_copy_user_pgaddrs(iwmr, pbl, level);
1508
1509 if (use_pbles)
1510 iwmr->pgaddrmem[0] = *pbl;
1511
1512 return 0;
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1523 struct i40iw_mem_reg_req *req,
1524 struct i40iw_pbl *iwpbl,
1525 bool use_pbles)
1526{
1527 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1528 struct i40iw_mr *iwmr = iwpbl->iwmr;
1529 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
1530 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
1531 struct i40iw_hmc_pble *hmc_p;
1532 u64 *arr = iwmr->pgaddrmem;
1533 u32 pg_size;
1534 int err;
1535 int total;
1536 bool ret = true;
1537
1538 total = req->sq_pages + req->rq_pages + req->cq_pages;
1539 pg_size = iwmr->page_size;
1540
1541 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1542 if (err)
1543 return err;
1544
1545 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
1546 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1547 iwpbl->pbl_allocated = false;
1548 return -ENOMEM;
1549 }
1550
1551 if (use_pbles)
1552 arr = (u64 *)palloc->level1.addr;
1553
1554 if (iwmr->type == IW_MEMREG_TYPE_QP) {
1555 hmc_p = &qpmr->sq_pbl;
1556 qpmr->shadow = (dma_addr_t)arr[total];
1557
1558 if (use_pbles) {
1559 ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
1560 if (ret)
1561 ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
1562 }
1563
1564 if (!ret) {
1565 hmc_p->idx = palloc->level1.idx;
1566 hmc_p = &qpmr->rq_pbl;
1567 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1568 } else {
1569 hmc_p->addr = arr[0];
1570 hmc_p = &qpmr->rq_pbl;
1571 hmc_p->addr = arr[req->sq_pages];
1572 }
1573 } else {
1574 hmc_p = &cqmr->cq_pbl;
1575 cqmr->shadow = (dma_addr_t)arr[total];
1576
1577 if (use_pbles)
1578 ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
1579
1580 if (!ret)
1581 hmc_p->idx = palloc->level1.idx;
1582 else
1583 hmc_p->addr = arr[0];
1584 }
1585
1586 if (use_pbles && ret) {
1587 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1588 iwpbl->pbl_allocated = false;
1589 }
1590
1591 return err;
1592}
1593
1594
1595
1596
1597
1598
1599static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
1600{
1601 struct i40iw_allocate_stag_info *info;
1602 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1603 enum i40iw_status_code status;
1604 int err = 0;
1605 struct i40iw_cqp_request *cqp_request;
1606 struct cqp_commands_info *cqp_info;
1607
1608 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1609 if (!cqp_request)
1610 return -ENOMEM;
1611
1612 cqp_info = &cqp_request->info;
1613 info = &cqp_info->in.u.alloc_stag.info;
1614 memset(info, 0, sizeof(*info));
1615 info->page_size = PAGE_SIZE;
1616 info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1617 info->pd_id = iwpd->sc_pd.pd_id;
1618 info->total_len = iwmr->length;
1619 info->remote_access = true;
1620 cqp_info->cqp_cmd = OP_ALLOC_STAG;
1621 cqp_info->post_sq = 1;
1622 cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
1623 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
1624
1625 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1626 if (status) {
1627 err = -ENOMEM;
1628 i40iw_pr_err("CQP-OP MR Reg fail");
1629 }
1630 return err;
1631}
1632
1633
1634
1635
1636
1637
1638
1639static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
1640 enum ib_mr_type mr_type,
1641 u32 max_num_sg)
1642{
1643 struct i40iw_pd *iwpd = to_iwpd(pd);
1644 struct i40iw_device *iwdev = to_iwdev(pd->device);
1645 struct i40iw_pble_alloc *palloc;
1646 struct i40iw_pbl *iwpbl;
1647 struct i40iw_mr *iwmr;
1648 enum i40iw_status_code status;
1649 u32 stag;
1650 int err_code = -ENOMEM;
1651
1652 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1653 if (!iwmr)
1654 return ERR_PTR(-ENOMEM);
1655
1656 stag = i40iw_create_stag(iwdev);
1657 if (!stag) {
1658 err_code = -EOVERFLOW;
1659 goto err;
1660 }
1661 stag &= ~I40IW_CQPSQ_STAG_KEY_MASK;
1662 iwmr->stag = stag;
1663 iwmr->ibmr.rkey = stag;
1664 iwmr->ibmr.lkey = stag;
1665 iwmr->ibmr.pd = pd;
1666 iwmr->ibmr.device = pd->device;
1667 iwpbl = &iwmr->iwpbl;
1668 iwpbl->iwmr = iwmr;
1669 iwmr->type = IW_MEMREG_TYPE_MEM;
1670 palloc = &iwpbl->pble_alloc;
1671 iwmr->page_cnt = max_num_sg;
1672 mutex_lock(&iwdev->pbl_mutex);
1673 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1674 mutex_unlock(&iwdev->pbl_mutex);
1675 if (status)
1676 goto err1;
1677
1678 if (palloc->level != I40IW_LEVEL_1)
1679 goto err2;
1680 err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
1681 if (err_code)
1682 goto err2;
1683 iwpbl->pbl_allocated = true;
1684 i40iw_add_pdusecount(iwpd);
1685 return &iwmr->ibmr;
1686err2:
1687 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1688err1:
1689 i40iw_free_stag(iwdev, stag);
1690err:
1691 kfree(iwmr);
1692 return ERR_PTR(err_code);
1693}
1694
1695
1696
1697
1698
1699
1700static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
1701{
1702 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1703 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1704 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1705 u64 *pbl;
1706
1707 if (unlikely(iwmr->npages == iwmr->page_cnt))
1708 return -ENOMEM;
1709
1710 pbl = (u64 *)palloc->level1.addr;
1711 pbl[iwmr->npages++] = cpu_to_le64(addr);
1712 return 0;
1713}
1714
1715
1716
1717
1718
1719
1720
1721static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
1722 int sg_nents, unsigned int *sg_offset)
1723{
1724 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1725
1726 iwmr->npages = 0;
1727 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
1728}
1729
1730
1731
1732
1733
1734static void i40iw_drain_sq(struct ib_qp *ibqp)
1735{
1736 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1737 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1738
1739 if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
1740 wait_for_completion(&iwqp->sq_drained);
1741}
1742
1743
1744
1745
1746
1747static void i40iw_drain_rq(struct ib_qp *ibqp)
1748{
1749 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1750 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1751
1752 if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
1753 wait_for_completion(&iwqp->rq_drained);
1754}
1755
1756
1757
1758
1759
1760
1761
1762static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
1763 struct i40iw_mr *iwmr,
1764 u16 access)
1765{
1766 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1767 struct i40iw_reg_ns_stag_info *stag_info;
1768 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1769 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1770 enum i40iw_status_code status;
1771 int err = 0;
1772 struct i40iw_cqp_request *cqp_request;
1773 struct cqp_commands_info *cqp_info;
1774
1775 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1776 if (!cqp_request)
1777 return -ENOMEM;
1778
1779 cqp_info = &cqp_request->info;
1780 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
1781 memset(stag_info, 0, sizeof(*stag_info));
1782 stag_info->va = (void *)(unsigned long)iwpbl->user_base;
1783 stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1784 stag_info->stag_key = (u8)iwmr->stag;
1785 stag_info->total_len = iwmr->length;
1786 stag_info->access_rights = access;
1787 stag_info->pd_id = iwpd->sc_pd.pd_id;
1788 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
1789 stag_info->page_size = iwmr->page_size;
1790
1791 if (iwpbl->pbl_allocated) {
1792 if (palloc->level == I40IW_LEVEL_1) {
1793 stag_info->first_pm_pbl_index = palloc->level1.idx;
1794 stag_info->chunk_size = 1;
1795 } else {
1796 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
1797 stag_info->chunk_size = 3;
1798 }
1799 } else {
1800 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
1801 }
1802
1803 cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
1804 cqp_info->post_sq = 1;
1805 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
1806 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
1807
1808 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1809 if (status) {
1810 err = -ENOMEM;
1811 i40iw_pr_err("CQP-OP MR Reg fail");
1812 }
1813 return err;
1814}
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1826 u64 start,
1827 u64 length,
1828 u64 virt,
1829 int acc,
1830 struct ib_udata *udata)
1831{
1832 struct i40iw_pd *iwpd = to_iwpd(pd);
1833 struct i40iw_device *iwdev = to_iwdev(pd->device);
1834 struct i40iw_ucontext *ucontext;
1835 struct i40iw_pble_alloc *palloc;
1836 struct i40iw_pbl *iwpbl;
1837 struct i40iw_mr *iwmr;
1838 struct ib_umem *region;
1839 struct i40iw_mem_reg_req req;
1840 u64 pbl_depth = 0;
1841 u32 stag = 0;
1842 u16 access;
1843 u64 region_length;
1844 bool use_pbles = false;
1845 unsigned long flags;
1846 int err = -ENOSYS;
1847 int ret;
1848 int pg_shift;
1849
1850 if (iwdev->closing)
1851 return ERR_PTR(-ENODEV);
1852
1853 if (length > I40IW_MAX_MR_SIZE)
1854 return ERR_PTR(-EINVAL);
1855 region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
1856 if (IS_ERR(region))
1857 return (struct ib_mr *)region;
1858
1859 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
1860 ib_umem_release(region);
1861 return ERR_PTR(-EFAULT);
1862 }
1863
1864 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1865 if (!iwmr) {
1866 ib_umem_release(region);
1867 return ERR_PTR(-ENOMEM);
1868 }
1869
1870 iwpbl = &iwmr->iwpbl;
1871 iwpbl->iwmr = iwmr;
1872 iwmr->region = region;
1873 iwmr->ibmr.pd = pd;
1874 iwmr->ibmr.device = pd->device;
1875 ucontext = to_ucontext(pd->uobject->context);
1876
1877 iwmr->page_size = PAGE_SIZE;
1878 iwmr->page_msk = PAGE_MASK;
1879
1880 if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
1881 i40iw_set_hugetlb_values(start, iwmr);
1882
1883 region_length = region->length + (start & (iwmr->page_size - 1));
1884 pg_shift = ffs(iwmr->page_size) - 1;
1885 pbl_depth = region_length >> pg_shift;
1886 pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
1887 iwmr->length = region->length;
1888
1889 iwpbl->user_base = virt;
1890 palloc = &iwpbl->pble_alloc;
1891
1892 iwmr->type = req.reg_type;
1893 iwmr->page_cnt = (u32)pbl_depth;
1894
1895 switch (req.reg_type) {
1896 case IW_MEMREG_TYPE_QP:
1897 use_pbles = ((req.sq_pages + req.rq_pages) > 2);
1898 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1899 if (err)
1900 goto error;
1901 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1902 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
1903 iwpbl->on_list = true;
1904 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1905 break;
1906 case IW_MEMREG_TYPE_CQ:
1907 use_pbles = (req.cq_pages > 1);
1908 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1909 if (err)
1910 goto error;
1911
1912 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1913 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
1914 iwpbl->on_list = true;
1915 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1916 break;
1917 case IW_MEMREG_TYPE_MEM:
1918 use_pbles = (iwmr->page_cnt != 1);
1919 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1920
1921 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1922 if (err)
1923 goto error;
1924
1925 if (use_pbles) {
1926 ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
1927 if (ret) {
1928 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1929 iwpbl->pbl_allocated = false;
1930 }
1931 }
1932
1933 access |= i40iw_get_user_access(acc);
1934 stag = i40iw_create_stag(iwdev);
1935 if (!stag) {
1936 err = -ENOMEM;
1937 goto error;
1938 }
1939
1940 iwmr->stag = stag;
1941 iwmr->ibmr.rkey = stag;
1942 iwmr->ibmr.lkey = stag;
1943
1944 err = i40iw_hwreg_mr(iwdev, iwmr, access);
1945 if (err) {
1946 i40iw_free_stag(iwdev, stag);
1947 goto error;
1948 }
1949
1950 break;
1951 default:
1952 goto error;
1953 }
1954
1955 iwmr->type = req.reg_type;
1956 if (req.reg_type == IW_MEMREG_TYPE_MEM)
1957 i40iw_add_pdusecount(iwpd);
1958 return &iwmr->ibmr;
1959
1960error:
1961 if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
1962 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1963 ib_umem_release(region);
1964 kfree(iwmr);
1965 return ERR_PTR(err);
1966}
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
1977 u64 addr,
1978 u64 size,
1979 int acc,
1980 u64 *iova_start)
1981{
1982 struct i40iw_pd *iwpd = to_iwpd(pd);
1983 struct i40iw_device *iwdev = to_iwdev(pd->device);
1984 struct i40iw_pbl *iwpbl;
1985 struct i40iw_mr *iwmr;
1986 enum i40iw_status_code status;
1987 u32 stag;
1988 u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1989 int ret;
1990
1991 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1992 if (!iwmr)
1993 return ERR_PTR(-ENOMEM);
1994 iwmr->ibmr.pd = pd;
1995 iwmr->ibmr.device = pd->device;
1996 iwpbl = &iwmr->iwpbl;
1997 iwpbl->iwmr = iwmr;
1998 iwmr->type = IW_MEMREG_TYPE_MEM;
1999 iwpbl->user_base = *iova_start;
2000 stag = i40iw_create_stag(iwdev);
2001 if (!stag) {
2002 ret = -EOVERFLOW;
2003 goto err;
2004 }
2005 access |= i40iw_get_user_access(acc);
2006 iwmr->stag = stag;
2007 iwmr->ibmr.rkey = stag;
2008 iwmr->ibmr.lkey = stag;
2009 iwmr->page_cnt = 1;
2010 iwmr->pgaddrmem[0] = addr;
2011 iwmr->length = size;
2012 status = i40iw_hwreg_mr(iwdev, iwmr, access);
2013 if (status) {
2014 i40iw_free_stag(iwdev, stag);
2015 ret = -ENOMEM;
2016 goto err;
2017 }
2018
2019 i40iw_add_pdusecount(iwpd);
2020 return &iwmr->ibmr;
2021 err:
2022 kfree(iwmr);
2023 return ERR_PTR(ret);
2024}
2025
2026
2027
2028
2029
2030
2031static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
2032{
2033 u64 kva = 0;
2034
2035 return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
2036}
2037
2038
2039
2040
2041
2042
2043static void i40iw_del_memlist(struct i40iw_mr *iwmr,
2044 struct i40iw_ucontext *ucontext)
2045{
2046 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
2047 unsigned long flags;
2048
2049 switch (iwmr->type) {
2050 case IW_MEMREG_TYPE_CQ:
2051 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2052 if (iwpbl->on_list) {
2053 iwpbl->on_list = false;
2054 list_del(&iwpbl->list);
2055 }
2056 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2057 break;
2058 case IW_MEMREG_TYPE_QP:
2059 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
2060 if (iwpbl->on_list) {
2061 iwpbl->on_list = false;
2062 list_del(&iwpbl->list);
2063 }
2064 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
2065 break;
2066 default:
2067 break;
2068 }
2069}
2070
2071
2072
2073
2074
2075static int i40iw_dereg_mr(struct ib_mr *ib_mr)
2076{
2077 struct ib_pd *ibpd = ib_mr->pd;
2078 struct i40iw_pd *iwpd = to_iwpd(ibpd);
2079 struct i40iw_mr *iwmr = to_iwmr(ib_mr);
2080 struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
2081 enum i40iw_status_code status;
2082 struct i40iw_dealloc_stag_info *info;
2083 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
2084 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
2085 struct i40iw_cqp_request *cqp_request;
2086 struct cqp_commands_info *cqp_info;
2087 u32 stag_idx;
2088
2089 if (iwmr->region)
2090 ib_umem_release(iwmr->region);
2091
2092 if (iwmr->type != IW_MEMREG_TYPE_MEM) {
2093
2094 if (iwmr->region) {
2095 struct i40iw_ucontext *ucontext;
2096
2097 ucontext = to_ucontext(ibpd->uobject->context);
2098 i40iw_del_memlist(iwmr, ucontext);
2099 }
2100 if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP)
2101 i40iw_free_pble(iwdev->pble_rsrc, palloc);
2102 kfree(iwmr);
2103 return 0;
2104 }
2105
2106 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
2107 if (!cqp_request)
2108 return -ENOMEM;
2109
2110 cqp_info = &cqp_request->info;
2111 info = &cqp_info->in.u.dealloc_stag.info;
2112 memset(info, 0, sizeof(*info));
2113
2114 info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
2115 info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
2116 stag_idx = info->stag_idx;
2117 info->mr = true;
2118 if (iwpbl->pbl_allocated)
2119 info->dealloc_pbl = true;
2120
2121 cqp_info->cqp_cmd = OP_DEALLOC_STAG;
2122 cqp_info->post_sq = 1;
2123 cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
2124 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
2125 status = i40iw_handle_cqp_op(iwdev, cqp_request);
2126 if (status)
2127 i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
2128 i40iw_rem_pdusecount(iwpd, iwdev);
2129 i40iw_free_stag(iwdev, iwmr->stag);
2130 if (iwpbl->pbl_allocated)
2131 i40iw_free_pble(iwdev->pble_rsrc, palloc);
2132 kfree(iwmr);
2133 return 0;
2134}
2135
2136
2137
2138
2139static ssize_t hw_rev_show(struct device *dev,
2140 struct device_attribute *attr, char *buf)
2141{
2142 struct i40iw_ib_device *iwibdev = container_of(dev,
2143 struct i40iw_ib_device,
2144 ibdev.dev);
2145 u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
2146
2147 return sprintf(buf, "%x\n", hw_rev);
2148}
2149static DEVICE_ATTR_RO(hw_rev);
2150
2151
2152
2153
2154static ssize_t hca_type_show(struct device *dev,
2155 struct device_attribute *attr, char *buf)
2156{
2157 return sprintf(buf, "I40IW\n");
2158}
2159static DEVICE_ATTR_RO(hca_type);
2160
2161
2162
2163
2164static ssize_t board_id_show(struct device *dev,
2165 struct device_attribute *attr, char *buf)
2166{
2167 return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
2168}
2169static DEVICE_ATTR_RO(board_id);
2170
2171static struct attribute *i40iw_dev_attributes[] = {
2172 &dev_attr_hw_rev.attr,
2173 &dev_attr_hca_type.attr,
2174 &dev_attr_board_id.attr,
2175 NULL
2176};
2177
2178static const struct attribute_group i40iw_attr_group = {
2179 .attrs = i40iw_dev_attributes,
2180};
2181
2182
2183
2184
2185
2186
2187
2188static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
2189{
2190 unsigned int i;
2191
2192 for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
2193 sg_list[i].tag_off = sgl[i].addr;
2194 sg_list[i].len = sgl[i].length;
2195 sg_list[i].stag = sgl[i].lkey;
2196 }
2197}
2198
2199
2200
2201
2202
2203
2204
2205static int i40iw_post_send(struct ib_qp *ibqp,
2206 const struct ib_send_wr *ib_wr,
2207 const struct ib_send_wr **bad_wr)
2208{
2209 struct i40iw_qp *iwqp;
2210 struct i40iw_qp_uk *ukqp;
2211 struct i40iw_post_sq_info info;
2212 enum i40iw_status_code ret;
2213 int err = 0;
2214 unsigned long flags;
2215 bool inv_stag;
2216
2217 iwqp = (struct i40iw_qp *)ibqp;
2218 ukqp = &iwqp->sc_qp.qp_uk;
2219
2220 spin_lock_irqsave(&iwqp->lock, flags);
2221
2222 if (iwqp->flush_issued) {
2223 err = -EINVAL;
2224 goto out;
2225 }
2226
2227 while (ib_wr) {
2228 inv_stag = false;
2229 memset(&info, 0, sizeof(info));
2230 info.wr_id = (u64)(ib_wr->wr_id);
2231 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
2232 info.signaled = true;
2233 if (ib_wr->send_flags & IB_SEND_FENCE)
2234 info.read_fence = true;
2235
2236 switch (ib_wr->opcode) {
2237 case IB_WR_SEND:
2238
2239 case IB_WR_SEND_WITH_INV:
2240 if (ib_wr->opcode == IB_WR_SEND) {
2241 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2242 info.op_type = I40IW_OP_TYPE_SEND_SOL;
2243 else
2244 info.op_type = I40IW_OP_TYPE_SEND;
2245 } else {
2246 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2247 info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
2248 else
2249 info.op_type = I40IW_OP_TYPE_SEND_INV;
2250 }
2251
2252 if (ib_wr->send_flags & IB_SEND_INLINE) {
2253 info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2254 info.op.inline_send.len = ib_wr->sg_list[0].length;
2255 ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2256 } else {
2257 info.op.send.num_sges = ib_wr->num_sge;
2258 info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
2259 ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2260 }
2261
2262 if (ret) {
2263 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2264 err = -ENOMEM;
2265 else
2266 err = -EINVAL;
2267 }
2268 break;
2269 case IB_WR_RDMA_WRITE:
2270 info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
2271
2272 if (ib_wr->send_flags & IB_SEND_INLINE) {
2273 info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2274 info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
2275 info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2276 info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2277 ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
2278 } else {
2279 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
2280 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
2281 info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2282 info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2283 ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
2284 }
2285
2286 if (ret) {
2287 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2288 err = -ENOMEM;
2289 else
2290 err = -EINVAL;
2291 }
2292 break;
2293 case IB_WR_RDMA_READ_WITH_INV:
2294 inv_stag = true;
2295
2296 case IB_WR_RDMA_READ:
2297 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
2298 err = -EINVAL;
2299 break;
2300 }
2301 info.op_type = I40IW_OP_TYPE_RDMA_READ;
2302 info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2303 info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2304 info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
2305 info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
2306 info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
2307 ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
2308 if (ret) {
2309 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2310 err = -ENOMEM;
2311 else
2312 err = -EINVAL;
2313 }
2314 break;
2315 case IB_WR_LOCAL_INV:
2316 info.op_type = I40IW_OP_TYPE_INV_STAG;
2317 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
2318 ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
2319 if (ret)
2320 err = -ENOMEM;
2321 break;
2322 case IB_WR_REG_MR:
2323 {
2324 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
2325 int flags = reg_wr(ib_wr)->access;
2326 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2327 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
2328 struct i40iw_fast_reg_stag_info info;
2329
2330 memset(&info, 0, sizeof(info));
2331 info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
2332 info.access_rights |= i40iw_get_user_access(flags);
2333 info.stag_key = reg_wr(ib_wr)->key & 0xff;
2334 info.stag_idx = reg_wr(ib_wr)->key >> 8;
2335 info.page_size = reg_wr(ib_wr)->mr->page_size;
2336 info.wr_id = ib_wr->wr_id;
2337
2338 info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
2339 info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
2340 info.total_len = iwmr->ibmr.length;
2341 info.reg_addr_pa = *(u64 *)palloc->level1.addr;
2342 info.first_pm_pbl_index = palloc->level1.idx;
2343 info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
2344 info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
2345
2346 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
2347 info.chunk_size = 1;
2348
2349 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
2350 if (ret)
2351 err = -ENOMEM;
2352 break;
2353 }
2354 default:
2355 err = -EINVAL;
2356 i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
2357 ib_wr->opcode);
2358 break;
2359 }
2360
2361 if (err)
2362 break;
2363 ib_wr = ib_wr->next;
2364 }
2365
2366out:
2367 if (err)
2368 *bad_wr = ib_wr;
2369 else
2370 ukqp->ops.iw_qp_post_wr(ukqp);
2371 spin_unlock_irqrestore(&iwqp->lock, flags);
2372
2373 return err;
2374}
2375
2376
2377
2378
2379
2380
2381
2382static int i40iw_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *ib_wr,
2383 const struct ib_recv_wr **bad_wr)
2384{
2385 struct i40iw_qp *iwqp;
2386 struct i40iw_qp_uk *ukqp;
2387 struct i40iw_post_rq_info post_recv;
2388 struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
2389 enum i40iw_status_code ret = 0;
2390 unsigned long flags;
2391 int err = 0;
2392
2393 iwqp = (struct i40iw_qp *)ibqp;
2394 ukqp = &iwqp->sc_qp.qp_uk;
2395
2396 memset(&post_recv, 0, sizeof(post_recv));
2397 spin_lock_irqsave(&iwqp->lock, flags);
2398
2399 if (iwqp->flush_issued) {
2400 err = -EINVAL;
2401 goto out;
2402 }
2403
2404 while (ib_wr) {
2405 post_recv.num_sges = ib_wr->num_sge;
2406 post_recv.wr_id = ib_wr->wr_id;
2407 i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
2408 post_recv.sg_list = sg_list;
2409 ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
2410 if (ret) {
2411 i40iw_pr_err(" post_recv err %d\n", ret);
2412 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2413 err = -ENOMEM;
2414 else
2415 err = -EINVAL;
2416 *bad_wr = ib_wr;
2417 goto out;
2418 }
2419 ib_wr = ib_wr->next;
2420 }
2421 out:
2422 spin_unlock_irqrestore(&iwqp->lock, flags);
2423 return err;
2424}
2425
2426
2427
2428
2429
2430
2431
2432static int i40iw_poll_cq(struct ib_cq *ibcq,
2433 int num_entries,
2434 struct ib_wc *entry)
2435{
2436 struct i40iw_cq *iwcq;
2437 int cqe_count = 0;
2438 struct i40iw_cq_poll_info cq_poll_info;
2439 enum i40iw_status_code ret;
2440 struct i40iw_cq_uk *ukcq;
2441 struct i40iw_sc_qp *qp;
2442 struct i40iw_qp *iwqp;
2443 unsigned long flags;
2444
2445 iwcq = (struct i40iw_cq *)ibcq;
2446 ukcq = &iwcq->sc_cq.cq_uk;
2447
2448 spin_lock_irqsave(&iwcq->lock, flags);
2449 while (cqe_count < num_entries) {
2450 ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
2451 if (ret == I40IW_ERR_QUEUE_EMPTY) {
2452 break;
2453 } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
2454 continue;
2455 } else if (ret) {
2456 if (!cqe_count)
2457 cqe_count = -1;
2458 break;
2459 }
2460 entry->wc_flags = 0;
2461 entry->wr_id = cq_poll_info.wr_id;
2462 if (cq_poll_info.error) {
2463 entry->status = IB_WC_WR_FLUSH_ERR;
2464 entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
2465 } else {
2466 entry->status = IB_WC_SUCCESS;
2467 }
2468
2469 switch (cq_poll_info.op_type) {
2470 case I40IW_OP_TYPE_RDMA_WRITE:
2471 entry->opcode = IB_WC_RDMA_WRITE;
2472 break;
2473 case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
2474 case I40IW_OP_TYPE_RDMA_READ:
2475 entry->opcode = IB_WC_RDMA_READ;
2476 break;
2477 case I40IW_OP_TYPE_SEND_SOL:
2478 case I40IW_OP_TYPE_SEND_SOL_INV:
2479 case I40IW_OP_TYPE_SEND_INV:
2480 case I40IW_OP_TYPE_SEND:
2481 entry->opcode = IB_WC_SEND;
2482 break;
2483 case I40IW_OP_TYPE_REC:
2484 entry->opcode = IB_WC_RECV;
2485 break;
2486 default:
2487 entry->opcode = IB_WC_RECV;
2488 break;
2489 }
2490
2491 entry->ex.imm_data = 0;
2492 qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
2493 entry->qp = (struct ib_qp *)qp->back_qp;
2494 entry->src_qp = cq_poll_info.qp_id;
2495 iwqp = (struct i40iw_qp *)qp->back_qp;
2496 if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
2497 if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
2498 complete(&iwqp->sq_drained);
2499 if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
2500 complete(&iwqp->rq_drained);
2501 }
2502 entry->byte_len = cq_poll_info.bytes_xfered;
2503 entry++;
2504 cqe_count++;
2505 }
2506 spin_unlock_irqrestore(&iwcq->lock, flags);
2507 return cqe_count;
2508}
2509
2510
2511
2512
2513
2514
2515static int i40iw_req_notify_cq(struct ib_cq *ibcq,
2516 enum ib_cq_notify_flags notify_flags)
2517{
2518 struct i40iw_cq *iwcq;
2519 struct i40iw_cq_uk *ukcq;
2520 unsigned long flags;
2521 enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
2522
2523 iwcq = (struct i40iw_cq *)ibcq;
2524 ukcq = &iwcq->sc_cq.cq_uk;
2525 if (notify_flags == IB_CQ_SOLICITED)
2526 cq_notify = IW_CQ_COMPL_SOLICITED;
2527 spin_lock_irqsave(&iwcq->lock, flags);
2528 ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
2529 spin_unlock_irqrestore(&iwcq->lock, flags);
2530 return 0;
2531}
2532
2533
2534
2535
2536
2537
2538
2539static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
2540 struct ib_port_immutable *immutable)
2541{
2542 struct ib_port_attr attr;
2543 int err;
2544
2545 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
2546
2547 err = ib_query_port(ibdev, port_num, &attr);
2548
2549 if (err)
2550 return err;
2551
2552 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2553 immutable->gid_tbl_len = attr.gid_tbl_len;
2554
2555 return 0;
2556}
2557
2558static const char * const i40iw_hw_stat_names[] = {
2559
2560 [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
2561 [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
2562 [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
2563 [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
2564 [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
2565 [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
2566 [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
2567 [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
2568 [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
2569
2570 [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2571 "ip4InOctets",
2572 [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2573 "ip4InPkts",
2574 [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2575 "ip4InReasmRqd",
2576 [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2577 "ip4InMcastPkts",
2578 [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2579 "ip4OutOctets",
2580 [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2581 "ip4OutPkts",
2582 [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2583 "ip4OutSegRqd",
2584 [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2585 "ip4OutMcastPkts",
2586 [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2587 "ip6InOctets",
2588 [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2589 "ip6InPkts",
2590 [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2591 "ip6InReasmRqd",
2592 [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2593 "ip6InMcastPkts",
2594 [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2595 "ip6OutOctets",
2596 [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2597 "ip6OutPkts",
2598 [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2599 "ip6OutSegRqd",
2600 [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2601 "ip6OutMcastPkts",
2602 [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
2603 "tcpInSegs",
2604 [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
2605 "tcpOutSegs",
2606 [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2607 "iwInRdmaReads",
2608 [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2609 "iwInRdmaSends",
2610 [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2611 "iwInRdmaWrites",
2612 [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2613 "iwOutRdmaReads",
2614 [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2615 "iwOutRdmaSends",
2616 [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2617 "iwOutRdmaWrites",
2618 [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
2619 "iwRdmaBnd",
2620 [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
2621 "iwRdmaInv"
2622};
2623
2624static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str)
2625{
2626 u32 firmware_version = I40IW_FW_VERSION;
2627
2628 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", firmware_version,
2629 (firmware_version & 0x000000ff));
2630}
2631
2632
2633
2634
2635
2636
2637static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
2638 u8 port_num)
2639{
2640 struct i40iw_device *iwdev = to_iwdev(ibdev);
2641 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2642 int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
2643 I40IW_HW_STAT_INDEX_MAX_64;
2644 unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
2645
2646 BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
2647 (I40IW_HW_STAT_INDEX_MAX_32 +
2648 I40IW_HW_STAT_INDEX_MAX_64));
2649
2650
2651
2652
2653
2654 if (!dev->is_pf)
2655 lifespan = 1000;
2656 return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
2657 lifespan);
2658}
2659
2660
2661
2662
2663
2664
2665
2666
2667static int i40iw_get_hw_stats(struct ib_device *ibdev,
2668 struct rdma_hw_stats *stats,
2669 u8 port_num, int index)
2670{
2671 struct i40iw_device *iwdev = to_iwdev(ibdev);
2672 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2673 struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
2674 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
2675
2676 if (dev->is_pf) {
2677 i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
2678 } else {
2679 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
2680 return -ENOSYS;
2681 }
2682
2683 memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
2684
2685 return stats->num_counters;
2686}
2687
2688
2689
2690
2691
2692
2693
2694
2695static int i40iw_query_gid(struct ib_device *ibdev,
2696 u8 port,
2697 int index,
2698 union ib_gid *gid)
2699{
2700 struct i40iw_device *iwdev = to_iwdev(ibdev);
2701
2702 memset(gid->raw, 0, sizeof(gid->raw));
2703 ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
2704 return 0;
2705}
2706
2707
2708
2709
2710
2711
2712
2713
2714static int i40iw_query_pkey(struct ib_device *ibdev,
2715 u8 port,
2716 u16 index,
2717 u16 *pkey)
2718{
2719 *pkey = 0;
2720 return 0;
2721}
2722
2723
2724
2725
2726
2727static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
2728{
2729 struct i40iw_ib_device *iwibdev;
2730 struct net_device *netdev = iwdev->netdev;
2731 struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
2732
2733 iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
2734 if (!iwibdev) {
2735 i40iw_pr_err("iwdev == NULL\n");
2736 return NULL;
2737 }
2738 iwibdev->ibdev.owner = THIS_MODULE;
2739 iwdev->iwibdev = iwibdev;
2740 iwibdev->iwdev = iwdev;
2741
2742 iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
2743 ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
2744
2745 iwibdev->ibdev.uverbs_cmd_mask =
2746 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2747 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2748 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2749 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2750 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2751 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2752 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2753 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2754 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2755 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2756 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2757 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2758 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2759 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2760 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2761 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2762 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2763 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2764 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2765 (1ull << IB_USER_VERBS_CMD_POST_SEND);
2766 iwibdev->ibdev.phys_port_cnt = 1;
2767 iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
2768 iwibdev->ibdev.dev.parent = &pcidev->dev;
2769 iwibdev->ibdev.query_port = i40iw_query_port;
2770 iwibdev->ibdev.query_pkey = i40iw_query_pkey;
2771 iwibdev->ibdev.query_gid = i40iw_query_gid;
2772 iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
2773 iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
2774 iwibdev->ibdev.mmap = i40iw_mmap;
2775 iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
2776 iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
2777 iwibdev->ibdev.create_qp = i40iw_create_qp;
2778 iwibdev->ibdev.modify_qp = i40iw_modify_qp;
2779 iwibdev->ibdev.query_qp = i40iw_query_qp;
2780 iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
2781 iwibdev->ibdev.create_cq = i40iw_create_cq;
2782 iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
2783 iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
2784 iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
2785 iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
2786 iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
2787 iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
2788 iwibdev->ibdev.query_device = i40iw_query_device;
2789 iwibdev->ibdev.drain_sq = i40iw_drain_sq;
2790 iwibdev->ibdev.drain_rq = i40iw_drain_rq;
2791 iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
2792 iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
2793 iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
2794 if (!iwibdev->ibdev.iwcm) {
2795 ib_dealloc_device(&iwibdev->ibdev);
2796 return NULL;
2797 }
2798
2799 iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
2800 iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
2801 iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
2802 iwibdev->ibdev.iwcm->connect = i40iw_connect;
2803 iwibdev->ibdev.iwcm->accept = i40iw_accept;
2804 iwibdev->ibdev.iwcm->reject = i40iw_reject;
2805 iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
2806 iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
2807 memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
2808 sizeof(iwibdev->ibdev.iwcm->ifname));
2809 iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
2810 iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
2811 iwibdev->ibdev.poll_cq = i40iw_poll_cq;
2812 iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
2813 iwibdev->ibdev.post_send = i40iw_post_send;
2814 iwibdev->ibdev.post_recv = i40iw_post_recv;
2815
2816 return iwibdev;
2817}
2818
2819
2820
2821
2822
2823void i40iw_port_ibevent(struct i40iw_device *iwdev)
2824{
2825 struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
2826 struct ib_event event;
2827
2828 event.device = &iwibdev->ibdev;
2829 event.element.port_num = 1;
2830 event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2831 ib_dispatch_event(&event);
2832}
2833
2834
2835
2836
2837
2838void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
2839{
2840 if (!iwibdev)
2841 return;
2842
2843 ib_unregister_device(&iwibdev->ibdev);
2844 kfree(iwibdev->ibdev.iwcm);
2845 iwibdev->ibdev.iwcm = NULL;
2846 wait_event_timeout(iwibdev->iwdev->close_wq,
2847 !atomic64_read(&iwibdev->iwdev->use_count),
2848 I40IW_EVENT_TIMEOUT);
2849 ib_dealloc_device(&iwibdev->ibdev);
2850}
2851
2852
2853
2854
2855
2856int i40iw_register_rdma_device(struct i40iw_device *iwdev)
2857{
2858 int ret;
2859 struct i40iw_ib_device *iwibdev;
2860
2861 iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
2862 if (!iwdev->iwibdev)
2863 return -ENOMEM;
2864 iwibdev = iwdev->iwibdev;
2865 rdma_set_device_sysfs_group(&iwibdev->ibdev, &i40iw_attr_group);
2866 iwibdev->ibdev.driver_id = RDMA_DRIVER_I40IW;
2867 ret = ib_register_device(&iwibdev->ibdev, "i40iw%d", NULL);
2868 if (ret)
2869 goto error;
2870
2871 return 0;
2872error:
2873 kfree(iwdev->iwibdev->ibdev.iwcm);
2874 iwdev->iwibdev->ibdev.iwcm = NULL;
2875 ib_dealloc_device(&iwdev->iwibdev->ibdev);
2876 return ret;
2877}
2878