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33#include <rdma/ib_mad.h>
34#include <rdma/ib_smi.h>
35#include <rdma/ib_sa.h>
36#include <rdma/ib_cache.h>
37
38#include <linux/random.h>
39#include <linux/mlx4/cmd.h>
40#include <linux/gfp.h>
41#include <rdma/ib_pma.h>
42#include <linux/ip.h>
43#include <net/ipv6.h>
44
45#include <linux/mlx4/driver.h>
46#include "mlx4_ib.h"
47
48enum {
49 MLX4_IB_VENDOR_CLASS1 = 0x9,
50 MLX4_IB_VENDOR_CLASS2 = 0xa
51};
52
53#define MLX4_TUN_SEND_WRID_SHIFT 34
54#define MLX4_TUN_QPN_SHIFT 32
55#define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT)
56#define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT)
57
58#define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1)
59#define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3)
60
61
62
63#define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr)
64#define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask)
65#define NUM_IDX_IN_PKEY_TBL_BLK 32
66#define GUID_TBL_ENTRY_SIZE 8
67#define GUID_TBL_BLK_NUM_ENTRIES 8
68#define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES)
69
70struct mlx4_mad_rcv_buf {
71 struct ib_grh grh;
72 u8 payload[256];
73} __packed;
74
75struct mlx4_mad_snd_buf {
76 u8 payload[256];
77} __packed;
78
79struct mlx4_tunnel_mad {
80 struct ib_grh grh;
81 struct mlx4_ib_tunnel_header hdr;
82 struct ib_mad mad;
83} __packed;
84
85struct mlx4_rcv_tunnel_mad {
86 struct mlx4_rcv_tunnel_hdr hdr;
87 struct ib_grh grh;
88 struct ib_mad mad;
89} __packed;
90
91static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num);
92static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num);
93static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
94 int block, u32 change_bitmap);
95
96__be64 mlx4_ib_gen_node_guid(void)
97{
98#define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40))
99 return cpu_to_be64(NODE_GUID_HI | prandom_u32());
100}
101
102__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx)
103{
104 return cpu_to_be64(atomic_inc_return(&ctx->tid)) |
105 cpu_to_be64(0xff00000000000000LL);
106}
107
108int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
109 int port, const struct ib_wc *in_wc,
110 const struct ib_grh *in_grh,
111 const void *in_mad, void *response_mad)
112{
113 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
114 void *inbox;
115 int err;
116 u32 in_modifier = port;
117 u8 op_modifier = 0;
118
119 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
120 if (IS_ERR(inmailbox))
121 return PTR_ERR(inmailbox);
122 inbox = inmailbox->buf;
123
124 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
125 if (IS_ERR(outmailbox)) {
126 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
127 return PTR_ERR(outmailbox);
128 }
129
130 memcpy(inbox, in_mad, 256);
131
132
133
134
135
136 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc)
137 op_modifier |= 0x1;
138 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc)
139 op_modifier |= 0x2;
140 if (mlx4_is_mfunc(dev->dev) &&
141 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc))
142 op_modifier |= 0x8;
143
144 if (in_wc) {
145 struct {
146 __be32 my_qpn;
147 u32 reserved1;
148 __be32 rqpn;
149 u8 sl;
150 u8 g_path;
151 u16 reserved2[2];
152 __be16 pkey;
153 u32 reserved3[11];
154 u8 grh[40];
155 } *ext_info;
156
157 memset(inbox + 256, 0, 256);
158 ext_info = inbox + 256;
159
160 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num);
161 ext_info->rqpn = cpu_to_be32(in_wc->src_qp);
162 ext_info->sl = in_wc->sl << 4;
163 ext_info->g_path = in_wc->dlid_path_bits |
164 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
165 ext_info->pkey = cpu_to_be16(in_wc->pkey_index);
166
167 if (in_grh)
168 memcpy(ext_info->grh, in_grh, 40);
169
170 op_modifier |= 0x4;
171
172 in_modifier |= ib_lid_cpu16(in_wc->slid) << 16;
173 }
174
175 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier,
176 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier,
177 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
178 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED);
179
180 if (!err)
181 memcpy(response_mad, outmailbox->buf, 256);
182
183 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
184 mlx4_free_cmd_mailbox(dev->dev, outmailbox);
185
186 return err;
187}
188
189static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl)
190{
191 struct ib_ah *new_ah;
192 struct rdma_ah_attr ah_attr;
193 unsigned long flags;
194
195 if (!dev->send_agent[port_num - 1][0])
196 return;
197
198 memset(&ah_attr, 0, sizeof ah_attr);
199 ah_attr.type = rdma_ah_find_type(&dev->ib_dev, port_num);
200 rdma_ah_set_dlid(&ah_attr, lid);
201 rdma_ah_set_sl(&ah_attr, sl);
202 rdma_ah_set_port_num(&ah_attr, port_num);
203
204 new_ah = rdma_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
205 &ah_attr);
206 if (IS_ERR(new_ah))
207 return;
208
209 spin_lock_irqsave(&dev->sm_lock, flags);
210 if (dev->sm_ah[port_num - 1])
211 rdma_destroy_ah(dev->sm_ah[port_num - 1]);
212 dev->sm_ah[port_num - 1] = new_ah;
213 spin_unlock_irqrestore(&dev->sm_lock, flags);
214}
215
216
217
218
219
220static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad,
221 u16 prev_lid)
222{
223 struct ib_port_info *pinfo;
224 u16 lid;
225 __be16 *base;
226 u32 bn, pkey_change_bitmap;
227 int i;
228
229
230 struct mlx4_ib_dev *dev = to_mdev(ibdev);
231 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
232 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
233 mad->mad_hdr.method == IB_MGMT_METHOD_SET)
234 switch (mad->mad_hdr.attr_id) {
235 case IB_SMP_ATTR_PORT_INFO:
236 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
237 return;
238 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data;
239 lid = be16_to_cpu(pinfo->lid);
240
241 update_sm_ah(dev, port_num,
242 be16_to_cpu(pinfo->sm_lid),
243 pinfo->neighbormtu_mastersmsl & 0xf);
244
245 if (pinfo->clientrereg_resv_subnetto & 0x80)
246 handle_client_rereg_event(dev, port_num);
247
248 if (prev_lid != lid)
249 handle_lid_change_event(dev, port_num);
250 break;
251
252 case IB_SMP_ATTR_PKEY_TABLE:
253 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
254 return;
255 if (!mlx4_is_mfunc(dev->dev)) {
256 mlx4_ib_dispatch_event(dev, port_num,
257 IB_EVENT_PKEY_CHANGE);
258 break;
259 }
260
261
262
263
264 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF;
265 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]);
266 pkey_change_bitmap = 0;
267 for (i = 0; i < 32; i++) {
268 pr_debug("PKEY[%d] = x%x\n",
269 i + bn*32, be16_to_cpu(base[i]));
270 if (be16_to_cpu(base[i]) !=
271 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) {
272 pkey_change_bitmap |= (1 << i);
273 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] =
274 be16_to_cpu(base[i]);
275 }
276 }
277 pr_debug("PKEY Change event: port=%d, "
278 "block=0x%x, change_bitmap=0x%x\n",
279 port_num, bn, pkey_change_bitmap);
280
281 if (pkey_change_bitmap) {
282 mlx4_ib_dispatch_event(dev, port_num,
283 IB_EVENT_PKEY_CHANGE);
284 if (!dev->sriov.is_going_down)
285 __propagate_pkey_ev(dev, port_num, bn,
286 pkey_change_bitmap);
287 }
288 break;
289
290 case IB_SMP_ATTR_GUID_INFO:
291 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
292 return;
293
294 if (!mlx4_is_master(dev->dev))
295 mlx4_ib_dispatch_event(dev, port_num,
296 IB_EVENT_GID_CHANGE);
297
298 if (mlx4_is_master(dev->dev) &&
299 !dev->sriov.is_going_down) {
300 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod);
301 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num,
302 (u8 *)(&((struct ib_smp *)mad)->data));
303 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num,
304 (u8 *)(&((struct ib_smp *)mad)->data));
305 }
306 break;
307
308 case IB_SMP_ATTR_SL_TO_VL_TABLE:
309
310
311
312 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV &&
313 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)
314 return;
315 if (!mlx4_is_slave(dev->dev)) {
316 union sl2vl_tbl_to_u64 sl2vl64;
317 int jj;
318
319 for (jj = 0; jj < 8; jj++) {
320 sl2vl64.sl8[jj] = ((struct ib_smp *)mad)->data[jj];
321 pr_debug("port %u, sl2vl[%d] = %02x\n",
322 port_num, jj, sl2vl64.sl8[jj]);
323 }
324 atomic64_set(&dev->sl2vl[port_num - 1], sl2vl64.sl64);
325 }
326 break;
327
328 default:
329 break;
330 }
331}
332
333static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
334 int block, u32 change_bitmap)
335{
336 int i, ix, slave, err;
337 int have_event = 0;
338
339 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) {
340 if (slave == mlx4_master_func_num(dev->dev))
341 continue;
342 if (!mlx4_is_slave_active(dev->dev, slave))
343 continue;
344
345 have_event = 0;
346 for (i = 0; i < 32; i++) {
347 if (!(change_bitmap & (1 << i)))
348 continue;
349 for (ix = 0;
350 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) {
351 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1]
352 [ix] == i + 32 * block) {
353 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num);
354 pr_debug("propagate_pkey_ev: slave %d,"
355 " port %d, ix %d (%d)\n",
356 slave, port_num, ix, err);
357 have_event = 1;
358 break;
359 }
360 }
361 if (have_event)
362 break;
363 }
364 }
365}
366
367static void node_desc_override(struct ib_device *dev,
368 struct ib_mad *mad)
369{
370 unsigned long flags;
371
372 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
373 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
374 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
375 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
376 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags);
377 memcpy(((struct ib_smp *) mad)->data, dev->node_desc,
378 IB_DEVICE_NODE_DESC_MAX);
379 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags);
380 }
381}
382
383static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad)
384{
385 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
386 struct ib_mad_send_buf *send_buf;
387 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
388 int ret;
389 unsigned long flags;
390
391 if (agent) {
392 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
393 IB_MGMT_MAD_DATA, GFP_ATOMIC,
394 IB_MGMT_BASE_VERSION);
395 if (IS_ERR(send_buf))
396 return;
397
398
399
400
401
402
403 spin_lock_irqsave(&dev->sm_lock, flags);
404 memcpy(send_buf->mad, mad, sizeof *mad);
405 if ((send_buf->ah = dev->sm_ah[port_num - 1]))
406 ret = ib_post_send_mad(send_buf, NULL);
407 else
408 ret = -EINVAL;
409 spin_unlock_irqrestore(&dev->sm_lock, flags);
410
411 if (ret)
412 ib_free_send_mad(send_buf);
413 }
414}
415
416static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave,
417 struct ib_sa_mad *sa_mad)
418{
419 int ret = 0;
420
421
422 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
423 case IB_SA_ATTR_MC_MEMBER_REC:
424 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad);
425 break;
426 default:
427 break;
428 }
429 return ret;
430}
431
432int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid)
433{
434 struct mlx4_ib_dev *dev = to_mdev(ibdev);
435 int i;
436
437 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
438 if (dev->sriov.demux[port - 1].guid_cache[i] == guid)
439 return i;
440 }
441 return -1;
442}
443
444
445static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
446 u8 port, u16 pkey, u16 *ix)
447{
448 int i, ret;
449 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF;
450 u16 slot_pkey;
451
452 if (slave == mlx4_master_func_num(dev->dev))
453 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix);
454
455 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1;
456
457 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) {
458 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix)
459 continue;
460
461 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i];
462
463 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey);
464 if (ret)
465 continue;
466 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) {
467 if (slot_pkey & 0x8000) {
468 *ix = (u16) pkey_ix;
469 return 0;
470 } else {
471
472 if (partial_ix == 0xFF)
473 partial_ix = pkey_ix;
474 }
475 }
476 }
477
478 if (partial_ix < 0xFF) {
479 *ix = (u16) partial_ix;
480 return 0;
481 }
482
483 return -EINVAL;
484}
485
486static int get_gids_from_l3_hdr(struct ib_grh *grh, union ib_gid *sgid,
487 union ib_gid *dgid)
488{
489 int version = ib_get_rdma_header_version((const union rdma_network_hdr *)grh);
490 enum rdma_network_type net_type;
491
492 if (version == 4)
493 net_type = RDMA_NETWORK_IPV4;
494 else if (version == 6)
495 net_type = RDMA_NETWORK_IPV6;
496 else
497 return -EINVAL;
498
499 return ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type,
500 sgid, dgid);
501}
502
503int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
504 enum ib_qp_type dest_qpt, struct ib_wc *wc,
505 struct ib_grh *grh, struct ib_mad *mad)
506{
507 struct ib_sge list;
508 struct ib_ud_wr wr;
509 const struct ib_send_wr *bad_wr;
510 struct mlx4_ib_demux_pv_ctx *tun_ctx;
511 struct mlx4_ib_demux_pv_qp *tun_qp;
512 struct mlx4_rcv_tunnel_mad *tun_mad;
513 struct rdma_ah_attr attr;
514 struct ib_ah *ah;
515 struct ib_qp *src_qp = NULL;
516 unsigned tun_tx_ix = 0;
517 int dqpn;
518 int ret = 0;
519 u16 tun_pkey_ix;
520 u16 cached_pkey;
521 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
522
523 if (dest_qpt > IB_QPT_GSI)
524 return -EINVAL;
525
526 tun_ctx = dev->sriov.demux[port-1].tun[slave];
527
528
529 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE)
530 return -EAGAIN;
531
532 if (!dest_qpt)
533 tun_qp = &tun_ctx->qp[0];
534 else
535 tun_qp = &tun_ctx->qp[1];
536
537
538 if (dest_qpt) {
539 u16 pkey_ix;
540 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey);
541 if (ret)
542 return -EINVAL;
543
544 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix);
545 if (ret)
546 return -EINVAL;
547 tun_pkey_ix = pkey_ix;
548 } else
549 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
550
551 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1;
552
553
554 src_qp = tun_qp->qp;
555
556
557
558 memset(&attr, 0, sizeof attr);
559 attr.type = rdma_ah_find_type(&dev->ib_dev, port);
560
561 rdma_ah_set_port_num(&attr, port);
562 if (is_eth) {
563 union ib_gid sgid;
564 union ib_gid dgid;
565
566 if (get_gids_from_l3_hdr(grh, &sgid, &dgid))
567 return -EINVAL;
568 rdma_ah_set_grh(&attr, &dgid, 0, 0, 0, 0);
569 }
570 ah = rdma_create_ah(tun_ctx->pd, &attr);
571 if (IS_ERR(ah))
572 return -ENOMEM;
573
574
575 spin_lock(&tun_qp->tx_lock);
576 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >=
577 (MLX4_NUM_TUNNEL_BUFS - 1))
578 ret = -EAGAIN;
579 else
580 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
581 spin_unlock(&tun_qp->tx_lock);
582 if (ret)
583 goto end;
584
585 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr);
586 if (tun_qp->tx_ring[tun_tx_ix].ah)
587 rdma_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah);
588 tun_qp->tx_ring[tun_tx_ix].ah = ah;
589 ib_dma_sync_single_for_cpu(&dev->ib_dev,
590 tun_qp->tx_ring[tun_tx_ix].buf.map,
591 sizeof (struct mlx4_rcv_tunnel_mad),
592 DMA_TO_DEVICE);
593
594
595 if (grh)
596 memcpy(&tun_mad->grh, grh, sizeof *grh);
597 memcpy(&tun_mad->mad, mad, sizeof *mad);
598
599
600 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix);
601 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF);
602 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0;
603
604 if (is_eth) {
605 u16 vlan = 0;
606 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan,
607 NULL)) {
608
609 if (vlan != wc->vlan_id)
610
611
612
613 goto out;
614 else
615
616
617
618 vlan = 0xffff;
619 } else {
620 vlan = wc->vlan_id;
621 }
622
623 tun_mad->hdr.sl_vid = cpu_to_be16(vlan);
624 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4);
625 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2);
626 } else {
627 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12);
628 tun_mad->hdr.slid_mac_47_32 = ib_lid_be16(wc->slid);
629 }
630
631 ib_dma_sync_single_for_device(&dev->ib_dev,
632 tun_qp->tx_ring[tun_tx_ix].buf.map,
633 sizeof (struct mlx4_rcv_tunnel_mad),
634 DMA_TO_DEVICE);
635
636 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map;
637 list.length = sizeof (struct mlx4_rcv_tunnel_mad);
638 list.lkey = tun_ctx->pd->local_dma_lkey;
639
640 wr.ah = ah;
641 wr.port_num = port;
642 wr.remote_qkey = IB_QP_SET_QKEY;
643 wr.remote_qpn = dqpn;
644 wr.wr.next = NULL;
645 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt);
646 wr.wr.sg_list = &list;
647 wr.wr.num_sge = 1;
648 wr.wr.opcode = IB_WR_SEND;
649 wr.wr.send_flags = IB_SEND_SIGNALED;
650
651 ret = ib_post_send(src_qp, &wr.wr, &bad_wr);
652 if (!ret)
653 return 0;
654 out:
655 spin_lock(&tun_qp->tx_lock);
656 tun_qp->tx_ix_tail++;
657 spin_unlock(&tun_qp->tx_lock);
658 tun_qp->tx_ring[tun_tx_ix].ah = NULL;
659end:
660 rdma_destroy_ah(ah);
661 return ret;
662}
663
664static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
665 struct ib_wc *wc, struct ib_grh *grh,
666 struct ib_mad *mad)
667{
668 struct mlx4_ib_dev *dev = to_mdev(ibdev);
669 int err, other_port;
670 int slave = -1;
671 u8 *slave_id;
672 int is_eth = 0;
673
674 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
675 is_eth = 0;
676 else
677 is_eth = 1;
678
679 if (is_eth) {
680 union ib_gid dgid;
681 union ib_gid sgid;
682
683 if (get_gids_from_l3_hdr(grh, &sgid, &dgid))
684 return -EINVAL;
685 if (!(wc->wc_flags & IB_WC_GRH)) {
686 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
687 return -EINVAL;
688 }
689 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) {
690 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
691 return -EINVAL;
692 }
693 err = mlx4_get_slave_from_roce_gid(dev->dev, port, dgid.raw, &slave);
694 if (err && mlx4_is_mf_bonded(dev->dev)) {
695 other_port = (port == 1) ? 2 : 1;
696 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, dgid.raw, &slave);
697 if (!err) {
698 port = other_port;
699 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n",
700 slave, grh->dgid.raw, port, other_port);
701 }
702 }
703 if (err) {
704 mlx4_ib_warn(ibdev, "failed matching grh\n");
705 return -ENOENT;
706 }
707 if (slave >= dev->dev->caps.sqp_demux) {
708 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
709 slave, dev->dev->caps.sqp_demux);
710 return -ENOENT;
711 }
712
713 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad))
714 return 0;
715
716 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
717 if (err)
718 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
719 slave, err);
720 return 0;
721 }
722
723
724 slave = mlx4_master_func_num(dev->dev);
725
726
727 if (mad->mad_hdr.method & 0x80) {
728 slave_id = (u8 *) &mad->mad_hdr.tid;
729 slave = *slave_id;
730 if (slave != 255)
731 *slave_id = 0;
732 }
733
734
735 if (wc->wc_flags & IB_WC_GRH) {
736 if (grh->dgid.global.interface_id ==
737 cpu_to_be64(IB_SA_WELL_KNOWN_GUID) &&
738 grh->dgid.global.subnet_prefix == cpu_to_be64(
739 atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix))) {
740 slave = 0;
741 } else {
742 slave = mlx4_ib_find_real_gid(ibdev, port,
743 grh->dgid.global.interface_id);
744 if (slave < 0) {
745 mlx4_ib_warn(ibdev, "failed matching grh\n");
746 return -ENOENT;
747 }
748 }
749 }
750
751 switch (mad->mad_hdr.mgmt_class) {
752 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
753 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
754
755 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) {
756 if (!mlx4_vf_smi_enabled(dev->dev, slave, port))
757 return -EPERM;
758
759 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) {
760 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n",
761 slave, mad->mad_hdr.mgmt_class,
762 mad->mad_hdr.method);
763 return -EINVAL;
764 }
765 }
766 break;
767 case IB_MGMT_CLASS_SUBN_ADM:
768 if (mlx4_ib_demux_sa_handler(ibdev, port, slave,
769 (struct ib_sa_mad *) mad))
770 return 0;
771 break;
772 case IB_MGMT_CLASS_CM:
773 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad))
774 return 0;
775 break;
776 case IB_MGMT_CLASS_DEVICE_MGMT:
777 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP)
778 return 0;
779 break;
780 default:
781
782 if (slave != mlx4_master_func_num(dev->dev)) {
783 pr_debug("dropping unsupported ingress mad from class:%d "
784 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave);
785 return 0;
786 }
787 }
788
789 if (slave >= dev->dev->caps.sqp_demux) {
790 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
791 slave, dev->dev->caps.sqp_demux);
792 return -ENOENT;
793 }
794
795 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
796 if (err)
797 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
798 slave, err);
799 return 0;
800}
801
802static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
803 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
804 const struct ib_mad *in_mad, struct ib_mad *out_mad)
805{
806 u16 slid, prev_lid = 0;
807 int err;
808 struct ib_port_attr pattr;
809
810 if (in_wc && in_wc->qp) {
811 pr_debug("received MAD: port:%d slid:%d sqpn:%d "
812 "dlid_bits:%d dqpn:%d wc_flags:0x%x tid:%016llx cls:%x mtd:%x atr:%x\n",
813 port_num,
814 in_wc->slid, in_wc->src_qp,
815 in_wc->dlid_path_bits,
816 in_wc->qp->qp_num,
817 in_wc->wc_flags,
818 be64_to_cpu(in_mad->mad_hdr.tid),
819 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method,
820 be16_to_cpu(in_mad->mad_hdr.attr_id));
821 if (in_wc->wc_flags & IB_WC_GRH) {
822 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n",
823 be64_to_cpu(in_grh->sgid.global.subnet_prefix),
824 be64_to_cpu(in_grh->sgid.global.interface_id));
825 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n",
826 be64_to_cpu(in_grh->dgid.global.subnet_prefix),
827 be64_to_cpu(in_grh->dgid.global.interface_id));
828 }
829 }
830
831 slid = in_wc ? ib_lid_cpu16(in_wc->slid) : be16_to_cpu(IB_LID_PERMISSIVE);
832
833 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) {
834 forward_trap(to_mdev(ibdev), port_num, in_mad);
835 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
836 }
837
838 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
839 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
840 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
841 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
842 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
843 return IB_MAD_RESULT_SUCCESS;
844
845
846
847
848 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
849 return IB_MAD_RESULT_SUCCESS;
850 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
851 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 ||
852 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 ||
853 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
854 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
855 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
856 return IB_MAD_RESULT_SUCCESS;
857 } else
858 return IB_MAD_RESULT_SUCCESS;
859
860 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
861 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
862 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
863 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
864 !ib_query_port(ibdev, port_num, &pattr))
865 prev_lid = ib_lid_cpu16(pattr.lid);
866
867 err = mlx4_MAD_IFC(to_mdev(ibdev),
868 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) |
869 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) |
870 MLX4_MAD_IFC_NET_VIEW,
871 port_num, in_wc, in_grh, in_mad, out_mad);
872 if (err)
873 return IB_MAD_RESULT_FAILURE;
874
875 if (!out_mad->mad_hdr.status) {
876 smp_snoop(ibdev, port_num, in_mad, prev_lid);
877
878 if (!mlx4_is_slave(to_mdev(ibdev)->dev))
879 node_desc_override(ibdev, out_mad);
880 }
881
882
883 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
884 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
885
886 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
887
888 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
889
890 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
891}
892
893static void edit_counter(struct mlx4_counter *cnt, void *counters,
894 __be16 attr_id)
895{
896 switch (attr_id) {
897 case IB_PMA_PORT_COUNTERS:
898 {
899 struct ib_pma_portcounters *pma_cnt =
900 (struct ib_pma_portcounters *)counters;
901
902 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data,
903 (be64_to_cpu(cnt->tx_bytes) >> 2));
904 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data,
905 (be64_to_cpu(cnt->rx_bytes) >> 2));
906 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets,
907 be64_to_cpu(cnt->tx_frames));
908 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets,
909 be64_to_cpu(cnt->rx_frames));
910 break;
911 }
912 case IB_PMA_PORT_COUNTERS_EXT:
913 {
914 struct ib_pma_portcounters_ext *pma_cnt_ext =
915 (struct ib_pma_portcounters_ext *)counters;
916
917 pma_cnt_ext->port_xmit_data =
918 cpu_to_be64(be64_to_cpu(cnt->tx_bytes) >> 2);
919 pma_cnt_ext->port_rcv_data =
920 cpu_to_be64(be64_to_cpu(cnt->rx_bytes) >> 2);
921 pma_cnt_ext->port_xmit_packets = cnt->tx_frames;
922 pma_cnt_ext->port_rcv_packets = cnt->rx_frames;
923 break;
924 }
925 }
926}
927
928static int iboe_process_mad_port_info(void *out_mad)
929{
930 struct ib_class_port_info cpi = {};
931
932 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH;
933 memcpy(out_mad, &cpi, sizeof(cpi));
934 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
935}
936
937static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
938 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
939 const struct ib_mad *in_mad, struct ib_mad *out_mad)
940{
941 struct mlx4_counter counter_stats;
942 struct mlx4_ib_dev *dev = to_mdev(ibdev);
943 struct counter_index *tmp_counter;
944 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0;
945
946 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
947 return -EINVAL;
948
949 if (in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO)
950 return iboe_process_mad_port_info((void *)(out_mad->data + 40));
951
952 memset(&counter_stats, 0, sizeof(counter_stats));
953 mutex_lock(&dev->counters_table[port_num - 1].mutex);
954 list_for_each_entry(tmp_counter,
955 &dev->counters_table[port_num - 1].counters_list,
956 list) {
957 err = mlx4_get_counter_stats(dev->dev,
958 tmp_counter->index,
959 &counter_stats, 0);
960 if (err) {
961 err = IB_MAD_RESULT_FAILURE;
962 stats_avail = 0;
963 break;
964 }
965 stats_avail = 1;
966 }
967 mutex_unlock(&dev->counters_table[port_num - 1].mutex);
968 if (stats_avail) {
969 memset(out_mad->data, 0, sizeof out_mad->data);
970 switch (counter_stats.counter_mode & 0xf) {
971 case 0:
972 edit_counter(&counter_stats,
973 (void *)(out_mad->data + 40),
974 in_mad->mad_hdr.attr_id);
975 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
976 break;
977 default:
978 err = IB_MAD_RESULT_FAILURE;
979 }
980 }
981
982 return err;
983}
984
985int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
986 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
987 const struct ib_mad_hdr *in, size_t in_mad_size,
988 struct ib_mad_hdr *out, size_t *out_mad_size,
989 u16 *out_mad_pkey_index)
990{
991 struct mlx4_ib_dev *dev = to_mdev(ibdev);
992 const struct ib_mad *in_mad = (const struct ib_mad *)in;
993 struct ib_mad *out_mad = (struct ib_mad *)out;
994 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num);
995
996 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) ||
997 *out_mad_size != sizeof(*out_mad)))
998 return IB_MAD_RESULT_FAILURE;
999
1000
1001
1002
1003 if (link == IB_LINK_LAYER_INFINIBAND) {
1004 if (mlx4_is_slave(dev->dev) &&
1005 (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT &&
1006 (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS ||
1007 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT ||
1008 in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO)))
1009 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
1010 in_grh, in_mad, out_mad);
1011
1012 return ib_process_mad(ibdev, mad_flags, port_num, in_wc,
1013 in_grh, in_mad, out_mad);
1014 }
1015
1016 if (link == IB_LINK_LAYER_ETHERNET)
1017 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
1018 in_grh, in_mad, out_mad);
1019
1020 return -EINVAL;
1021}
1022
1023static void send_handler(struct ib_mad_agent *agent,
1024 struct ib_mad_send_wc *mad_send_wc)
1025{
1026 if (mad_send_wc->send_buf->context[0])
1027 rdma_destroy_ah(mad_send_wc->send_buf->context[0]);
1028 ib_free_send_mad(mad_send_wc->send_buf);
1029}
1030
1031int mlx4_ib_mad_init(struct mlx4_ib_dev *dev)
1032{
1033 struct ib_mad_agent *agent;
1034 int p, q;
1035 int ret;
1036 enum rdma_link_layer ll;
1037
1038 for (p = 0; p < dev->num_ports; ++p) {
1039 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1);
1040 for (q = 0; q <= 1; ++q) {
1041 if (ll == IB_LINK_LAYER_INFINIBAND) {
1042 agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
1043 q ? IB_QPT_GSI : IB_QPT_SMI,
1044 NULL, 0, send_handler,
1045 NULL, NULL, 0);
1046 if (IS_ERR(agent)) {
1047 ret = PTR_ERR(agent);
1048 goto err;
1049 }
1050 dev->send_agent[p][q] = agent;
1051 } else
1052 dev->send_agent[p][q] = NULL;
1053 }
1054 }
1055
1056 return 0;
1057
1058err:
1059 for (p = 0; p < dev->num_ports; ++p)
1060 for (q = 0; q <= 1; ++q)
1061 if (dev->send_agent[p][q])
1062 ib_unregister_mad_agent(dev->send_agent[p][q]);
1063
1064 return ret;
1065}
1066
1067void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev)
1068{
1069 struct ib_mad_agent *agent;
1070 int p, q;
1071
1072 for (p = 0; p < dev->num_ports; ++p) {
1073 for (q = 0; q <= 1; ++q) {
1074 agent = dev->send_agent[p][q];
1075 if (agent) {
1076 dev->send_agent[p][q] = NULL;
1077 ib_unregister_mad_agent(agent);
1078 }
1079 }
1080
1081 if (dev->sm_ah[p])
1082 rdma_destroy_ah(dev->sm_ah[p]);
1083 }
1084}
1085
1086static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num)
1087{
1088 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE);
1089
1090 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1091 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
1092 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK);
1093}
1094
1095static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num)
1096{
1097
1098 if (mlx4_is_master(dev->dev)) {
1099 mlx4_ib_invalidate_all_guid_record(dev, port_num);
1100
1101 if (!dev->sriov.is_going_down) {
1102 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0);
1103 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
1104 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK);
1105 }
1106 }
1107
1108
1109
1110
1111
1112 if (!mlx4_is_slave(dev->dev) &&
1113 dev->dev->flags & MLX4_FLAG_SECURE_HOST &&
1114 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) {
1115 if (mlx4_is_master(dev->dev))
1116
1117
1118
1119
1120 mlx4_ib_sl2vl_update(dev, port_num);
1121 else
1122 mlx4_sched_ib_sl2vl_update_work(dev, port_num);
1123 }
1124 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER);
1125}
1126
1127static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
1128 struct mlx4_eqe *eqe)
1129{
1130 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe),
1131 GET_MASK_FROM_EQE(eqe));
1132}
1133
1134static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
1135 u32 guid_tbl_blk_num, u32 change_bitmap)
1136{
1137 struct ib_smp *in_mad = NULL;
1138 struct ib_smp *out_mad = NULL;
1139 u16 i;
1140
1141 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev))
1142 return;
1143
1144 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
1145 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1146 if (!in_mad || !out_mad)
1147 goto out;
1148
1149 guid_tbl_blk_num *= 4;
1150
1151 for (i = 0; i < 4; i++) {
1152 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff)))
1153 continue;
1154 memset(in_mad, 0, sizeof *in_mad);
1155 memset(out_mad, 0, sizeof *out_mad);
1156
1157 in_mad->base_version = 1;
1158 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1159 in_mad->class_version = 1;
1160 in_mad->method = IB_MGMT_METHOD_GET;
1161 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
1162 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i);
1163
1164 if (mlx4_MAD_IFC(dev,
1165 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW,
1166 port_num, NULL, NULL, in_mad, out_mad)) {
1167 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n");
1168 goto out;
1169 }
1170
1171 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i,
1172 port_num,
1173 (u8 *)(&((struct ib_smp *)out_mad)->data));
1174 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i,
1175 port_num,
1176 (u8 *)(&((struct ib_smp *)out_mad)->data));
1177 }
1178
1179out:
1180 kfree(in_mad);
1181 kfree(out_mad);
1182 return;
1183}
1184
1185void handle_port_mgmt_change_event(struct work_struct *work)
1186{
1187 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
1188 struct mlx4_ib_dev *dev = ew->ib_dev;
1189 struct mlx4_eqe *eqe = &(ew->ib_eqe);
1190 u8 port = eqe->event.port_mgmt_change.port;
1191 u32 changed_attr;
1192 u32 tbl_block;
1193 u32 change_bitmap;
1194
1195 switch (eqe->subtype) {
1196 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO:
1197 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr);
1198
1199
1200
1201 if (changed_attr & MSTR_SM_CHANGE_MASK) {
1202 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid);
1203 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf;
1204 update_sm_ah(dev, port, lid, sl);
1205 }
1206
1207
1208 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK)
1209 handle_lid_change_event(dev, port);
1210
1211
1212 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) {
1213 if (mlx4_is_master(dev->dev)) {
1214 union ib_gid gid;
1215 int err = 0;
1216
1217 if (!eqe->event.port_mgmt_change.params.port_info.gid_prefix)
1218 err = __mlx4_ib_query_gid(&dev->ib_dev, port, 0, &gid, 1);
1219 else
1220 gid.global.subnet_prefix =
1221 eqe->event.port_mgmt_change.params.port_info.gid_prefix;
1222 if (err) {
1223 pr_warn("Could not change QP1 subnet prefix for port %d: query_gid error (%d)\n",
1224 port, err);
1225 } else {
1226 pr_debug("Changing QP1 subnet prefix for port %d. old=0x%llx. new=0x%llx\n",
1227 port,
1228 (u64)atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix),
1229 be64_to_cpu(gid.global.subnet_prefix));
1230 atomic64_set(&dev->sriov.demux[port - 1].subnet_prefix,
1231 be64_to_cpu(gid.global.subnet_prefix));
1232 }
1233 }
1234 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1235
1236 if (mlx4_is_master(dev->dev))
1237 mlx4_gen_slaves_port_mgt_ev(dev->dev, port,
1238 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK);
1239 }
1240
1241 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK)
1242 handle_client_rereg_event(dev, port);
1243 break;
1244
1245 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE:
1246 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE);
1247 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1248 propagate_pkey_ev(dev, port, eqe);
1249 break;
1250 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO:
1251
1252 if (!mlx4_is_master(dev->dev))
1253 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1254
1255 else if (!dev->sriov.is_going_down) {
1256 tbl_block = GET_BLK_PTR_FROM_EQE(eqe);
1257 change_bitmap = GET_MASK_FROM_EQE(eqe);
1258 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap);
1259 }
1260 break;
1261
1262 case MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP:
1263
1264
1265
1266 if (!mlx4_is_slave(dev->dev)) {
1267 union sl2vl_tbl_to_u64 sl2vl64;
1268 int jj;
1269
1270 for (jj = 0; jj < 8; jj++) {
1271 sl2vl64.sl8[jj] =
1272 eqe->event.port_mgmt_change.params.sl2vl_tbl_change_info.sl2vl_table[jj];
1273 pr_debug("port %u, sl2vl[%d] = %02x\n",
1274 port, jj, sl2vl64.sl8[jj]);
1275 }
1276 atomic64_set(&dev->sl2vl[port - 1], sl2vl64.sl64);
1277 }
1278 break;
1279 default:
1280 pr_warn("Unsupported subtype 0x%x for "
1281 "Port Management Change event\n", eqe->subtype);
1282 }
1283
1284 kfree(ew);
1285}
1286
1287void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
1288 enum ib_event_type type)
1289{
1290 struct ib_event event;
1291
1292 event.device = &dev->ib_dev;
1293 event.element.port_num = port_num;
1294 event.event = type;
1295
1296 ib_dispatch_event(&event);
1297}
1298
1299static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg)
1300{
1301 unsigned long flags;
1302 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context;
1303 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1304 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
1305 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE)
1306 queue_work(ctx->wq, &ctx->work);
1307 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
1308}
1309
1310static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx,
1311 struct mlx4_ib_demux_pv_qp *tun_qp,
1312 int index)
1313{
1314 struct ib_sge sg_list;
1315 struct ib_recv_wr recv_wr;
1316 const struct ib_recv_wr *bad_recv_wr;
1317 int size;
1318
1319 size = (tun_qp->qp->qp_type == IB_QPT_UD) ?
1320 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf);
1321
1322 sg_list.addr = tun_qp->ring[index].map;
1323 sg_list.length = size;
1324 sg_list.lkey = ctx->pd->local_dma_lkey;
1325
1326 recv_wr.next = NULL;
1327 recv_wr.sg_list = &sg_list;
1328 recv_wr.num_sge = 1;
1329 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV |
1330 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt);
1331 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map,
1332 size, DMA_FROM_DEVICE);
1333 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr);
1334}
1335
1336static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port,
1337 int slave, struct ib_sa_mad *sa_mad)
1338{
1339 int ret = 0;
1340
1341
1342 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
1343 case IB_SA_ATTR_MC_MEMBER_REC:
1344 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad);
1345 break;
1346 default:
1347 break;
1348 }
1349 return ret;
1350}
1351
1352static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave)
1353{
1354 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave;
1355
1356 return (qpn >= proxy_start && qpn <= proxy_start + 1);
1357}
1358
1359
1360int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
1361 enum ib_qp_type dest_qpt, u16 pkey_index,
1362 u32 remote_qpn, u32 qkey, struct rdma_ah_attr *attr,
1363 u8 *s_mac, u16 vlan_id, struct ib_mad *mad)
1364{
1365 struct ib_sge list;
1366 struct ib_ud_wr wr;
1367 const struct ib_send_wr *bad_wr;
1368 struct mlx4_ib_demux_pv_ctx *sqp_ctx;
1369 struct mlx4_ib_demux_pv_qp *sqp;
1370 struct mlx4_mad_snd_buf *sqp_mad;
1371 struct ib_ah *ah;
1372 struct ib_qp *send_qp = NULL;
1373 unsigned wire_tx_ix = 0;
1374 int ret = 0;
1375 u16 wire_pkey_ix;
1376 int src_qpnum;
1377
1378 sqp_ctx = dev->sriov.sqps[port-1];
1379
1380
1381 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE)
1382 return -EAGAIN;
1383
1384 if (dest_qpt == IB_QPT_SMI) {
1385 src_qpnum = 0;
1386 sqp = &sqp_ctx->qp[0];
1387 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
1388 } else {
1389 src_qpnum = 1;
1390 sqp = &sqp_ctx->qp[1];
1391 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index];
1392 }
1393
1394 send_qp = sqp->qp;
1395
1396
1397 ah = mlx4_ib_create_ah_slave(sqp_ctx->pd, attr,
1398 rdma_ah_retrieve_grh(attr)->sgid_index,
1399 s_mac, vlan_id);
1400 if (IS_ERR(ah))
1401 return -ENOMEM;
1402 spin_lock(&sqp->tx_lock);
1403 if (sqp->tx_ix_head - sqp->tx_ix_tail >=
1404 (MLX4_NUM_TUNNEL_BUFS - 1))
1405 ret = -EAGAIN;
1406 else
1407 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
1408 spin_unlock(&sqp->tx_lock);
1409 if (ret)
1410 goto out;
1411
1412 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr);
1413 if (sqp->tx_ring[wire_tx_ix].ah)
1414 mlx4_ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah);
1415 sqp->tx_ring[wire_tx_ix].ah = ah;
1416 ib_dma_sync_single_for_cpu(&dev->ib_dev,
1417 sqp->tx_ring[wire_tx_ix].buf.map,
1418 sizeof (struct mlx4_mad_snd_buf),
1419 DMA_TO_DEVICE);
1420
1421 memcpy(&sqp_mad->payload, mad, sizeof *mad);
1422
1423 ib_dma_sync_single_for_device(&dev->ib_dev,
1424 sqp->tx_ring[wire_tx_ix].buf.map,
1425 sizeof (struct mlx4_mad_snd_buf),
1426 DMA_TO_DEVICE);
1427
1428 list.addr = sqp->tx_ring[wire_tx_ix].buf.map;
1429 list.length = sizeof (struct mlx4_mad_snd_buf);
1430 list.lkey = sqp_ctx->pd->local_dma_lkey;
1431
1432 wr.ah = ah;
1433 wr.port_num = port;
1434 wr.pkey_index = wire_pkey_ix;
1435 wr.remote_qkey = qkey;
1436 wr.remote_qpn = remote_qpn;
1437 wr.wr.next = NULL;
1438 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum);
1439 wr.wr.sg_list = &list;
1440 wr.wr.num_sge = 1;
1441 wr.wr.opcode = IB_WR_SEND;
1442 wr.wr.send_flags = IB_SEND_SIGNALED;
1443
1444 ret = ib_post_send(send_qp, &wr.wr, &bad_wr);
1445 if (!ret)
1446 return 0;
1447
1448 spin_lock(&sqp->tx_lock);
1449 sqp->tx_ix_tail++;
1450 spin_unlock(&sqp->tx_lock);
1451 sqp->tx_ring[wire_tx_ix].ah = NULL;
1452out:
1453 mlx4_ib_destroy_ah(ah);
1454 return ret;
1455}
1456
1457static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port)
1458{
1459 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1460 return slave;
1461 return mlx4_get_base_gid_ix(dev->dev, slave, port);
1462}
1463
1464static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port,
1465 struct rdma_ah_attr *ah_attr)
1466{
1467 struct ib_global_route *grh = rdma_ah_retrieve_grh(ah_attr);
1468 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1469 grh->sgid_index = slave;
1470 else
1471 grh->sgid_index += get_slave_base_gid_ix(dev, slave, port);
1472}
1473
1474static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc)
1475{
1476 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1477 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)];
1478 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1);
1479 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr;
1480 struct mlx4_ib_ah ah;
1481 struct rdma_ah_attr ah_attr;
1482 u8 *slave_id;
1483 int slave;
1484 int port;
1485 u16 vlan_id;
1486 u8 qos;
1487 u8 *dmac;
1488
1489
1490 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn ||
1491 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX ||
1492 (wc->src_qp & 0x1) != ctx->port - 1 ||
1493 wc->src_qp & 0x4) {
1494 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp);
1495 return;
1496 }
1497 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8;
1498 if (slave != ctx->slave) {
1499 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1500 "belongs to another slave\n", wc->src_qp);
1501 return;
1502 }
1503
1504
1505 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map,
1506 sizeof (struct mlx4_tunnel_mad),
1507 DMA_FROM_DEVICE);
1508 switch (tunnel->mad.mad_hdr.method) {
1509 case IB_MGMT_METHOD_SET:
1510 case IB_MGMT_METHOD_GET:
1511 case IB_MGMT_METHOD_REPORT:
1512 case IB_SA_METHOD_GET_TABLE:
1513 case IB_SA_METHOD_DELETE:
1514 case IB_SA_METHOD_GET_MULTI:
1515 case IB_SA_METHOD_GET_TRACE_TBL:
1516 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid;
1517 if (*slave_id) {
1518 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d "
1519 "class:%d slave:%d\n", *slave_id,
1520 tunnel->mad.mad_hdr.mgmt_class, slave);
1521 return;
1522 } else
1523 *slave_id = slave;
1524 default:
1525 ;
1526 }
1527
1528
1529 switch (tunnel->mad.mad_hdr.mgmt_class) {
1530 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
1531 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
1532 if (slave != mlx4_master_func_num(dev->dev) &&
1533 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port))
1534 return;
1535 break;
1536 case IB_MGMT_CLASS_SUBN_ADM:
1537 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave,
1538 (struct ib_sa_mad *) &tunnel->mad))
1539 return;
1540 break;
1541 case IB_MGMT_CLASS_CM:
1542 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave,
1543 (struct ib_mad *) &tunnel->mad))
1544 return;
1545 break;
1546 case IB_MGMT_CLASS_DEVICE_MGMT:
1547 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET &&
1548 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET)
1549 return;
1550 break;
1551 default:
1552
1553 if (slave != mlx4_master_func_num(dev->dev)) {
1554 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d "
1555 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave);
1556 return;
1557 }
1558 }
1559
1560
1561
1562 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));
1563 ah.ibah.device = ctx->ib_dev;
1564
1565 port = be32_to_cpu(ah.av.ib.port_pd) >> 24;
1566 port = mlx4_slave_convert_port(dev->dev, slave, port);
1567 if (port < 0)
1568 return;
1569 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));
1570 ah.ibah.type = rdma_ah_find_type(&dev->ib_dev, port);
1571
1572 mlx4_ib_query_ah(&ah.ibah, &ah_attr);
1573 if (rdma_ah_get_ah_flags(&ah_attr) & IB_AH_GRH)
1574 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr);
1575 dmac = rdma_ah_retrieve_dmac(&ah_attr);
1576 if (dmac)
1577 memcpy(dmac, tunnel->hdr.mac, ETH_ALEN);
1578 vlan_id = be16_to_cpu(tunnel->hdr.vlan);
1579
1580 if (mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave,
1581 &vlan_id, &qos))
1582 rdma_ah_set_sl(&ah_attr, qos);
1583
1584 mlx4_ib_send_to_wire(dev, slave, ctx->port,
1585 is_proxy_qp0(dev, wc->src_qp, slave) ?
1586 IB_QPT_SMI : IB_QPT_GSI,
1587 be16_to_cpu(tunnel->hdr.pkey_index),
1588 be32_to_cpu(tunnel->hdr.remote_qpn),
1589 be32_to_cpu(tunnel->hdr.qkey),
1590 &ah_attr, wc->smac, vlan_id, &tunnel->mad);
1591}
1592
1593static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1594 enum ib_qp_type qp_type, int is_tun)
1595{
1596 int i;
1597 struct mlx4_ib_demux_pv_qp *tun_qp;
1598 int rx_buf_size, tx_buf_size;
1599
1600 if (qp_type > IB_QPT_GSI)
1601 return -EINVAL;
1602
1603 tun_qp = &ctx->qp[qp_type];
1604
1605 tun_qp->ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1606 sizeof(struct mlx4_ib_buf),
1607 GFP_KERNEL);
1608 if (!tun_qp->ring)
1609 return -ENOMEM;
1610
1611 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1612 sizeof (struct mlx4_ib_tun_tx_buf),
1613 GFP_KERNEL);
1614 if (!tun_qp->tx_ring) {
1615 kfree(tun_qp->ring);
1616 tun_qp->ring = NULL;
1617 return -ENOMEM;
1618 }
1619
1620 if (is_tun) {
1621 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1622 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1623 } else {
1624 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1625 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1626 }
1627
1628 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1629 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL);
1630 if (!tun_qp->ring[i].addr)
1631 goto err;
1632 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev,
1633 tun_qp->ring[i].addr,
1634 rx_buf_size,
1635 DMA_FROM_DEVICE);
1636 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) {
1637 kfree(tun_qp->ring[i].addr);
1638 goto err;
1639 }
1640 }
1641
1642 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1643 tun_qp->tx_ring[i].buf.addr =
1644 kmalloc(tx_buf_size, GFP_KERNEL);
1645 if (!tun_qp->tx_ring[i].buf.addr)
1646 goto tx_err;
1647 tun_qp->tx_ring[i].buf.map =
1648 ib_dma_map_single(ctx->ib_dev,
1649 tun_qp->tx_ring[i].buf.addr,
1650 tx_buf_size,
1651 DMA_TO_DEVICE);
1652 if (ib_dma_mapping_error(ctx->ib_dev,
1653 tun_qp->tx_ring[i].buf.map)) {
1654 kfree(tun_qp->tx_ring[i].buf.addr);
1655 goto tx_err;
1656 }
1657 tun_qp->tx_ring[i].ah = NULL;
1658 }
1659 spin_lock_init(&tun_qp->tx_lock);
1660 tun_qp->tx_ix_head = 0;
1661 tun_qp->tx_ix_tail = 0;
1662 tun_qp->proxy_qpt = qp_type;
1663
1664 return 0;
1665
1666tx_err:
1667 while (i > 0) {
1668 --i;
1669 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1670 tx_buf_size, DMA_TO_DEVICE);
1671 kfree(tun_qp->tx_ring[i].buf.addr);
1672 }
1673 kfree(tun_qp->tx_ring);
1674 tun_qp->tx_ring = NULL;
1675 i = MLX4_NUM_TUNNEL_BUFS;
1676err:
1677 while (i > 0) {
1678 --i;
1679 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1680 rx_buf_size, DMA_FROM_DEVICE);
1681 kfree(tun_qp->ring[i].addr);
1682 }
1683 kfree(tun_qp->ring);
1684 tun_qp->ring = NULL;
1685 return -ENOMEM;
1686}
1687
1688static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1689 enum ib_qp_type qp_type, int is_tun)
1690{
1691 int i;
1692 struct mlx4_ib_demux_pv_qp *tun_qp;
1693 int rx_buf_size, tx_buf_size;
1694
1695 if (qp_type > IB_QPT_GSI)
1696 return;
1697
1698 tun_qp = &ctx->qp[qp_type];
1699 if (is_tun) {
1700 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1701 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1702 } else {
1703 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1704 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1705 }
1706
1707
1708 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1709 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1710 rx_buf_size, DMA_FROM_DEVICE);
1711 kfree(tun_qp->ring[i].addr);
1712 }
1713
1714 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1715 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1716 tx_buf_size, DMA_TO_DEVICE);
1717 kfree(tun_qp->tx_ring[i].buf.addr);
1718 if (tun_qp->tx_ring[i].ah)
1719 rdma_destroy_ah(tun_qp->tx_ring[i].ah);
1720 }
1721 kfree(tun_qp->tx_ring);
1722 kfree(tun_qp->ring);
1723}
1724
1725static void mlx4_ib_tunnel_comp_worker(struct work_struct *work)
1726{
1727 struct mlx4_ib_demux_pv_ctx *ctx;
1728 struct mlx4_ib_demux_pv_qp *tun_qp;
1729 struct ib_wc wc;
1730 int ret;
1731 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1732 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1733
1734 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1735 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1736 if (wc.status == IB_WC_SUCCESS) {
1737 switch (wc.opcode) {
1738 case IB_WC_RECV:
1739 mlx4_ib_multiplex_mad(ctx, &wc);
1740 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp,
1741 wc.wr_id &
1742 (MLX4_NUM_TUNNEL_BUFS - 1));
1743 if (ret)
1744 pr_err("Failed reposting tunnel "
1745 "buf:%lld\n", wc.wr_id);
1746 break;
1747 case IB_WC_SEND:
1748 pr_debug("received tunnel send completion:"
1749 "wrid=0x%llx, status=0x%x\n",
1750 wc.wr_id, wc.status);
1751 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1752 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1753 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1754 = NULL;
1755 spin_lock(&tun_qp->tx_lock);
1756 tun_qp->tx_ix_tail++;
1757 spin_unlock(&tun_qp->tx_lock);
1758
1759 break;
1760 default:
1761 break;
1762 }
1763 } else {
1764 pr_debug("mlx4_ib: completion error in tunnel: %d."
1765 " status = %d, wrid = 0x%llx\n",
1766 ctx->slave, wc.status, wc.wr_id);
1767 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1768 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1769 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1770 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1771 = NULL;
1772 spin_lock(&tun_qp->tx_lock);
1773 tun_qp->tx_ix_tail++;
1774 spin_unlock(&tun_qp->tx_lock);
1775 }
1776 }
1777 }
1778}
1779
1780static void pv_qp_event_handler(struct ib_event *event, void *qp_context)
1781{
1782 struct mlx4_ib_demux_pv_ctx *sqp = qp_context;
1783
1784
1785 pr_err("Fatal error (%d) on a MAD QP on port %d\n",
1786 event->event, sqp->port);
1787}
1788
1789static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx,
1790 enum ib_qp_type qp_type, int create_tun)
1791{
1792 int i, ret;
1793 struct mlx4_ib_demux_pv_qp *tun_qp;
1794 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr;
1795 struct ib_qp_attr attr;
1796 int qp_attr_mask_INIT;
1797
1798 if (qp_type > IB_QPT_GSI)
1799 return -EINVAL;
1800
1801 tun_qp = &ctx->qp[qp_type];
1802
1803 memset(&qp_init_attr, 0, sizeof qp_init_attr);
1804 qp_init_attr.init_attr.send_cq = ctx->cq;
1805 qp_init_attr.init_attr.recv_cq = ctx->cq;
1806 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
1807 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS;
1808 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS;
1809 qp_init_attr.init_attr.cap.max_send_sge = 1;
1810 qp_init_attr.init_attr.cap.max_recv_sge = 1;
1811 if (create_tun) {
1812 qp_init_attr.init_attr.qp_type = IB_QPT_UD;
1813 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP;
1814 qp_init_attr.port = ctx->port;
1815 qp_init_attr.slave = ctx->slave;
1816 qp_init_attr.proxy_qp_type = qp_type;
1817 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX |
1818 IB_QP_QKEY | IB_QP_PORT;
1819 } else {
1820 qp_init_attr.init_attr.qp_type = qp_type;
1821 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP;
1822 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY;
1823 }
1824 qp_init_attr.init_attr.port_num = ctx->port;
1825 qp_init_attr.init_attr.qp_context = ctx;
1826 qp_init_attr.init_attr.event_handler = pv_qp_event_handler;
1827 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr);
1828 if (IS_ERR(tun_qp->qp)) {
1829 ret = PTR_ERR(tun_qp->qp);
1830 tun_qp->qp = NULL;
1831 pr_err("Couldn't create %s QP (%d)\n",
1832 create_tun ? "tunnel" : "special", ret);
1833 return ret;
1834 }
1835
1836 memset(&attr, 0, sizeof attr);
1837 attr.qp_state = IB_QPS_INIT;
1838 ret = 0;
1839 if (create_tun)
1840 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave,
1841 ctx->port, IB_DEFAULT_PKEY_FULL,
1842 &attr.pkey_index);
1843 if (ret || !create_tun)
1844 attr.pkey_index =
1845 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0];
1846 attr.qkey = IB_QP1_QKEY;
1847 attr.port_num = ctx->port;
1848 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT);
1849 if (ret) {
1850 pr_err("Couldn't change %s qp state to INIT (%d)\n",
1851 create_tun ? "tunnel" : "special", ret);
1852 goto err_qp;
1853 }
1854 attr.qp_state = IB_QPS_RTR;
1855 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE);
1856 if (ret) {
1857 pr_err("Couldn't change %s qp state to RTR (%d)\n",
1858 create_tun ? "tunnel" : "special", ret);
1859 goto err_qp;
1860 }
1861 attr.qp_state = IB_QPS_RTS;
1862 attr.sq_psn = 0;
1863 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
1864 if (ret) {
1865 pr_err("Couldn't change %s qp state to RTS (%d)\n",
1866 create_tun ? "tunnel" : "special", ret);
1867 goto err_qp;
1868 }
1869
1870 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1871 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i);
1872 if (ret) {
1873 pr_err(" mlx4_ib_post_pv_buf error"
1874 " (err = %d, i = %d)\n", ret, i);
1875 goto err_qp;
1876 }
1877 }
1878 return 0;
1879
1880err_qp:
1881 ib_destroy_qp(tun_qp->qp);
1882 tun_qp->qp = NULL;
1883 return ret;
1884}
1885
1886
1887
1888
1889static void mlx4_ib_sqp_comp_worker(struct work_struct *work)
1890{
1891 struct mlx4_ib_demux_pv_ctx *ctx;
1892 struct mlx4_ib_demux_pv_qp *sqp;
1893 struct ib_wc wc;
1894 struct ib_grh *grh;
1895 struct ib_mad *mad;
1896
1897 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1898 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1899
1900 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1901 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1902 if (wc.status == IB_WC_SUCCESS) {
1903 switch (wc.opcode) {
1904 case IB_WC_SEND:
1905 mlx4_ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1906 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1907 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1908 = NULL;
1909 spin_lock(&sqp->tx_lock);
1910 sqp->tx_ix_tail++;
1911 spin_unlock(&sqp->tx_lock);
1912 break;
1913 case IB_WC_RECV:
1914 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *)
1915 (sqp->ring[wc.wr_id &
1916 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload);
1917 grh = &(((struct mlx4_mad_rcv_buf *)
1918 (sqp->ring[wc.wr_id &
1919 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh);
1920 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad);
1921 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id &
1922 (MLX4_NUM_TUNNEL_BUFS - 1)))
1923 pr_err("Failed reposting SQP "
1924 "buf:%lld\n", wc.wr_id);
1925 break;
1926 default:
1927 break;
1928 }
1929 } else {
1930 pr_debug("mlx4_ib: completion error in tunnel: %d."
1931 " status = %d, wrid = 0x%llx\n",
1932 ctx->slave, wc.status, wc.wr_id);
1933 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1934 mlx4_ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1935 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1936 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1937 = NULL;
1938 spin_lock(&sqp->tx_lock);
1939 sqp->tx_ix_tail++;
1940 spin_unlock(&sqp->tx_lock);
1941 }
1942 }
1943 }
1944}
1945
1946static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1947 struct mlx4_ib_demux_pv_ctx **ret_ctx)
1948{
1949 struct mlx4_ib_demux_pv_ctx *ctx;
1950
1951 *ret_ctx = NULL;
1952 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1953 if (!ctx)
1954 return -ENOMEM;
1955
1956 ctx->ib_dev = &dev->ib_dev;
1957 ctx->port = port;
1958 ctx->slave = slave;
1959 *ret_ctx = ctx;
1960 return 0;
1961}
1962
1963static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port)
1964{
1965 if (dev->sriov.demux[port - 1].tun[slave]) {
1966 kfree(dev->sriov.demux[port - 1].tun[slave]);
1967 dev->sriov.demux[port - 1].tun[slave] = NULL;
1968 }
1969}
1970
1971static int create_pv_resources(struct ib_device *ibdev, int slave, int port,
1972 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx)
1973{
1974 int ret, cq_size;
1975 struct ib_cq_init_attr cq_attr = {};
1976
1977 if (ctx->state != DEMUX_PV_STATE_DOWN)
1978 return -EEXIST;
1979
1980 ctx->state = DEMUX_PV_STATE_STARTING;
1981
1982 if (rdma_port_get_link_layer(ibdev, ctx->port) ==
1983 IB_LINK_LAYER_INFINIBAND)
1984 ctx->has_smi = 1;
1985
1986 if (ctx->has_smi) {
1987 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun);
1988 if (ret) {
1989 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret);
1990 goto err_out;
1991 }
1992 }
1993
1994 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun);
1995 if (ret) {
1996 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret);
1997 goto err_out_qp0;
1998 }
1999
2000 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS;
2001 if (ctx->has_smi)
2002 cq_size *= 2;
2003
2004 cq_attr.cqe = cq_size;
2005 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler,
2006 NULL, ctx, &cq_attr);
2007 if (IS_ERR(ctx->cq)) {
2008 ret = PTR_ERR(ctx->cq);
2009 pr_err("Couldn't create tunnel CQ (%d)\n", ret);
2010 goto err_buf;
2011 }
2012
2013 ctx->pd = ib_alloc_pd(ctx->ib_dev, 0);
2014 if (IS_ERR(ctx->pd)) {
2015 ret = PTR_ERR(ctx->pd);
2016 pr_err("Couldn't create tunnel PD (%d)\n", ret);
2017 goto err_cq;
2018 }
2019
2020 if (ctx->has_smi) {
2021 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun);
2022 if (ret) {
2023 pr_err("Couldn't create %s QP0 (%d)\n",
2024 create_tun ? "tunnel for" : "", ret);
2025 goto err_pd;
2026 }
2027 }
2028
2029 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun);
2030 if (ret) {
2031 pr_err("Couldn't create %s QP1 (%d)\n",
2032 create_tun ? "tunnel for" : "", ret);
2033 goto err_qp0;
2034 }
2035
2036 if (create_tun)
2037 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker);
2038 else
2039 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker);
2040
2041 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq;
2042
2043 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
2044 if (ret) {
2045 pr_err("Couldn't arm tunnel cq (%d)\n", ret);
2046 goto err_wq;
2047 }
2048 ctx->state = DEMUX_PV_STATE_ACTIVE;
2049 return 0;
2050
2051err_wq:
2052 ctx->wq = NULL;
2053 ib_destroy_qp(ctx->qp[1].qp);
2054 ctx->qp[1].qp = NULL;
2055
2056
2057err_qp0:
2058 if (ctx->has_smi)
2059 ib_destroy_qp(ctx->qp[0].qp);
2060 ctx->qp[0].qp = NULL;
2061
2062err_pd:
2063 ib_dealloc_pd(ctx->pd);
2064 ctx->pd = NULL;
2065
2066err_cq:
2067 ib_destroy_cq(ctx->cq);
2068 ctx->cq = NULL;
2069
2070err_buf:
2071 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun);
2072
2073err_out_qp0:
2074 if (ctx->has_smi)
2075 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun);
2076err_out:
2077 ctx->state = DEMUX_PV_STATE_DOWN;
2078 return ret;
2079}
2080
2081static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port,
2082 struct mlx4_ib_demux_pv_ctx *ctx, int flush)
2083{
2084 if (!ctx)
2085 return;
2086 if (ctx->state > DEMUX_PV_STATE_DOWN) {
2087 ctx->state = DEMUX_PV_STATE_DOWNING;
2088 if (flush)
2089 flush_workqueue(ctx->wq);
2090 if (ctx->has_smi) {
2091 ib_destroy_qp(ctx->qp[0].qp);
2092 ctx->qp[0].qp = NULL;
2093 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1);
2094 }
2095 ib_destroy_qp(ctx->qp[1].qp);
2096 ctx->qp[1].qp = NULL;
2097 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1);
2098 ib_dealloc_pd(ctx->pd);
2099 ctx->pd = NULL;
2100 ib_destroy_cq(ctx->cq);
2101 ctx->cq = NULL;
2102 ctx->state = DEMUX_PV_STATE_DOWN;
2103 }
2104}
2105
2106static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave,
2107 int port, int do_init)
2108{
2109 int ret = 0;
2110
2111 if (!do_init) {
2112 clean_vf_mcast(&dev->sriov.demux[port - 1], slave);
2113
2114 if (slave == mlx4_master_func_num(dev->dev))
2115 destroy_pv_resources(dev, slave, port,
2116 dev->sriov.sqps[port - 1], 1);
2117
2118 destroy_pv_resources(dev, slave, port,
2119 dev->sriov.demux[port - 1].tun[slave], 1);
2120 return 0;
2121 }
2122
2123
2124 ret = create_pv_resources(&dev->ib_dev, slave, port, 1,
2125 dev->sriov.demux[port - 1].tun[slave]);
2126
2127
2128 if (!ret && slave == mlx4_master_func_num(dev->dev))
2129 ret = create_pv_resources(&dev->ib_dev, slave, port, 0,
2130 dev->sriov.sqps[port - 1]);
2131 return ret;
2132}
2133
2134void mlx4_ib_tunnels_update_work(struct work_struct *work)
2135{
2136 struct mlx4_ib_demux_work *dmxw;
2137
2138 dmxw = container_of(work, struct mlx4_ib_demux_work, work);
2139 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port,
2140 dmxw->do_init);
2141 kfree(dmxw);
2142 return;
2143}
2144
2145static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev,
2146 struct mlx4_ib_demux_ctx *ctx,
2147 int port)
2148{
2149 char name[12];
2150 int ret = 0;
2151 int i;
2152
2153 ctx->tun = kcalloc(dev->dev->caps.sqp_demux,
2154 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL);
2155 if (!ctx->tun)
2156 return -ENOMEM;
2157
2158 ctx->dev = dev;
2159 ctx->port = port;
2160 ctx->ib_dev = &dev->ib_dev;
2161
2162 for (i = 0;
2163 i < min(dev->dev->caps.sqp_demux,
2164 (u16)(dev->dev->persist->num_vfs + 1));
2165 i++) {
2166 struct mlx4_active_ports actv_ports =
2167 mlx4_get_active_ports(dev->dev, i);
2168
2169 if (!test_bit(port - 1, actv_ports.ports))
2170 continue;
2171
2172 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]);
2173 if (ret) {
2174 ret = -ENOMEM;
2175 goto err_mcg;
2176 }
2177 }
2178
2179 ret = mlx4_ib_mcg_port_init(ctx);
2180 if (ret) {
2181 pr_err("Failed initializing mcg para-virt (%d)\n", ret);
2182 goto err_mcg;
2183 }
2184
2185 snprintf(name, sizeof name, "mlx4_ibt%d", port);
2186 ctx->wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM);
2187 if (!ctx->wq) {
2188 pr_err("Failed to create tunnelling WQ for port %d\n", port);
2189 ret = -ENOMEM;
2190 goto err_wq;
2191 }
2192
2193 snprintf(name, sizeof name, "mlx4_ibud%d", port);
2194 ctx->ud_wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM);
2195 if (!ctx->ud_wq) {
2196 pr_err("Failed to create up/down WQ for port %d\n", port);
2197 ret = -ENOMEM;
2198 goto err_udwq;
2199 }
2200
2201 return 0;
2202
2203err_udwq:
2204 destroy_workqueue(ctx->wq);
2205 ctx->wq = NULL;
2206
2207err_wq:
2208 mlx4_ib_mcg_port_cleanup(ctx, 1);
2209err_mcg:
2210 for (i = 0; i < dev->dev->caps.sqp_demux; i++)
2211 free_pv_object(dev, i, port);
2212 kfree(ctx->tun);
2213 ctx->tun = NULL;
2214 return ret;
2215}
2216
2217static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx)
2218{
2219 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) {
2220 sqp_ctx->state = DEMUX_PV_STATE_DOWNING;
2221 flush_workqueue(sqp_ctx->wq);
2222 if (sqp_ctx->has_smi) {
2223 ib_destroy_qp(sqp_ctx->qp[0].qp);
2224 sqp_ctx->qp[0].qp = NULL;
2225 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0);
2226 }
2227 ib_destroy_qp(sqp_ctx->qp[1].qp);
2228 sqp_ctx->qp[1].qp = NULL;
2229 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0);
2230 ib_dealloc_pd(sqp_ctx->pd);
2231 sqp_ctx->pd = NULL;
2232 ib_destroy_cq(sqp_ctx->cq);
2233 sqp_ctx->cq = NULL;
2234 sqp_ctx->state = DEMUX_PV_STATE_DOWN;
2235 }
2236}
2237
2238static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx)
2239{
2240 int i;
2241 if (ctx) {
2242 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
2243 mlx4_ib_mcg_port_cleanup(ctx, 1);
2244 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2245 if (!ctx->tun[i])
2246 continue;
2247 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN)
2248 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING;
2249 }
2250 flush_workqueue(ctx->wq);
2251 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2252 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0);
2253 free_pv_object(dev, i, ctx->port);
2254 }
2255 kfree(ctx->tun);
2256 destroy_workqueue(ctx->ud_wq);
2257 destroy_workqueue(ctx->wq);
2258 }
2259}
2260
2261static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init)
2262{
2263 int i;
2264
2265 if (!mlx4_is_master(dev->dev))
2266 return;
2267
2268 for (i = 0; i < dev->dev->caps.num_ports; i++)
2269 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init);
2270 return;
2271}
2272
2273int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev)
2274{
2275 int i = 0;
2276 int err;
2277
2278 if (!mlx4_is_mfunc(dev->dev))
2279 return 0;
2280
2281 dev->sriov.is_going_down = 0;
2282 spin_lock_init(&dev->sriov.going_down_lock);
2283 mlx4_ib_cm_paravirt_init(dev);
2284
2285 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n");
2286
2287 if (mlx4_is_slave(dev->dev)) {
2288 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n");
2289 return 0;
2290 }
2291
2292 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2293 if (i == mlx4_master_func_num(dev->dev))
2294 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid);
2295 else
2296 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid());
2297 }
2298
2299 err = mlx4_ib_init_alias_guid_service(dev);
2300 if (err) {
2301 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n");
2302 goto paravirt_err;
2303 }
2304 err = mlx4_ib_device_register_sysfs(dev);
2305 if (err) {
2306 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n");
2307 goto sysfs_err;
2308 }
2309
2310 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n",
2311 dev->dev->caps.sqp_demux);
2312 for (i = 0; i < dev->num_ports; i++) {
2313 union ib_gid gid;
2314 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1);
2315 if (err)
2316 goto demux_err;
2317 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id;
2318 atomic64_set(&dev->sriov.demux[i].subnet_prefix,
2319 be64_to_cpu(gid.global.subnet_prefix));
2320 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1,
2321 &dev->sriov.sqps[i]);
2322 if (err)
2323 goto demux_err;
2324 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1);
2325 if (err)
2326 goto free_pv;
2327 }
2328 mlx4_ib_master_tunnels(dev, 1);
2329 return 0;
2330
2331free_pv:
2332 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2333demux_err:
2334 while (--i >= 0) {
2335 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2336 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2337 }
2338 mlx4_ib_device_unregister_sysfs(dev);
2339
2340sysfs_err:
2341 mlx4_ib_destroy_alias_guid_service(dev);
2342
2343paravirt_err:
2344 mlx4_ib_cm_paravirt_clean(dev, -1);
2345
2346 return err;
2347}
2348
2349void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev)
2350{
2351 int i;
2352 unsigned long flags;
2353
2354 if (!mlx4_is_mfunc(dev->dev))
2355 return;
2356
2357 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
2358 dev->sriov.is_going_down = 1;
2359 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
2360 if (mlx4_is_master(dev->dev)) {
2361 for (i = 0; i < dev->num_ports; i++) {
2362 flush_workqueue(dev->sriov.demux[i].ud_wq);
2363 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]);
2364 kfree(dev->sriov.sqps[i]);
2365 dev->sriov.sqps[i] = NULL;
2366 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2367 }
2368
2369 mlx4_ib_cm_paravirt_clean(dev, -1);
2370 mlx4_ib_destroy_alias_guid_service(dev);
2371 mlx4_ib_device_unregister_sysfs(dev);
2372 }
2373}
2374
