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21#include "rtl2832_priv.h"
22#include "dvb_math.h"
23#include <linux/bitops.h>
24
25
26#define MAX_XFER_SIZE 64
27
28int rtl2832_debug;
29module_param_named(debug, rtl2832_debug, int, 0644);
30MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
31
32#define REG_MASK(b) (BIT(b + 1) - 1)
33
34static const struct rtl2832_reg_entry registers[] = {
35 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
36 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
37 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
38 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
39 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
40 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
41 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
42 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
43 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
44 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
45 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
46 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
47 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
48 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
49 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
50 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
51 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
52 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
53 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
54 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
55 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
56 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
57 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
58 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
59 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
60 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
61 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
62 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
63 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
64 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
65 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
66 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
67 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
68 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
69 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
70 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
71 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
72 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
73 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
74 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
75 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
76 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
77 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
78 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
79 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
80 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
81 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
82 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
83 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
84 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
85 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
86 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
87 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
88 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
89 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
90 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
91 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
92 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
93 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
94 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
95 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
96 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
97 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
98 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
99 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
100 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
101 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
102 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
103 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
104 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
105 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
106 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
107 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
108 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
109 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
110 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
111 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
112 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
113 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
114 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
115 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
116 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
117 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
118 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
119 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
120 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
121 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
122 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
123 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
124 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
125 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
126 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
127 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
128 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
129 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
130 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
131 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
132 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
133 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
134 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
135 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
136 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
137 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
138 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
139 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
140 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
141 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
142 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
143 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
144 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
145 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
146 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
147 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
148 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
149 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
150 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
151 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
152 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
153 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
154 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
155 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
156 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
157 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
158 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
159 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
160 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
161 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
162};
163
164
165static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
166{
167 int ret;
168 u8 buf[MAX_XFER_SIZE];
169 struct i2c_msg msg[1] = {
170 {
171 .addr = priv->cfg.i2c_addr,
172 .flags = 0,
173 .len = 1 + len,
174 .buf = buf,
175 }
176 };
177
178 if (1 + len > sizeof(buf)) {
179 dev_warn(&priv->i2c->dev,
180 "%s: i2c wr reg=%04x: len=%d is too big!\n",
181 KBUILD_MODNAME, reg, len);
182 return -EINVAL;
183 }
184
185 buf[0] = reg;
186 memcpy(&buf[1], val, len);
187
188 ret = i2c_transfer(priv->i2c, msg, 1);
189 if (ret == 1) {
190 ret = 0;
191 } else {
192 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
193 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
194 ret = -EREMOTEIO;
195 }
196 return ret;
197}
198
199
200static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
201{
202 int ret;
203 struct i2c_msg msg[2] = {
204 {
205 .addr = priv->cfg.i2c_addr,
206 .flags = 0,
207 .len = 1,
208 .buf = ®,
209 }, {
210 .addr = priv->cfg.i2c_addr,
211 .flags = I2C_M_RD,
212 .len = len,
213 .buf = val,
214 }
215 };
216
217 ret = i2c_transfer(priv->i2c, msg, 2);
218 if (ret == 2) {
219 ret = 0;
220 } else {
221 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
222 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
223 ret = -EREMOTEIO;
224 }
225 return ret;
226}
227
228
229static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
230 int len)
231{
232 int ret;
233
234
235 if (page != priv->page) {
236 ret = rtl2832_wr(priv, 0x00, &page, 1);
237 if (ret)
238 return ret;
239
240 priv->page = page;
241}
242
243return rtl2832_wr(priv, reg, val, len);
244}
245
246
247static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
248 int len)
249{
250 int ret;
251
252
253 if (page != priv->page) {
254 ret = rtl2832_wr(priv, 0x00, &page, 1);
255 if (ret)
256 return ret;
257
258 priv->page = page;
259 }
260
261 return rtl2832_rd(priv, reg, val, len);
262}
263
264#if 0
265
266static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
267{
268 return rtl2832_wr_regs(priv, reg, page, &val, 1);
269}
270#endif
271
272
273static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
274{
275 return rtl2832_rd_regs(priv, reg, page, val, 1);
276}
277
278static int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
279{
280 int ret;
281
282 u8 reg_start_addr;
283 u8 msb, lsb;
284 u8 page;
285 u8 reading[4];
286 u32 reading_tmp;
287 int i;
288
289 u8 len;
290 u32 mask;
291
292 reg_start_addr = registers[reg].start_address;
293 msb = registers[reg].msb;
294 lsb = registers[reg].lsb;
295 page = registers[reg].page;
296
297 len = (msb >> 3) + 1;
298 mask = REG_MASK(msb - lsb);
299
300 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
301 if (ret)
302 goto err;
303
304 reading_tmp = 0;
305 for (i = 0; i < len; i++)
306 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
307
308 *val = (reading_tmp >> lsb) & mask;
309
310 return ret;
311
312err:
313 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
314 return ret;
315
316}
317
318static int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
319{
320 int ret, i;
321 u8 len;
322 u8 reg_start_addr;
323 u8 msb, lsb;
324 u8 page;
325 u32 mask;
326
327
328 u8 reading[4];
329 u8 writing[4];
330 u32 reading_tmp;
331 u32 writing_tmp;
332
333
334 reg_start_addr = registers[reg].start_address;
335 msb = registers[reg].msb;
336 lsb = registers[reg].lsb;
337 page = registers[reg].page;
338
339 len = (msb >> 3) + 1;
340 mask = REG_MASK(msb - lsb);
341
342
343 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
344 if (ret)
345 goto err;
346
347 reading_tmp = 0;
348 for (i = 0; i < len; i++)
349 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
350
351 writing_tmp = reading_tmp & ~(mask << lsb);
352 writing_tmp |= ((val & mask) << lsb);
353
354
355 for (i = 0; i < len; i++)
356 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
357
358 ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
359 if (ret)
360 goto err;
361
362 return ret;
363
364err:
365 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
366 return ret;
367
368}
369
370static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
371{
372 int ret;
373 struct rtl2832_priv *priv = fe->demodulator_priv;
374
375 dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
376
377
378 if (priv->i2c_gate_state == enable)
379 return 0;
380
381 ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
382 if (ret)
383 goto err;
384
385 priv->i2c_gate_state = enable;
386
387 return ret;
388err:
389 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
390 return ret;
391}
392
393
394static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
395{
396 struct rtl2832_priv *priv = fe->demodulator_priv;
397 int ret;
398 u64 pset_iffreq;
399 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
400
401
402
403
404
405
406 pset_iffreq = if_freq % priv->cfg.xtal;
407 pset_iffreq *= 0x400000;
408 pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
409 pset_iffreq = -pset_iffreq;
410 pset_iffreq = pset_iffreq & 0x3fffff;
411 dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d pset_iffreq=%08x\n",
412 __func__, if_freq, (unsigned)pset_iffreq);
413
414 ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
415 if (ret)
416 return ret;
417
418 ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
419
420 return (ret);
421}
422
423static int rtl2832_init(struct dvb_frontend *fe)
424{
425 struct rtl2832_priv *priv = fe->demodulator_priv;
426 const struct rtl2832_reg_value *init;
427 int i, ret, len;
428
429
430 struct rtl2832_reg_value rtl2832_initial_regs[] = {
431 {DVBT_AD_EN_REG, 0x1},
432 {DVBT_AD_EN_REG1, 0x1},
433 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
434 {DVBT_MGD_THD0, 0x10},
435 {DVBT_MGD_THD1, 0x20},
436 {DVBT_MGD_THD2, 0x20},
437 {DVBT_MGD_THD3, 0x40},
438 {DVBT_MGD_THD4, 0x22},
439 {DVBT_MGD_THD5, 0x32},
440 {DVBT_MGD_THD6, 0x37},
441 {DVBT_MGD_THD7, 0x39},
442 {DVBT_EN_BK_TRK, 0x0},
443 {DVBT_EN_CACQ_NOTCH, 0x0},
444 {DVBT_AD_AV_REF, 0x2a},
445 {DVBT_REG_PI, 0x6},
446 {DVBT_PIP_ON, 0x0},
447 {DVBT_CDIV_PH0, 0x8},
448 {DVBT_CDIV_PH1, 0x8},
449 {DVBT_SCALE1_B92, 0x4},
450 {DVBT_SCALE1_B93, 0xb0},
451 {DVBT_SCALE1_BA7, 0x78},
452 {DVBT_SCALE1_BA9, 0x28},
453 {DVBT_SCALE1_BAA, 0x59},
454 {DVBT_SCALE1_BAB, 0x83},
455 {DVBT_SCALE1_BAC, 0xd4},
456 {DVBT_SCALE1_BB0, 0x65},
457 {DVBT_SCALE1_BB1, 0x43},
458 {DVBT_KB_P1, 0x1},
459 {DVBT_KB_P2, 0x4},
460 {DVBT_KB_P3, 0x7},
461 {DVBT_K1_CR_STEP12, 0xa},
462 {DVBT_REG_GPE, 0x1},
463 {DVBT_SERIAL, 0x0},
464 {DVBT_CDIV_PH0, 0x9},
465 {DVBT_CDIV_PH1, 0x9},
466 {DVBT_MPEG_IO_OPT_2_2, 0x0},
467 {DVBT_MPEG_IO_OPT_1_0, 0x0},
468 {DVBT_TRK_KS_P2, 0x4},
469 {DVBT_TRK_KS_I2, 0x7},
470 {DVBT_TR_THD_SET2, 0x6},
471 {DVBT_TRK_KC_I2, 0x5},
472 {DVBT_CR_THD_SET2, 0x1},
473 };
474
475 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
476
477 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
478 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
479 rtl2832_initial_regs[i].value);
480 if (ret)
481 goto err;
482 }
483
484
485 dev_dbg(&priv->i2c->dev, "%s: load settings for tuner=%02x\n",
486 __func__, priv->cfg.tuner);
487 switch (priv->cfg.tuner) {
488 case RTL2832_TUNER_FC0012:
489 case RTL2832_TUNER_FC0013:
490 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
491 init = rtl2832_tuner_init_fc0012;
492 break;
493 case RTL2832_TUNER_TUA9001:
494 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
495 init = rtl2832_tuner_init_tua9001;
496 break;
497 case RTL2832_TUNER_E4000:
498 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
499 init = rtl2832_tuner_init_e4000;
500 break;
501 case RTL2832_TUNER_R820T:
502 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
503 init = rtl2832_tuner_init_r820t;
504 break;
505 default:
506 ret = -EINVAL;
507 goto err;
508 }
509
510 for (i = 0; i < len; i++) {
511 ret = rtl2832_wr_demod_reg(priv, init[i].reg, init[i].value);
512 if (ret)
513 goto err;
514 }
515
516 if (!fe->ops.tuner_ops.get_if_frequency) {
517 ret = rtl2832_set_if(fe, priv->cfg.if_dvbt);
518 if (ret)
519 goto err;
520 }
521
522
523
524
525
526#if 1
527
528 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
529 if (ret)
530 goto err;
531
532 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
533 if (ret)
534 goto err;
535#endif
536
537 priv->sleeping = false;
538
539 return ret;
540
541err:
542 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
543 return ret;
544}
545
546static int rtl2832_sleep(struct dvb_frontend *fe)
547{
548 struct rtl2832_priv *priv = fe->demodulator_priv;
549
550 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
551 priv->sleeping = true;
552 return 0;
553}
554
555static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
556 struct dvb_frontend_tune_settings *s)
557{
558 struct rtl2832_priv *priv = fe->demodulator_priv;
559
560 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
561 s->min_delay_ms = 1000;
562 s->step_size = fe->ops.info.frequency_stepsize * 2;
563 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
564 return 0;
565}
566
567static int rtl2832_set_frontend(struct dvb_frontend *fe)
568{
569 struct rtl2832_priv *priv = fe->demodulator_priv;
570 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
571 int ret, i, j;
572 u64 bw_mode, num, num2;
573 u32 resamp_ratio, cfreq_off_ratio;
574 static u8 bw_params[3][32] = {
575
576 {
577 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
578 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
579 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
580 0x19, 0xe0,
581 },
582
583
584 {
585 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
586 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
587 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
588 0x19, 0x10,
589 },
590
591
592 {
593 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
594 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
595 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
596 0x19, 0xe0,
597 },
598 };
599
600
601 dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d " \
602 "inversion=%d\n", __func__, c->frequency,
603 c->bandwidth_hz, c->inversion);
604
605
606 if (fe->ops.tuner_ops.set_params)
607 fe->ops.tuner_ops.set_params(fe);
608
609
610 if (fe->ops.tuner_ops.get_if_frequency) {
611 u32 if_freq;
612
613 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
614 if (ret)
615 goto err;
616
617 ret = rtl2832_set_if(fe, if_freq);
618 if (ret)
619 goto err;
620 }
621
622 switch (c->bandwidth_hz) {
623 case 6000000:
624 i = 0;
625 bw_mode = 48000000;
626 break;
627 case 7000000:
628 i = 1;
629 bw_mode = 56000000;
630 break;
631 case 8000000:
632 i = 2;
633 bw_mode = 64000000;
634 break;
635 default:
636 dev_dbg(&priv->i2c->dev, "%s: invalid bandwidth\n", __func__);
637 return -EINVAL;
638 }
639
640 for (j = 0; j < sizeof(bw_params[0]); j++) {
641 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
642 if (ret)
643 goto err;
644 }
645
646
647
648
649
650 num = priv->cfg.xtal * 7;
651 num *= 0x400000;
652 num = div_u64(num, bw_mode);
653 resamp_ratio = num & 0x3ffffff;
654 ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
655 if (ret)
656 goto err;
657
658
659
660
661
662 num = bw_mode << 20;
663 num2 = priv->cfg.xtal * 7;
664 num = div_u64(num, num2);
665 num = -num;
666 cfreq_off_ratio = num & 0xfffff;
667 ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
668 if (ret)
669 goto err;
670
671
672
673 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
674 if (ret)
675 goto err;
676
677 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
678 if (ret)
679 goto err;
680
681 return ret;
682err:
683 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
684 return ret;
685}
686
687static int rtl2832_get_frontend(struct dvb_frontend *fe)
688{
689 struct rtl2832_priv *priv = fe->demodulator_priv;
690 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
691 int ret;
692 u8 buf[3];
693
694 if (priv->sleeping)
695 return 0;
696
697 ret = rtl2832_rd_regs(priv, 0x3c, 3, buf, 2);
698 if (ret)
699 goto err;
700
701 ret = rtl2832_rd_reg(priv, 0x51, 3, &buf[2]);
702 if (ret)
703 goto err;
704
705 dev_dbg(&priv->i2c->dev, "%s: TPS=%*ph\n", __func__, 3, buf);
706
707 switch ((buf[0] >> 2) & 3) {
708 case 0:
709 c->modulation = QPSK;
710 break;
711 case 1:
712 c->modulation = QAM_16;
713 break;
714 case 2:
715 c->modulation = QAM_64;
716 break;
717 }
718
719 switch ((buf[2] >> 2) & 1) {
720 case 0:
721 c->transmission_mode = TRANSMISSION_MODE_2K;
722 break;
723 case 1:
724 c->transmission_mode = TRANSMISSION_MODE_8K;
725 }
726
727 switch ((buf[2] >> 0) & 3) {
728 case 0:
729 c->guard_interval = GUARD_INTERVAL_1_32;
730 break;
731 case 1:
732 c->guard_interval = GUARD_INTERVAL_1_16;
733 break;
734 case 2:
735 c->guard_interval = GUARD_INTERVAL_1_8;
736 break;
737 case 3:
738 c->guard_interval = GUARD_INTERVAL_1_4;
739 break;
740 }
741
742 switch ((buf[0] >> 4) & 7) {
743 case 0:
744 c->hierarchy = HIERARCHY_NONE;
745 break;
746 case 1:
747 c->hierarchy = HIERARCHY_1;
748 break;
749 case 2:
750 c->hierarchy = HIERARCHY_2;
751 break;
752 case 3:
753 c->hierarchy = HIERARCHY_4;
754 break;
755 }
756
757 switch ((buf[1] >> 3) & 7) {
758 case 0:
759 c->code_rate_HP = FEC_1_2;
760 break;
761 case 1:
762 c->code_rate_HP = FEC_2_3;
763 break;
764 case 2:
765 c->code_rate_HP = FEC_3_4;
766 break;
767 case 3:
768 c->code_rate_HP = FEC_5_6;
769 break;
770 case 4:
771 c->code_rate_HP = FEC_7_8;
772 break;
773 }
774
775 switch ((buf[1] >> 0) & 7) {
776 case 0:
777 c->code_rate_LP = FEC_1_2;
778 break;
779 case 1:
780 c->code_rate_LP = FEC_2_3;
781 break;
782 case 2:
783 c->code_rate_LP = FEC_3_4;
784 break;
785 case 3:
786 c->code_rate_LP = FEC_5_6;
787 break;
788 case 4:
789 c->code_rate_LP = FEC_7_8;
790 break;
791 }
792
793 return 0;
794err:
795 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
796 return ret;
797}
798
799static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
800{
801 struct rtl2832_priv *priv = fe->demodulator_priv;
802 int ret;
803 u32 tmp;
804 *status = 0;
805
806 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
807 if (priv->sleeping)
808 return 0;
809
810 ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
811 if (ret)
812 goto err;
813
814 if (tmp == 11) {
815 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
816 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
817 }
818
819
820
821
822
823
824 return ret;
825err:
826 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
827 return ret;
828}
829
830static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
831{
832 struct rtl2832_priv *priv = fe->demodulator_priv;
833 int ret, hierarchy, constellation;
834 u8 buf[2], tmp;
835 u16 tmp16;
836#define CONSTELLATION_NUM 3
837#define HIERARCHY_NUM 4
838 static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
839 { 85387325, 85387325, 85387325, 85387325 },
840 { 86676178, 86676178, 87167949, 87795660 },
841 { 87659938, 87659938, 87885178, 88241743 },
842 };
843
844
845
846 ret = rtl2832_rd_reg(priv, 0x3c, 3, &tmp);
847 if (ret)
848 goto err;
849
850 constellation = (tmp >> 2) & 0x03;
851 if (constellation > CONSTELLATION_NUM - 1)
852 goto err;
853
854 hierarchy = (tmp >> 4) & 0x07;
855 if (hierarchy > HIERARCHY_NUM - 1)
856 goto err;
857
858 ret = rtl2832_rd_regs(priv, 0x0c, 4, buf, 2);
859 if (ret)
860 goto err;
861
862 tmp16 = buf[0] << 8 | buf[1];
863
864 if (tmp16)
865 *snr = (snr_constant[constellation][hierarchy] -
866 intlog10(tmp16)) / ((1 << 24) / 100);
867 else
868 *snr = 0;
869
870 return 0;
871err:
872 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
873 return ret;
874}
875
876static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
877{
878 struct rtl2832_priv *priv = fe->demodulator_priv;
879 int ret;
880 u8 buf[2];
881
882 ret = rtl2832_rd_regs(priv, 0x4e, 3, buf, 2);
883 if (ret)
884 goto err;
885
886 *ber = buf[0] << 8 | buf[1];
887
888 return 0;
889err:
890 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
891 return ret;
892}
893
894static struct dvb_frontend_ops rtl2832_ops;
895
896static void rtl2832_release(struct dvb_frontend *fe)
897{
898 struct rtl2832_priv *priv = fe->demodulator_priv;
899
900 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
901 kfree(priv);
902}
903
904struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg,
905 struct i2c_adapter *i2c)
906{
907 struct rtl2832_priv *priv = NULL;
908 int ret = 0;
909 u8 tmp;
910
911 dev_dbg(&i2c->dev, "%s:\n", __func__);
912
913
914 priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
915 if (priv == NULL)
916 goto err;
917
918
919 priv->i2c = i2c;
920 priv->tuner = cfg->tuner;
921 memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config));
922
923
924 ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
925 if (ret)
926 goto err;
927
928
929 memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
930 priv->fe.demodulator_priv = priv;
931
932
933 priv->sleeping = true;
934
935 return &priv->fe;
936err:
937 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
938 kfree(priv);
939 return NULL;
940}
941EXPORT_SYMBOL(rtl2832_attach);
942
943static struct dvb_frontend_ops rtl2832_ops = {
944 .delsys = { SYS_DVBT },
945 .info = {
946 .name = "Realtek RTL2832 (DVB-T)",
947 .frequency_min = 174000000,
948 .frequency_max = 862000000,
949 .frequency_stepsize = 166667,
950 .caps = FE_CAN_FEC_1_2 |
951 FE_CAN_FEC_2_3 |
952 FE_CAN_FEC_3_4 |
953 FE_CAN_FEC_5_6 |
954 FE_CAN_FEC_7_8 |
955 FE_CAN_FEC_AUTO |
956 FE_CAN_QPSK |
957 FE_CAN_QAM_16 |
958 FE_CAN_QAM_64 |
959 FE_CAN_QAM_AUTO |
960 FE_CAN_TRANSMISSION_MODE_AUTO |
961 FE_CAN_GUARD_INTERVAL_AUTO |
962 FE_CAN_HIERARCHY_AUTO |
963 FE_CAN_RECOVER |
964 FE_CAN_MUTE_TS
965 },
966
967 .release = rtl2832_release,
968
969 .init = rtl2832_init,
970 .sleep = rtl2832_sleep,
971
972 .get_tune_settings = rtl2832_get_tune_settings,
973
974 .set_frontend = rtl2832_set_frontend,
975 .get_frontend = rtl2832_get_frontend,
976
977 .read_status = rtl2832_read_status,
978 .read_snr = rtl2832_read_snr,
979 .read_ber = rtl2832_read_ber,
980
981 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
982};
983
984MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
985MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
986MODULE_LICENSE("GPL");
987MODULE_VERSION("0.5");
988
