linux/drivers/media/i2c/adv7343.c
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   1/*
   2 * adv7343 - ADV7343 Video Encoder Driver
   3 *
   4 * The encoder hardware does not support SECAM.
   5 *
   6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation version 2.
  11 *
  12 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13 * kind, whether express or implied; without even the implied warranty
  14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20#include <linux/ctype.h>
  21#include <linux/slab.h>
  22#include <linux/i2c.h>
  23#include <linux/device.h>
  24#include <linux/delay.h>
  25#include <linux/module.h>
  26#include <linux/videodev2.h>
  27#include <linux/uaccess.h>
  28
  29#include <media/adv7343.h>
  30#include <media/v4l2-device.h>
  31#include <media/v4l2-chip-ident.h>
  32#include <media/v4l2-ctrls.h>
  33
  34#include "adv7343_regs.h"
  35
  36MODULE_DESCRIPTION("ADV7343 video encoder driver");
  37MODULE_LICENSE("GPL");
  38
  39static int debug;
  40module_param(debug, int, 0644);
  41MODULE_PARM_DESC(debug, "Debug level 0-1");
  42
  43struct adv7343_state {
  44        struct v4l2_subdev sd;
  45        struct v4l2_ctrl_handler hdl;
  46        const struct adv7343_platform_data *pdata;
  47        u8 reg00;
  48        u8 reg01;
  49        u8 reg02;
  50        u8 reg35;
  51        u8 reg80;
  52        u8 reg82;
  53        u32 output;
  54        v4l2_std_id std;
  55};
  56
  57static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
  58{
  59        return container_of(sd, struct adv7343_state, sd);
  60}
  61
  62static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  63{
  64        return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
  65}
  66
  67static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  68{
  69        struct i2c_client *client = v4l2_get_subdevdata(sd);
  70
  71        return i2c_smbus_write_byte_data(client, reg, value);
  72}
  73
  74static const u8 adv7343_init_reg_val[] = {
  75        ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
  76        ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
  77
  78        ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
  79        ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
  80        ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
  81        ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
  82        ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
  83        ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
  84        ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
  85
  86        ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
  87        ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
  88        ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
  89        ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
  90        ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
  91        ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
  92        ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
  93        ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
  94
  95        ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
  96        ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
  97        ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
  98};
  99
 100/*
 101 *                          2^32
 102 * FSC(reg) =  FSC (HZ) * --------
 103 *                        27000000
 104 */
 105static const struct adv7343_std_info stdinfo[] = {
 106        {
 107                /* FSC(Hz) = 3,579,545.45 Hz */
 108                SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
 109        }, {
 110                /* FSC(Hz) = 3,575,611.00 Hz */
 111                SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
 112        }, {
 113                /* FSC(Hz) = 3,582,056.00 */
 114                SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
 115        }, {
 116                /* FSC(Hz) = 4,433,618.75 Hz */
 117                SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
 118        }, {
 119                /* FSC(Hz) = 4,433,618.75 Hz */
 120                SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
 121        }, {
 122                /* FSC(Hz) = 4,433,618.75 Hz */
 123                SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
 124        }, {
 125                /* FSC(Hz) = 4,433,618.75 Hz */
 126                SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
 127        },
 128};
 129
 130static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
 131{
 132        struct adv7343_state *state = to_state(sd);
 133        struct adv7343_std_info *std_info;
 134        int num_std;
 135        char *fsc_ptr;
 136        u8 reg, val;
 137        int err = 0;
 138        int i = 0;
 139
 140        std_info = (struct adv7343_std_info *)stdinfo;
 141        num_std = ARRAY_SIZE(stdinfo);
 142
 143        for (i = 0; i < num_std; i++) {
 144                if (std_info[i].stdid & std)
 145                        break;
 146        }
 147
 148        if (i == num_std) {
 149                v4l2_dbg(1, debug, sd,
 150                                "Invalid std or std is not supported: %llx\n",
 151                                                (unsigned long long)std);
 152                return -EINVAL;
 153        }
 154
 155        /* Set the standard */
 156        val = state->reg80 & (~(SD_STD_MASK));
 157        val |= std_info[i].standard_val3;
 158        err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
 159        if (err < 0)
 160                goto setstd_exit;
 161
 162        state->reg80 = val;
 163
 164        /* Configure the input mode register */
 165        val = state->reg01 & (~((u8) INPUT_MODE_MASK));
 166        val |= SD_INPUT_MODE;
 167        err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
 168        if (err < 0)
 169                goto setstd_exit;
 170
 171        state->reg01 = val;
 172
 173        /* Program the sub carrier frequency registers */
 174        fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
 175        reg = ADV7343_FSC_REG0;
 176        for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
 177                err = adv7343_write(sd, reg, *fsc_ptr);
 178                if (err < 0)
 179                        goto setstd_exit;
 180        }
 181
 182        val = state->reg80;
 183
 184        /* Filter settings */
 185        if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
 186                val &= 0x03;
 187        else if (std & ~V4L2_STD_SECAM)
 188                val |= 0x04;
 189
 190        err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
 191        if (err < 0)
 192                goto setstd_exit;
 193
 194        state->reg80 = val;
 195
 196setstd_exit:
 197        if (err != 0)
 198                v4l2_err(sd, "Error setting std, write failed\n");
 199
 200        return err;
 201}
 202
 203static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
 204{
 205        struct adv7343_state *state = to_state(sd);
 206        unsigned char val;
 207        int err = 0;
 208
 209        if (output_type > ADV7343_SVIDEO_ID) {
 210                v4l2_dbg(1, debug, sd,
 211                        "Invalid output type or output type not supported:%d\n",
 212                                                                output_type);
 213                return -EINVAL;
 214        }
 215
 216        /* Enable Appropriate DAC */
 217        val = state->reg00 & 0x03;
 218
 219        /* configure default configuration */
 220        if (!state->pdata)
 221                if (output_type == ADV7343_COMPOSITE_ID)
 222                        val |= ADV7343_COMPOSITE_POWER_VALUE;
 223                else if (output_type == ADV7343_COMPONENT_ID)
 224                        val |= ADV7343_COMPONENT_POWER_VALUE;
 225                else
 226                        val |= ADV7343_SVIDEO_POWER_VALUE;
 227        else
 228                val = state->pdata->mode_config.sleep_mode << 0 |
 229                      state->pdata->mode_config.pll_control << 1 |
 230                      state->pdata->mode_config.dac_3 << 2 |
 231                      state->pdata->mode_config.dac_2 << 3 |
 232                      state->pdata->mode_config.dac_1 << 4 |
 233                      state->pdata->mode_config.dac_6 << 5 |
 234                      state->pdata->mode_config.dac_5 << 6 |
 235                      state->pdata->mode_config.dac_4 << 7;
 236
 237        err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
 238        if (err < 0)
 239                goto setoutput_exit;
 240
 241        state->reg00 = val;
 242
 243        /* Enable YUV output */
 244        val = state->reg02 | YUV_OUTPUT_SELECT;
 245        err = adv7343_write(sd, ADV7343_MODE_REG0, val);
 246        if (err < 0)
 247                goto setoutput_exit;
 248
 249        state->reg02 = val;
 250
 251        /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
 252        val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
 253
 254        if (state->pdata && state->pdata->sd_config.sd_dac_out1)
 255                val = val | (state->pdata->sd_config.sd_dac_out1 << 1);
 256        else if (state->pdata && !state->pdata->sd_config.sd_dac_out1)
 257                val = val & ~(state->pdata->sd_config.sd_dac_out1 << 1);
 258
 259        if (state->pdata && state->pdata->sd_config.sd_dac_out2)
 260                val = val | (state->pdata->sd_config.sd_dac_out2 << 2);
 261        else if (state->pdata && !state->pdata->sd_config.sd_dac_out2)
 262                val = val & ~(state->pdata->sd_config.sd_dac_out2 << 2);
 263
 264        err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
 265        if (err < 0)
 266                goto setoutput_exit;
 267
 268        state->reg82 = val;
 269
 270        /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
 271         * zero */
 272        val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
 273        err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
 274        if (err < 0)
 275                goto setoutput_exit;
 276
 277        state->reg35 = val;
 278
 279setoutput_exit:
 280        if (err != 0)
 281                v4l2_err(sd, "Error setting output, write failed\n");
 282
 283        return err;
 284}
 285
 286static int adv7343_log_status(struct v4l2_subdev *sd)
 287{
 288        struct adv7343_state *state = to_state(sd);
 289
 290        v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
 291        v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
 292                        ((state->output == 1) ? "Component" : "S-Video"));
 293        return 0;
 294}
 295
 296static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
 297{
 298        struct v4l2_subdev *sd = to_sd(ctrl);
 299
 300        switch (ctrl->id) {
 301        case V4L2_CID_BRIGHTNESS:
 302                return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
 303                                        ctrl->val);
 304
 305        case V4L2_CID_HUE:
 306                return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
 307
 308        case V4L2_CID_GAIN:
 309                return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
 310        }
 311        return -EINVAL;
 312}
 313
 314static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
 315                                struct v4l2_dbg_chip_ident *chip)
 316{
 317        struct i2c_client *client = v4l2_get_subdevdata(sd);
 318
 319        return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
 320}
 321
 322static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
 323        .s_ctrl = adv7343_s_ctrl,
 324};
 325
 326static const struct v4l2_subdev_core_ops adv7343_core_ops = {
 327        .log_status = adv7343_log_status,
 328        .g_chip_ident = adv7343_g_chip_ident,
 329        .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
 330        .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
 331        .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
 332        .g_ctrl = v4l2_subdev_g_ctrl,
 333        .s_ctrl = v4l2_subdev_s_ctrl,
 334        .queryctrl = v4l2_subdev_queryctrl,
 335        .querymenu = v4l2_subdev_querymenu,
 336};
 337
 338static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
 339{
 340        struct adv7343_state *state = to_state(sd);
 341        int err = 0;
 342
 343        if (state->std == std)
 344                return 0;
 345
 346        err = adv7343_setstd(sd, std);
 347        if (!err)
 348                state->std = std;
 349
 350        return err;
 351}
 352
 353static int adv7343_s_routing(struct v4l2_subdev *sd,
 354                u32 input, u32 output, u32 config)
 355{
 356        struct adv7343_state *state = to_state(sd);
 357        int err = 0;
 358
 359        if (state->output == output)
 360                return 0;
 361
 362        err = adv7343_setoutput(sd, output);
 363        if (!err)
 364                state->output = output;
 365
 366        return err;
 367}
 368
 369static const struct v4l2_subdev_video_ops adv7343_video_ops = {
 370        .s_std_output   = adv7343_s_std_output,
 371        .s_routing      = adv7343_s_routing,
 372};
 373
 374static const struct v4l2_subdev_ops adv7343_ops = {
 375        .core   = &adv7343_core_ops,
 376        .video  = &adv7343_video_ops,
 377};
 378
 379static int adv7343_initialize(struct v4l2_subdev *sd)
 380{
 381        struct adv7343_state *state = to_state(sd);
 382        int err = 0;
 383        int i;
 384
 385        for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
 386
 387                err = adv7343_write(sd, adv7343_init_reg_val[i],
 388                                        adv7343_init_reg_val[i+1]);
 389                if (err) {
 390                        v4l2_err(sd, "Error initializing\n");
 391                        return err;
 392                }
 393        }
 394
 395        /* Configure for default video standard */
 396        err = adv7343_setoutput(sd, state->output);
 397        if (err < 0) {
 398                v4l2_err(sd, "Error setting output during init\n");
 399                return -EINVAL;
 400        }
 401
 402        err = adv7343_setstd(sd, state->std);
 403        if (err < 0) {
 404                v4l2_err(sd, "Error setting std during init\n");
 405                return -EINVAL;
 406        }
 407
 408        return err;
 409}
 410
 411static int adv7343_probe(struct i2c_client *client,
 412                                const struct i2c_device_id *id)
 413{
 414        struct adv7343_state *state;
 415        int err;
 416
 417        if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 418                return -ENODEV;
 419
 420        v4l_info(client, "chip found @ 0x%x (%s)\n",
 421                        client->addr << 1, client->adapter->name);
 422
 423        state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
 424                             GFP_KERNEL);
 425        if (state == NULL)
 426                return -ENOMEM;
 427
 428        /* Copy board specific information here */
 429        state->pdata = client->dev.platform_data;
 430
 431        state->reg00    = 0x80;
 432        state->reg01    = 0x00;
 433        state->reg02    = 0x20;
 434        state->reg35    = 0x00;
 435        state->reg80    = ADV7343_SD_MODE_REG1_DEFAULT;
 436        state->reg82    = ADV7343_SD_MODE_REG2_DEFAULT;
 437
 438        state->output = ADV7343_COMPOSITE_ID;
 439        state->std = V4L2_STD_NTSC;
 440
 441        v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
 442
 443        v4l2_ctrl_handler_init(&state->hdl, 2);
 444        v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
 445                        V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
 446                                             ADV7343_BRIGHTNESS_MAX, 1,
 447                                             ADV7343_BRIGHTNESS_DEF);
 448        v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
 449                        V4L2_CID_HUE, ADV7343_HUE_MIN,
 450                                      ADV7343_HUE_MAX, 1,
 451                                      ADV7343_HUE_DEF);
 452        v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
 453                        V4L2_CID_GAIN, ADV7343_GAIN_MIN,
 454                                       ADV7343_GAIN_MAX, 1,
 455                                       ADV7343_GAIN_DEF);
 456        state->sd.ctrl_handler = &state->hdl;
 457        if (state->hdl.error) {
 458                int err = state->hdl.error;
 459
 460                v4l2_ctrl_handler_free(&state->hdl);
 461                return err;
 462        }
 463        v4l2_ctrl_handler_setup(&state->hdl);
 464
 465        err = adv7343_initialize(&state->sd);
 466        if (err)
 467                v4l2_ctrl_handler_free(&state->hdl);
 468        return err;
 469}
 470
 471static int adv7343_remove(struct i2c_client *client)
 472{
 473        struct v4l2_subdev *sd = i2c_get_clientdata(client);
 474        struct adv7343_state *state = to_state(sd);
 475
 476        v4l2_device_unregister_subdev(sd);
 477        v4l2_ctrl_handler_free(&state->hdl);
 478
 479        return 0;
 480}
 481
 482static const struct i2c_device_id adv7343_id[] = {
 483        {"adv7343", 0},
 484        {},
 485};
 486
 487MODULE_DEVICE_TABLE(i2c, adv7343_id);
 488
 489static struct i2c_driver adv7343_driver = {
 490        .driver = {
 491                .owner  = THIS_MODULE,
 492                .name   = "adv7343",
 493        },
 494        .probe          = adv7343_probe,
 495        .remove         = adv7343_remove,
 496        .id_table       = adv7343_id,
 497};
 498
 499module_i2c_driver(adv7343_driver);
 500