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33#ifndef ENA_COM
34#define ENA_COM
35
36#include <linux/compiler.h>
37#include <linux/delay.h>
38#include <linux/dma-mapping.h>
39#include <linux/gfp.h>
40#include <linux/io.h>
41#include <linux/sched.h>
42#include <linux/sizes.h>
43#include <linux/spinlock.h>
44#include <linux/types.h>
45#include <linux/wait.h>
46
47#include "ena_common_defs.h"
48#include "ena_admin_defs.h"
49#include "ena_eth_io_defs.h"
50#include "ena_regs_defs.h"
51
52#undef pr_fmt
53#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54
55#define ENA_MAX_NUM_IO_QUEUES 128U
56
57#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
58
59#define ENA_MAX_HANDLERS 256
60
61#define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
62
63
64#define ENA_REG_READ_TIMEOUT 200000
65
66#define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry))
67#define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry))
68#define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry))
69
70
71
72
73
74#define ENA_INTR_LOWEST_USECS (0)
75#define ENA_INTR_LOWEST_PKTS (3)
76#define ENA_INTR_LOWEST_BYTES (2 * 1524)
77
78#define ENA_INTR_LOW_USECS (32)
79#define ENA_INTR_LOW_PKTS (12)
80#define ENA_INTR_LOW_BYTES (16 * 1024)
81
82#define ENA_INTR_MID_USECS (80)
83#define ENA_INTR_MID_PKTS (48)
84#define ENA_INTR_MID_BYTES (64 * 1024)
85
86#define ENA_INTR_HIGH_USECS (128)
87#define ENA_INTR_HIGH_PKTS (96)
88#define ENA_INTR_HIGH_BYTES (128 * 1024)
89
90#define ENA_INTR_HIGHEST_USECS (192)
91#define ENA_INTR_HIGHEST_PKTS (128)
92#define ENA_INTR_HIGHEST_BYTES (192 * 1024)
93
94#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196
95#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4
96#define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6
97#define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4
98#define ENA_INTR_MODER_LEVEL_STRIDE 2
99#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF
100
101#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
102
103enum ena_intr_moder_level {
104 ENA_INTR_MODER_LOWEST = 0,
105 ENA_INTR_MODER_LOW,
106 ENA_INTR_MODER_MID,
107 ENA_INTR_MODER_HIGH,
108 ENA_INTR_MODER_HIGHEST,
109 ENA_INTR_MAX_NUM_OF_LEVELS,
110};
111
112struct ena_llq_configurations {
113 enum ena_admin_llq_header_location llq_header_location;
114 enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
115 enum ena_admin_llq_stride_ctrl llq_stride_ctrl;
116 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
117 u16 llq_ring_entry_size_value;
118};
119
120struct ena_intr_moder_entry {
121 unsigned int intr_moder_interval;
122 unsigned int pkts_per_interval;
123 unsigned int bytes_per_interval;
124};
125
126enum queue_direction {
127 ENA_COM_IO_QUEUE_DIRECTION_TX,
128 ENA_COM_IO_QUEUE_DIRECTION_RX
129};
130
131struct ena_com_buf {
132 dma_addr_t paddr;
133 u16 len;
134};
135
136struct ena_com_rx_buf_info {
137 u16 len;
138 u16 req_id;
139};
140
141struct ena_com_io_desc_addr {
142 u8 __iomem *pbuf_dev_addr;
143 u8 *virt_addr;
144 dma_addr_t phys_addr;
145};
146
147struct ena_com_tx_meta {
148 u16 mss;
149 u16 l3_hdr_len;
150 u16 l3_hdr_offset;
151 u16 l4_hdr_len;
152};
153
154struct ena_com_llq_info {
155 u16 header_location_ctrl;
156 u16 desc_stride_ctrl;
157 u16 desc_list_entry_size_ctrl;
158 u16 desc_list_entry_size;
159 u16 descs_num_before_header;
160 u16 descs_per_entry;
161};
162
163struct ena_com_io_cq {
164 struct ena_com_io_desc_addr cdesc_addr;
165
166
167 u32 __iomem *unmask_reg;
168
169
170 u32 __iomem *cq_head_db_reg;
171
172
173 u32 __iomem *numa_node_cfg_reg;
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177
178 u32 msix_vector;
179
180 enum queue_direction direction;
181
182
183 u16 cur_rx_pkt_cdesc_count;
184
185 u16 cur_rx_pkt_cdesc_start_idx;
186
187 u16 q_depth;
188
189 u16 qid;
190
191
192 u16 idx;
193 u16 head;
194 u16 last_head_update;
195 u8 phase;
196 u8 cdesc_entry_size_in_bytes;
197
198} ____cacheline_aligned;
199
200struct ena_com_io_bounce_buffer_control {
201 u8 *base_buffer;
202 u16 next_to_use;
203 u16 buffer_size;
204 u16 buffers_num;
205};
206
207
208struct ena_com_llq_pkt_ctrl {
209 u8 *curr_bounce_buf;
210 u16 idx;
211 u16 descs_left_in_line;
212};
213
214struct ena_com_io_sq {
215 struct ena_com_io_desc_addr desc_addr;
216
217 u32 __iomem *db_addr;
218 u8 __iomem *header_addr;
219
220 enum queue_direction direction;
221 enum ena_admin_placement_policy_type mem_queue_type;
222
223 u32 msix_vector;
224 struct ena_com_tx_meta cached_tx_meta;
225 struct ena_com_llq_info llq_info;
226 struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
227 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
228
229 u16 q_depth;
230 u16 qid;
231
232 u16 idx;
233 u16 tail;
234 u16 next_to_comp;
235 u16 llq_last_copy_tail;
236 u32 tx_max_header_size;
237 u8 phase;
238 u8 desc_entry_size;
239 u8 dma_addr_bits;
240} ____cacheline_aligned;
241
242struct ena_com_admin_cq {
243 struct ena_admin_acq_entry *entries;
244 dma_addr_t dma_addr;
245
246 u16 head;
247 u8 phase;
248};
249
250struct ena_com_admin_sq {
251 struct ena_admin_aq_entry *entries;
252 dma_addr_t dma_addr;
253
254 u32 __iomem *db_addr;
255
256 u16 head;
257 u16 tail;
258 u8 phase;
259
260};
261
262struct ena_com_stats_admin {
263 u32 aborted_cmd;
264 u32 submitted_cmd;
265 u32 completed_cmd;
266 u32 out_of_space;
267 u32 no_completion;
268};
269
270struct ena_com_admin_queue {
271 void *q_dmadev;
272 spinlock_t q_lock;
273
274 struct ena_comp_ctx *comp_ctx;
275 u32 completion_timeout;
276 u16 q_depth;
277 struct ena_com_admin_cq cq;
278 struct ena_com_admin_sq sq;
279
280
281 bool polling;
282
283 u16 curr_cmd_id;
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287
288 bool running_state;
289
290
291 atomic_t outstanding_cmds;
292
293 struct ena_com_stats_admin stats;
294};
295
296struct ena_aenq_handlers;
297
298struct ena_com_aenq {
299 u16 head;
300 u8 phase;
301 struct ena_admin_aenq_entry *entries;
302 dma_addr_t dma_addr;
303 u16 q_depth;
304 struct ena_aenq_handlers *aenq_handlers;
305};
306
307struct ena_com_mmio_read {
308 struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
309 dma_addr_t read_resp_dma_addr;
310 u32 reg_read_to;
311 u16 seq_num;
312 bool readless_supported;
313
314 spinlock_t lock;
315};
316
317struct ena_rss {
318
319 u16 *host_rss_ind_tbl;
320 struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
321 dma_addr_t rss_ind_tbl_dma_addr;
322 u16 tbl_log_size;
323
324
325 enum ena_admin_hash_functions hash_func;
326 struct ena_admin_feature_rss_flow_hash_control *hash_key;
327 dma_addr_t hash_key_dma_addr;
328 u32 hash_init_val;
329
330
331 struct ena_admin_feature_rss_hash_control *hash_ctrl;
332 dma_addr_t hash_ctrl_dma_addr;
333
334};
335
336struct ena_host_attribute {
337
338 u8 *debug_area_virt_addr;
339 dma_addr_t debug_area_dma_addr;
340 u32 debug_area_size;
341
342
343 struct ena_admin_host_info *host_info;
344 dma_addr_t host_info_dma_addr;
345};
346
347
348struct ena_com_dev {
349 struct ena_com_admin_queue admin_queue;
350 struct ena_com_aenq aenq;
351 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
352 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
353 u8 __iomem *reg_bar;
354 void __iomem *mem_bar;
355 void *dmadev;
356
357 enum ena_admin_placement_policy_type tx_mem_queue_type;
358 u32 tx_max_header_size;
359 u16 stats_func;
360 u16 stats_queue;
361
362 struct ena_com_mmio_read mmio_read;
363
364 struct ena_rss rss;
365 u32 supported_features;
366 u32 dma_addr_bits;
367
368 struct ena_host_attribute host_attr;
369 bool adaptive_coalescing;
370 u16 intr_delay_resolution;
371 u32 intr_moder_tx_interval;
372 struct ena_intr_moder_entry *intr_moder_tbl;
373
374 struct ena_com_llq_info llq_info;
375};
376
377struct ena_com_dev_get_features_ctx {
378 struct ena_admin_queue_feature_desc max_queues;
379 struct ena_admin_device_attr_feature_desc dev_attr;
380 struct ena_admin_feature_aenq_desc aenq;
381 struct ena_admin_feature_offload_desc offload;
382 struct ena_admin_ena_hw_hints hw_hints;
383 struct ena_admin_feature_llq_desc llq;
384};
385
386struct ena_com_create_io_ctx {
387 enum ena_admin_placement_policy_type mem_queue_type;
388 enum queue_direction direction;
389 int numa_node;
390 u32 msix_vector;
391 u16 queue_size;
392 u16 qid;
393};
394
395typedef void (*ena_aenq_handler)(void *data,
396 struct ena_admin_aenq_entry *aenq_e);
397
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399struct ena_aenq_handlers {
400 ena_aenq_handler handlers[ENA_MAX_HANDLERS];
401 ena_aenq_handler unimplemented_handler;
402};
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416int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
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422void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
423 bool readless_supported);
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429void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
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434void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
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445int ena_com_admin_init(struct ena_com_dev *ena_dev,
446 struct ena_aenq_handlers *aenq_handlers);
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455void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
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463int ena_com_dev_reset(struct ena_com_dev *ena_dev,
464 enum ena_regs_reset_reason_types reset_reason);
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474int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
475 struct ena_com_create_io_ctx *ctx);
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481void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
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491int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
492 struct ena_com_io_sq **io_sq,
493 struct ena_com_io_cq **io_cq);
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500void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
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507void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
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516bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
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524void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
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536bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev);
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546void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
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554void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
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563void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
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570void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
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582int ena_com_validate_version(struct ena_com_dev *ena_dev);
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593int ena_com_get_link_params(struct ena_com_dev *ena_dev,
594 struct ena_admin_get_feat_resp *resp);
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604int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
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614int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
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622int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
623 struct ena_com_dev_get_features_ctx *get_feat_ctx);
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631int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
632 struct ena_admin_basic_stats *stats);
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640int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
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648int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
649 struct ena_admin_feature_offload_desc *offload);
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661int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
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668void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
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684int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
685 enum ena_admin_hash_functions func,
686 const u8 *key, u16 key_len, u32 init_val);
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699int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
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714int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
715 enum ena_admin_hash_functions *func,
716 u8 *key);
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730int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
731 enum ena_admin_flow_hash_proto proto,
732 u16 hash_fields);
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743int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
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757int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
758 enum ena_admin_flow_hash_proto proto,
759 u16 *fields);
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771int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
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785int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
786 u16 entry_idx, u16 entry_value);
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796int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
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809int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
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816int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
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824int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
825 u32 debug_area_size);
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832void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
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839void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
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847int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
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857int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
858 struct ena_com_io_cq *io_cq);
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868int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
869 struct ena_com_io_cq *io_cq);
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884int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
885 struct ena_admin_aq_entry *cmd,
886 size_t cmd_size,
887 struct ena_admin_acq_entry *cmd_comp,
888 size_t cmd_comp_size);
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895int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
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900void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev);
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907bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
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913void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
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922int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
923 u32 tx_coalesce_usecs);
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932int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
933 u32 rx_coalesce_usecs);
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941unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
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949unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
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959void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
960 enum ena_intr_moder_level level,
961 struct ena_intr_moder_entry *entry);
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970void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
971 enum ena_intr_moder_level level,
972 struct ena_intr_moder_entry *entry);
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980int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
981 struct ena_admin_feature_llq_desc *llq_features,
982 struct ena_llq_configurations *llq_default_config);
983
984static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
985{
986 return ena_dev->adaptive_coalescing;
987}
988
989static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
990{
991 ena_dev->adaptive_coalescing = true;
992}
993
994static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
995{
996 ena_dev->adaptive_coalescing = false;
997}
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1007static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
1008 unsigned int pkts,
1009 unsigned int bytes,
1010 unsigned int *smoothed_interval,
1011 unsigned int *moder_tbl_idx)
1012{
1013 enum ena_intr_moder_level curr_moder_idx, new_moder_idx;
1014 struct ena_intr_moder_entry *curr_moder_entry;
1015 struct ena_intr_moder_entry *pred_moder_entry;
1016 struct ena_intr_moder_entry *new_moder_entry;
1017 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1018 unsigned int interval;
1019
1020
1021
1022
1023 if (!pkts || !bytes)
1024
1025
1026
1027 return;
1028
1029 curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx);
1030 if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) {
1031 pr_err("Wrong moderation index %u\n", curr_moder_idx);
1032 return;
1033 }
1034
1035 curr_moder_entry = &intr_moder_tbl[curr_moder_idx];
1036 new_moder_idx = curr_moder_idx;
1037
1038 if (curr_moder_idx == ENA_INTR_MODER_LOWEST) {
1039 if ((pkts > curr_moder_entry->pkts_per_interval) ||
1040 (bytes > curr_moder_entry->bytes_per_interval))
1041 new_moder_idx =
1042 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
1043 } else {
1044 pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE];
1045
1046 if ((pkts <= pred_moder_entry->pkts_per_interval) ||
1047 (bytes <= pred_moder_entry->bytes_per_interval))
1048 new_moder_idx =
1049 (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE);
1050 else if ((pkts > curr_moder_entry->pkts_per_interval) ||
1051 (bytes > curr_moder_entry->bytes_per_interval)) {
1052 if (curr_moder_idx != ENA_INTR_MODER_HIGHEST)
1053 new_moder_idx =
1054 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
1055 }
1056 }
1057 new_moder_entry = &intr_moder_tbl[new_moder_idx];
1058
1059 interval = new_moder_entry->intr_moder_interval;
1060 *smoothed_interval = (
1061 (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT +
1062 ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) /
1063 10;
1064
1065 *moder_tbl_idx = new_moder_idx;
1066}
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
1077 u32 rx_delay_interval,
1078 u32 tx_delay_interval,
1079 bool unmask)
1080{
1081 intr_reg->intr_control = 0;
1082 intr_reg->intr_control |= rx_delay_interval &
1083 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1084
1085 intr_reg->intr_control |=
1086 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1087 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1088
1089 if (unmask)
1090 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1091}
1092
1093static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
1094{
1095 u16 size, buffers_num;
1096 u8 *buf;
1097
1098 size = bounce_buf_ctrl->buffer_size;
1099 buffers_num = bounce_buf_ctrl->buffers_num;
1100
1101 buf = bounce_buf_ctrl->base_buffer +
1102 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
1103
1104 prefetchw(bounce_buf_ctrl->base_buffer +
1105 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1106
1107 return buf;
1108}
1109
1110#endif
1111