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33#include <rdma/ib_verbs.h>
34#include <linux/mlx5/fs.h>
35#include "en.h"
36#include "ipoib.h"
37
38#define IB_DEFAULT_Q_KEY 0xb1b
39#define MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE 9
40
41static int mlx5i_open(struct net_device *netdev);
42static int mlx5i_close(struct net_device *netdev);
43static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu);
44
45static const struct net_device_ops mlx5i_netdev_ops = {
46 .ndo_size = sizeof(struct net_device_ops),
47 .ndo_open = mlx5i_open,
48 .ndo_stop = mlx5i_close,
49 .ndo_get_stats64 = mlx5i_get_stats,
50 .ndo_init = mlx5i_dev_init,
51 .ndo_uninit = mlx5i_dev_cleanup,
52 .extended.ndo_change_mtu = mlx5i_change_mtu,
53 .ndo_do_ioctl = mlx5i_ioctl,
54};
55
56
57static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
58 struct mlx5e_params *params)
59{
60
61 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, false);
62 mlx5e_set_rq_type(mdev, params);
63 mlx5e_init_rq_type_params(mdev, params);
64
65
66 params->log_rq_mtu_frames = is_kdump_kernel() ?
67 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
68 MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE;
69
70 params->lro_en = false;
71 params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
72}
73
74
75int mlx5i_init(struct mlx5_core_dev *mdev,
76 struct net_device *netdev,
77 const struct mlx5e_profile *profile,
78 void *ppriv)
79{
80 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
81 u16 max_mtu;
82 int err;
83
84 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
85 if (err)
86 return err;
87
88 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
89 netdev->mtu = max_mtu;
90
91 mlx5e_build_nic_params(mdev, &priv->channels.params,
92 mlx5e_get_netdev_max_channels(netdev),
93 netdev->mtu);
94 mlx5i_build_nic_params(mdev, &priv->channels.params);
95
96 mlx5e_timestamp_init(priv);
97
98
99 netdev->hw_features |= NETIF_F_SG;
100 netdev->hw_features |= NETIF_F_IP_CSUM;
101 netdev->hw_features |= NETIF_F_IPV6_CSUM;
102 netdev->hw_features |= NETIF_F_GRO;
103 netdev->hw_features |= NETIF_F_TSO;
104 netdev->hw_features |= NETIF_F_TSO6;
105 netdev->hw_features |= NETIF_F_RXCSUM;
106 netdev->hw_features |= NETIF_F_RXHASH;
107
108 netdev->netdev_ops = &mlx5i_netdev_ops;
109 netdev->ethtool_ops = &mlx5i_ethtool_ops;
110
111 return 0;
112}
113
114
115void mlx5i_cleanup(struct mlx5e_priv *priv)
116{
117 mlx5e_netdev_cleanup(priv->netdev, priv);
118}
119
120static void mlx5i_grp_sw_update_stats(struct mlx5e_priv *priv)
121{
122 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
123 struct mlx5e_sw_stats s = { 0 };
124 int i, j;
125
126 for (i = 0; i < max_nch; i++) {
127 struct mlx5e_channel_stats *channel_stats;
128 struct mlx5e_rq_stats *rq_stats;
129
130 channel_stats = &priv->channel_stats[i];
131 rq_stats = &channel_stats->rq;
132
133 s.rx_packets += rq_stats->packets;
134 s.rx_bytes += rq_stats->bytes;
135
136 for (j = 0; j < priv->max_opened_tc; j++) {
137 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
138
139 s.tx_packets += sq_stats->packets;
140 s.tx_bytes += sq_stats->bytes;
141 s.tx_queue_dropped += sq_stats->dropped;
142 }
143 }
144
145 memcpy(&priv->stats.sw, &s, sizeof(s));
146}
147
148void mlx5i_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
149{
150 struct mlx5e_priv *priv = mlx5i_epriv(dev);
151 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
152
153 mlx5i_grp_sw_update_stats(priv);
154
155 stats->rx_packets = sstats->rx_packets;
156 stats->rx_bytes = sstats->rx_bytes;
157 stats->tx_packets = sstats->tx_packets;
158 stats->tx_bytes = sstats->tx_bytes;
159 stats->tx_dropped = sstats->tx_queue_dropped;
160}
161
162int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
163{
164 struct mlx5_core_dev *mdev = priv->mdev;
165 struct mlx5i_priv *ipriv = priv->ppriv;
166 struct mlx5_core_qp *qp = &ipriv->qp;
167 struct mlx5_qp_context *context;
168 int ret;
169
170
171 context = kzalloc(sizeof(*context), GFP_KERNEL);
172 if (!context)
173 return -ENOMEM;
174
175 context->flags = cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
176 context->pri_path.port = 1;
177 context->pri_path.pkey_index = cpu_to_be16(ipriv->pkey_index);
178 context->qkey = cpu_to_be32(IB_DEFAULT_Q_KEY);
179
180 ret = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RST2INIT_QP, 0, context, qp);
181 if (ret) {
182 mlx5_core_err(mdev, "Failed to modify qp RST2INIT, err: %d\n", ret);
183 goto err_qp_modify_to_err;
184 }
185 memset(context, 0, sizeof(*context));
186
187 ret = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_INIT2RTR_QP, 0, context, qp);
188 if (ret) {
189 mlx5_core_err(mdev, "Failed to modify qp INIT2RTR, err: %d\n", ret);
190 goto err_qp_modify_to_err;
191 }
192
193 ret = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RTR2RTS_QP, 0, context, qp);
194 if (ret) {
195 mlx5_core_err(mdev, "Failed to modify qp RTR2RTS, err: %d\n", ret);
196 goto err_qp_modify_to_err;
197 }
198
199 kfree(context);
200 return 0;
201
202err_qp_modify_to_err:
203 mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2ERR_QP, 0, &context, qp);
204 kfree(context);
205 return ret;
206}
207
208void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv)
209{
210 struct mlx5i_priv *ipriv = priv->ppriv;
211 struct mlx5_core_dev *mdev = priv->mdev;
212 struct mlx5_qp_context context;
213 int err;
214
215 err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2RST_QP, 0, &context,
216 &ipriv->qp);
217 if (err)
218 mlx5_core_err(mdev, "Failed to modify qp 2RST, err: %d\n", err);
219}
220
221#define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2
222
223int mlx5i_create_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp)
224{
225 u32 *in = NULL;
226 void *addr_path;
227 int ret = 0;
228 int inlen;
229 void *qpc;
230
231 inlen = MLX5_ST_SZ_BYTES(create_qp_in);
232 in = kvzalloc(inlen, GFP_KERNEL);
233 if (!in)
234 return -ENOMEM;
235
236 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
237 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
238 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
239 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode,
240 MLX5_QP_ENHANCED_ULP_STATELESS_MODE);
241
242 addr_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
243 MLX5_SET(ads, addr_path, vhca_port_num, 1);
244 MLX5_SET(ads, addr_path, grh, 1);
245
246 ret = mlx5_core_create_qp(mdev, qp, in, inlen);
247 if (ret) {
248 mlx5_core_err(mdev, "Failed creating IPoIB QP err : %d\n", ret);
249 goto out;
250 }
251
252out:
253 kvfree(in);
254 return ret;
255}
256
257void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp)
258{
259 mlx5_core_destroy_qp(mdev, qp);
260}
261
262static int mlx5i_init_tx(struct mlx5e_priv *priv)
263{
264 struct mlx5i_priv *ipriv = priv->ppriv;
265 int err;
266
267 err = mlx5i_create_underlay_qp(priv->mdev, &ipriv->qp);
268 if (err) {
269 mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err);
270 return err;
271 }
272
273 err = mlx5e_create_tis(priv->mdev, 0 , ipriv->qp.qpn, &priv->tisn[0]);
274 if (err) {
275 mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err);
276 goto err_destroy_underlay_qp;
277 }
278
279 return 0;
280
281err_destroy_underlay_qp:
282 mlx5i_destroy_underlay_qp(priv->mdev, &ipriv->qp);
283 return err;
284}
285
286static void mlx5i_cleanup_tx(struct mlx5e_priv *priv)
287{
288 struct mlx5i_priv *ipriv = priv->ppriv;
289
290 mlx5e_destroy_tis(priv->mdev, priv->tisn[0]);
291 mlx5i_destroy_underlay_qp(priv->mdev, &ipriv->qp);
292}
293
294static int mlx5i_create_flow_steering(struct mlx5e_priv *priv)
295{
296 struct ttc_params ttc_params = {};
297 int tt, err;
298
299 priv->fs.ns = mlx5_get_flow_namespace(priv->mdev,
300 MLX5_FLOW_NAMESPACE_KERNEL);
301
302 if (!priv->fs.ns)
303 return -EINVAL;
304
305 err = mlx5e_arfs_create_tables(priv);
306 if (err) {
307 netdev_err(priv->netdev, "Failed to create arfs tables, err=%d\n",
308 err);
309 priv->netdev->hw_features &= ~NETIF_F_NTUPLE;
310 }
311
312 mlx5e_set_ttc_basic_params(priv, &ttc_params);
313 mlx5e_set_inner_ttc_ft_params(&ttc_params);
314 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
315 ttc_params.indir_tirn[tt] = priv->inner_indir_tir[tt].tirn;
316
317 err = mlx5e_create_inner_ttc_table(priv, &ttc_params, &priv->fs.inner_ttc);
318 if (err) {
319 netdev_err(priv->netdev, "Failed to create inner ttc table, err=%d\n",
320 err);
321 goto err_destroy_arfs_tables;
322 }
323
324 mlx5e_set_ttc_ft_params(&ttc_params);
325 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
326 ttc_params.indir_tirn[tt] = priv->indir_tir[tt].tirn;
327
328 err = mlx5e_create_ttc_table(priv, &ttc_params, &priv->fs.ttc);
329 if (err) {
330 netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n",
331 err);
332 goto err_destroy_inner_ttc_table;
333 }
334
335 return 0;
336
337err_destroy_inner_ttc_table:
338 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc);
339err_destroy_arfs_tables:
340 mlx5e_arfs_destroy_tables(priv);
341
342 return err;
343}
344
345static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv)
346{
347 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc);
348 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc);
349 mlx5e_arfs_destroy_tables(priv);
350}
351
352static int mlx5i_init_rx(struct mlx5e_priv *priv)
353{
354 struct mlx5_core_dev *mdev = priv->mdev;
355 int err;
356
357 mlx5e_create_q_counters(priv);
358
359 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
360 if (err) {
361 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
362 goto err_destroy_q_counters;
363 }
364
365 err = mlx5e_create_indirect_rqt(priv);
366 if (err)
367 goto err_close_drop_rq;
368
369 err = mlx5e_create_direct_rqts(priv);
370 if (err)
371 goto err_destroy_indirect_rqts;
372
373 err = mlx5e_create_indirect_tirs(priv, true);
374 if (err)
375 goto err_destroy_direct_rqts;
376
377 err = mlx5e_create_direct_tirs(priv);
378 if (err)
379 goto err_destroy_indirect_tirs;
380
381 err = mlx5i_create_flow_steering(priv);
382 if (err)
383 goto err_destroy_direct_tirs;
384
385 return 0;
386
387err_destroy_direct_tirs:
388 mlx5e_destroy_direct_tirs(priv);
389err_destroy_indirect_tirs:
390 mlx5e_destroy_indirect_tirs(priv, true);
391err_destroy_direct_rqts:
392 mlx5e_destroy_direct_rqts(priv);
393err_destroy_indirect_rqts:
394 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
395err_close_drop_rq:
396 mlx5e_close_drop_rq(&priv->drop_rq);
397err_destroy_q_counters:
398 mlx5e_destroy_q_counters(priv);
399 return err;
400}
401
402static void mlx5i_cleanup_rx(struct mlx5e_priv *priv)
403{
404 mlx5i_destroy_flow_steering(priv);
405 mlx5e_destroy_direct_tirs(priv);
406 mlx5e_destroy_indirect_tirs(priv, true);
407 mlx5e_destroy_direct_rqts(priv);
408 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
409 mlx5e_close_drop_rq(&priv->drop_rq);
410 mlx5e_destroy_q_counters(priv);
411}
412
413static const struct mlx5e_profile mlx5i_nic_profile = {
414 .init = mlx5i_init,
415 .cleanup = mlx5i_cleanup,
416 .init_tx = mlx5i_init_tx,
417 .cleanup_tx = mlx5i_cleanup_tx,
418 .init_rx = mlx5i_init_rx,
419 .cleanup_rx = mlx5i_cleanup_rx,
420 .enable = NULL,
421 .disable = NULL,
422 .update_stats = NULL,
423 .update_carrier = NULL,
424 .rx_handlers.handle_rx_cqe = mlx5i_handle_rx_cqe,
425 .rx_handlers.handle_rx_cqe_mpwqe = NULL,
426 .max_tc = MLX5I_MAX_NUM_TC,
427};
428
429
430
431static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu)
432{
433 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
434 struct mlx5e_channels new_channels = {};
435 struct mlx5e_params *params;
436 int err = 0;
437
438 mutex_lock(&priv->state_lock);
439
440 params = &priv->channels.params;
441
442 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
443 params->sw_mtu = new_mtu;
444 netdev->mtu = params->sw_mtu;
445 goto out;
446 }
447
448 new_channels.params = *params;
449 new_channels.params.sw_mtu = new_mtu;
450 err = mlx5e_open_channels(priv, &new_channels);
451 if (err)
452 goto out;
453
454 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
455 netdev->mtu = new_channels.params.sw_mtu;
456
457out:
458 mutex_unlock(&priv->state_lock);
459 return err;
460}
461
462int mlx5i_dev_init(struct net_device *dev)
463{
464 struct mlx5e_priv *priv = mlx5i_epriv(dev);
465 struct mlx5i_priv *ipriv = priv->ppriv;
466
467
468 dev->dev_addr[1] = (ipriv->qp.qpn >> 16) & 0xff;
469 dev->dev_addr[2] = (ipriv->qp.qpn >> 8) & 0xff;
470 dev->dev_addr[3] = (ipriv->qp.qpn) & 0xff;
471
472
473 mlx5i_pkey_add_qpn(dev ,ipriv->qp.qpn);
474
475 return 0;
476}
477
478int mlx5i_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
479{
480 struct mlx5e_priv *priv = mlx5i_epriv(dev);
481
482 switch (cmd) {
483 case SIOCSHWTSTAMP:
484 return mlx5e_hwstamp_set(priv, ifr);
485 case SIOCGHWTSTAMP:
486 return mlx5e_hwstamp_get(priv, ifr);
487 default:
488 return -EOPNOTSUPP;
489 }
490}
491
492void mlx5i_dev_cleanup(struct net_device *dev)
493{
494 struct mlx5e_priv *priv = mlx5i_epriv(dev);
495 struct mlx5i_priv *ipriv = priv->ppriv;
496
497 mlx5i_uninit_underlay_qp(priv);
498
499
500 mlx5i_pkey_del_qpn(dev, ipriv->qp.qpn);
501}
502
503static int mlx5i_open(struct net_device *netdev)
504{
505 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
506 struct mlx5i_priv *ipriv = epriv->ppriv;
507 struct mlx5_core_dev *mdev = epriv->mdev;
508 int err;
509
510 mutex_lock(&epriv->state_lock);
511
512 set_bit(MLX5E_STATE_OPENED, &epriv->state);
513
514 err = mlx5i_init_underlay_qp(epriv);
515 if (err) {
516 mlx5_core_warn(mdev, "prepare underlay qp state failed, %d\n", err);
517 goto err_clear_state_opened_flag;
518 }
519
520 err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qp.qpn);
521 if (err) {
522 mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err);
523 goto err_reset_qp;
524 }
525
526 err = mlx5e_open_channels(epriv, &epriv->channels);
527 if (err)
528 goto err_remove_fs_underlay_qp;
529
530 mlx5e_refresh_tirs(epriv, false);
531 mlx5e_activate_priv_channels(epriv);
532
533 mutex_unlock(&epriv->state_lock);
534 return 0;
535
536err_remove_fs_underlay_qp:
537 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
538err_reset_qp:
539 mlx5i_uninit_underlay_qp(epriv);
540err_clear_state_opened_flag:
541 clear_bit(MLX5E_STATE_OPENED, &epriv->state);
542 mutex_unlock(&epriv->state_lock);
543 return err;
544}
545
546static int mlx5i_close(struct net_device *netdev)
547{
548 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
549 struct mlx5i_priv *ipriv = epriv->ppriv;
550 struct mlx5_core_dev *mdev = epriv->mdev;
551
552
553
554
555 mutex_lock(&epriv->state_lock);
556
557 if (!test_bit(MLX5E_STATE_OPENED, &epriv->state))
558 goto unlock;
559
560 clear_bit(MLX5E_STATE_OPENED, &epriv->state);
561
562 netif_carrier_off(epriv->netdev);
563 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
564 mlx5e_deactivate_priv_channels(epriv);
565 mlx5e_close_channels(&epriv->channels);
566 mlx5i_uninit_underlay_qp(epriv);
567unlock:
568 mutex_unlock(&epriv->state_lock);
569 return 0;
570}
571
572
573static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca,
574 union ib_gid *gid, u16 lid, int set_qkey,
575 u32 qkey)
576{
577 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
578 struct mlx5_core_dev *mdev = epriv->mdev;
579 struct mlx5i_priv *ipriv = epriv->ppriv;
580 int err;
581
582 mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qp.qpn, gid->raw);
583 err = mlx5_core_attach_mcg(mdev, gid, ipriv->qp.qpn);
584 if (err)
585 mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n",
586 ipriv->qp.qpn, gid->raw);
587
588 if (set_qkey) {
589 mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n",
590 netdev->name, qkey);
591 ipriv->qkey = qkey;
592 }
593
594 return err;
595}
596
597static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca,
598 union ib_gid *gid, u16 lid)
599{
600 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
601 struct mlx5_core_dev *mdev = epriv->mdev;
602 struct mlx5i_priv *ipriv = epriv->ppriv;
603 int err;
604
605 mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qp.qpn, gid->raw);
606
607 err = mlx5_core_detach_mcg(mdev, gid, ipriv->qp.qpn);
608 if (err)
609 mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n",
610 ipriv->qp.qpn, gid->raw);
611
612 return err;
613}
614
615static int mlx5i_xmit(struct net_device *dev, struct sk_buff *skb,
616 struct ib_ah *address, u32 dqpn)
617{
618 struct mlx5e_priv *epriv = mlx5i_epriv(dev);
619 struct mlx5e_txqsq *sq = epriv->txq2sq[skb_get_queue_mapping(skb)];
620 struct mlx5_ib_ah *mah = to_mah(address);
621 struct mlx5i_priv *ipriv = epriv->ppriv;
622
623 return mlx5i_sq_xmit(sq, skb, &mah->av, dqpn, ipriv->qkey);
624}
625
626static void mlx5i_set_pkey_index(struct net_device *netdev, int id)
627{
628 struct mlx5i_priv *ipriv = netdev_priv(netdev);
629
630 ipriv->pkey_index = (u16)id;
631}
632
633static int mlx5i_check_required_hca_cap(struct mlx5_core_dev *mdev)
634{
635 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
636 return -EOPNOTSUPP;
637
638 if (!MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) {
639 mlx5_core_warn(mdev, "IPoIB enhanced offloads are not supported\n");
640 return -EOPNOTSUPP;
641 }
642
643 return 0;
644}
645
646static void mlx5_rdma_netdev_free(struct net_device *netdev)
647{
648 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
649 struct mlx5i_priv *ipriv = priv->ppriv;
650 const struct mlx5e_profile *profile = priv->profile;
651
652 mlx5e_detach_netdev(priv);
653 profile->cleanup(priv);
654
655 if (!ipriv->sub_interface) {
656 mlx5i_pkey_qpn_ht_cleanup(netdev);
657 mlx5e_destroy_mdev_resources(priv->mdev);
658 }
659}
660
661static bool mlx5_is_sub_interface(struct mlx5_core_dev *mdev)
662{
663 return mdev->mlx5e_res.pdn != 0;
664}
665
666static const struct mlx5e_profile *mlx5_get_profile(struct mlx5_core_dev *mdev)
667{
668 if (mlx5_is_sub_interface(mdev))
669 return mlx5i_pkey_get_profile();
670 return &mlx5i_nic_profile;
671}
672
673static int mlx5_rdma_setup_rn(struct ib_device *ibdev, u8 port_num,
674 struct net_device *netdev, void *param)
675{
676 struct mlx5_core_dev *mdev = (struct mlx5_core_dev *)param;
677 const struct mlx5e_profile *prof = mlx5_get_profile(mdev);
678 struct mlx5i_priv *ipriv;
679 struct mlx5e_priv *epriv;
680 struct rdma_netdev *rn;
681 int err;
682
683 ipriv = netdev_priv(netdev);
684 epriv = mlx5i_epriv(netdev);
685
686 ipriv->sub_interface = mlx5_is_sub_interface(mdev);
687 if (!ipriv->sub_interface) {
688 err = mlx5i_pkey_qpn_ht_init(netdev);
689 if (err) {
690 mlx5_core_warn(mdev, "allocate qpn_to_netdev ht failed\n");
691 return err;
692 }
693
694
695 err = mlx5e_create_mdev_resources(mdev);
696 if (err)
697 goto destroy_ht;
698 }
699
700 prof->init(mdev, netdev, prof, ipriv);
701
702 mlx5e_attach_netdev(epriv);
703 netif_carrier_off(netdev);
704
705
706 rn = &ipriv->rn;
707 rn->hca = ibdev;
708 rn->send = mlx5i_xmit;
709 rn->attach_mcast = mlx5i_attach_mcast;
710 rn->detach_mcast = mlx5i_detach_mcast;
711 rn->set_id = mlx5i_set_pkey_index;
712
713 netdev->extended->priv_destructor = mlx5_rdma_netdev_free;
714 netdev->extended->needs_free_netdev = 1;
715
716 return 0;
717
718destroy_ht:
719 mlx5i_pkey_qpn_ht_cleanup(netdev);
720 return err;
721}
722
723int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
724 struct ib_device *device,
725 struct rdma_netdev_alloc_params *params)
726{
727 int nch;
728 int rc;
729
730 rc = mlx5i_check_required_hca_cap(mdev);
731 if (rc)
732 return rc;
733
734 nch = mlx5e_get_max_num_channels(mdev);
735
736 *params = (struct rdma_netdev_alloc_params){
737 .sizeof_priv = sizeof(struct mlx5i_priv) +
738 sizeof(struct mlx5e_priv),
739 .txqs = nch * MLX5E_MAX_NUM_TC,
740 .rxqs = nch,
741 .param = mdev,
742 .initialize_rdma_netdev = mlx5_rdma_setup_rn,
743 };
744
745 return 0;
746}
747EXPORT_SYMBOL(mlx5_rdma_rn_get_params);
748