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2
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4
5#ifndef __RTK_MAIN_H_
6#define __RTK_MAIN_H_
7
8#include <net/mac80211.h>
9#include <linux/vmalloc.h>
10#include <linux/firmware.h>
11#include <linux/average.h>
12#include <linux/bitops.h>
13#include <linux/bitfield.h>
14#include <linux/module.h>
15
16#include "util.h"
17
18#define RTW_MAX_MAC_ID_NUM 32
19#define RTW_MAX_SEC_CAM_NUM 32
20
21#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
22
23#define RFREG_MASK 0xfffff
24#define INV_RF_DATA 0xffffffff
25#define TX_PAGE_SIZE_SHIFT 7
26
27#define RTW_CHANNEL_WIDTH_MAX 3
28#define RTW_RF_PATH_MAX 4
29#define HW_FEATURE_LEN 13
30
31extern unsigned int rtw_debug_mask;
32extern const struct ieee80211_ops rtw_ops;
33extern struct rtw_chip_info rtw8822b_hw_spec;
34extern struct rtw_chip_info rtw8822c_hw_spec;
35
36#define RTW_MAX_CHANNEL_NUM_2G 14
37#define RTW_MAX_CHANNEL_NUM_5G 49
38
39struct rtw_dev;
40
41enum rtw_hci_type {
42 RTW_HCI_TYPE_PCIE,
43 RTW_HCI_TYPE_USB,
44 RTW_HCI_TYPE_SDIO,
45
46 RTW_HCI_TYPE_UNDEFINE,
47};
48
49struct rtw_hci {
50 struct rtw_hci_ops *ops;
51 enum rtw_hci_type type;
52
53 u32 rpwm_addr;
54
55 u8 bulkout_num;
56};
57
58enum rtw_supported_band {
59 RTW_BAND_2G = 1 << 0,
60 RTW_BAND_5G = 1 << 1,
61 RTW_BAND_60G = 1 << 2,
62
63 RTW_BAND_MAX,
64};
65
66enum rtw_bandwidth {
67 RTW_CHANNEL_WIDTH_20 = 0,
68 RTW_CHANNEL_WIDTH_40 = 1,
69 RTW_CHANNEL_WIDTH_80 = 2,
70 RTW_CHANNEL_WIDTH_160 = 3,
71 RTW_CHANNEL_WIDTH_80_80 = 4,
72 RTW_CHANNEL_WIDTH_5 = 5,
73 RTW_CHANNEL_WIDTH_10 = 6,
74};
75
76enum rtw_net_type {
77 RTW_NET_NO_LINK = 0,
78 RTW_NET_AD_HOC = 1,
79 RTW_NET_MGD_LINKED = 2,
80 RTW_NET_AP_MODE = 3,
81};
82
83enum rtw_rf_type {
84 RF_1T1R = 0,
85 RF_1T2R = 1,
86 RF_2T2R = 2,
87 RF_2T3R = 3,
88 RF_2T4R = 4,
89 RF_3T3R = 5,
90 RF_3T4R = 6,
91 RF_4T4R = 7,
92 RF_TYPE_MAX,
93};
94
95enum rtw_rf_path {
96 RF_PATH_A = 0,
97 RF_PATH_B = 1,
98 RF_PATH_C = 2,
99 RF_PATH_D = 3,
100};
101
102enum rtw_bb_path {
103 BB_PATH_A = BIT(0),
104 BB_PATH_B = BIT(1),
105 BB_PATH_C = BIT(2),
106 BB_PATH_D = BIT(3),
107
108 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
109 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
110 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
111 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
112 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
113 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
114
115 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
116 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
117 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
118 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
119
120 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
121};
122
123enum rtw_rate_section {
124 RTW_RATE_SECTION_CCK = 0,
125 RTW_RATE_SECTION_OFDM,
126 RTW_RATE_SECTION_HT_1S,
127 RTW_RATE_SECTION_HT_2S,
128 RTW_RATE_SECTION_VHT_1S,
129 RTW_RATE_SECTION_VHT_2S,
130
131
132 RTW_RATE_SECTION_MAX,
133};
134
135enum rtw_wireless_set {
136 WIRELESS_CCK = 0x00000001,
137 WIRELESS_OFDM = 0x00000002,
138 WIRELESS_HT = 0x00000004,
139 WIRELESS_VHT = 0x00000008,
140};
141
142#define HT_STBC_EN BIT(0)
143#define VHT_STBC_EN BIT(1)
144#define HT_LDPC_EN BIT(0)
145#define VHT_LDPC_EN BIT(1)
146
147enum rtw_chip_type {
148 RTW_CHIP_TYPE_8822B,
149 RTW_CHIP_TYPE_8822C,
150};
151
152enum rtw_tx_queue_type {
153
154 RTW_TX_QUEUE_BK = 0x0,
155 RTW_TX_QUEUE_BE = 0x1,
156 RTW_TX_QUEUE_VI = 0x2,
157 RTW_TX_QUEUE_VO = 0x3,
158
159 RTW_TX_QUEUE_BCN = 0x4,
160 RTW_TX_QUEUE_MGMT = 0x5,
161 RTW_TX_QUEUE_HI0 = 0x6,
162 RTW_TX_QUEUE_H2C = 0x7,
163
164 RTK_MAX_TX_QUEUE_NUM
165};
166
167enum rtw_rx_queue_type {
168 RTW_RX_QUEUE_MPDU = 0x0,
169 RTW_RX_QUEUE_C2H = 0x1,
170
171 RTK_MAX_RX_QUEUE_NUM
172};
173
174enum rtw_rate_index {
175 RTW_RATEID_BGN_40M_2SS = 0,
176 RTW_RATEID_BGN_40M_1SS = 1,
177 RTW_RATEID_BGN_20M_2SS = 2,
178 RTW_RATEID_BGN_20M_1SS = 3,
179 RTW_RATEID_GN_N2SS = 4,
180 RTW_RATEID_GN_N1SS = 5,
181 RTW_RATEID_BG = 6,
182 RTW_RATEID_G = 7,
183 RTW_RATEID_B_20M = 8,
184 RTW_RATEID_ARFR0_AC_2SS = 9,
185 RTW_RATEID_ARFR1_AC_1SS = 10,
186 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
187 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
188 RTW_RATEID_ARFR4_AC_3SS = 13,
189 RTW_RATEID_ARFR5_N_3SS = 14,
190 RTW_RATEID_ARFR7_N_4SS = 15,
191 RTW_RATEID_ARFR6_AC_4SS = 16
192};
193
194enum rtw_trx_desc_rate {
195 DESC_RATE1M = 0x00,
196 DESC_RATE2M = 0x01,
197 DESC_RATE5_5M = 0x02,
198 DESC_RATE11M = 0x03,
199
200 DESC_RATE6M = 0x04,
201 DESC_RATE9M = 0x05,
202 DESC_RATE12M = 0x06,
203 DESC_RATE18M = 0x07,
204 DESC_RATE24M = 0x08,
205 DESC_RATE36M = 0x09,
206 DESC_RATE48M = 0x0a,
207 DESC_RATE54M = 0x0b,
208
209 DESC_RATEMCS0 = 0x0c,
210 DESC_RATEMCS1 = 0x0d,
211 DESC_RATEMCS2 = 0x0e,
212 DESC_RATEMCS3 = 0x0f,
213 DESC_RATEMCS4 = 0x10,
214 DESC_RATEMCS5 = 0x11,
215 DESC_RATEMCS6 = 0x12,
216 DESC_RATEMCS7 = 0x13,
217 DESC_RATEMCS8 = 0x14,
218 DESC_RATEMCS9 = 0x15,
219 DESC_RATEMCS10 = 0x16,
220 DESC_RATEMCS11 = 0x17,
221 DESC_RATEMCS12 = 0x18,
222 DESC_RATEMCS13 = 0x19,
223 DESC_RATEMCS14 = 0x1a,
224 DESC_RATEMCS15 = 0x1b,
225 DESC_RATEMCS16 = 0x1c,
226 DESC_RATEMCS17 = 0x1d,
227 DESC_RATEMCS18 = 0x1e,
228 DESC_RATEMCS19 = 0x1f,
229 DESC_RATEMCS20 = 0x20,
230 DESC_RATEMCS21 = 0x21,
231 DESC_RATEMCS22 = 0x22,
232 DESC_RATEMCS23 = 0x23,
233 DESC_RATEMCS24 = 0x24,
234 DESC_RATEMCS25 = 0x25,
235 DESC_RATEMCS26 = 0x26,
236 DESC_RATEMCS27 = 0x27,
237 DESC_RATEMCS28 = 0x28,
238 DESC_RATEMCS29 = 0x29,
239 DESC_RATEMCS30 = 0x2a,
240 DESC_RATEMCS31 = 0x2b,
241
242 DESC_RATEVHT1SS_MCS0 = 0x2c,
243 DESC_RATEVHT1SS_MCS1 = 0x2d,
244 DESC_RATEVHT1SS_MCS2 = 0x2e,
245 DESC_RATEVHT1SS_MCS3 = 0x2f,
246 DESC_RATEVHT1SS_MCS4 = 0x30,
247 DESC_RATEVHT1SS_MCS5 = 0x31,
248 DESC_RATEVHT1SS_MCS6 = 0x32,
249 DESC_RATEVHT1SS_MCS7 = 0x33,
250 DESC_RATEVHT1SS_MCS8 = 0x34,
251 DESC_RATEVHT1SS_MCS9 = 0x35,
252
253 DESC_RATEVHT2SS_MCS0 = 0x36,
254 DESC_RATEVHT2SS_MCS1 = 0x37,
255 DESC_RATEVHT2SS_MCS2 = 0x38,
256 DESC_RATEVHT2SS_MCS3 = 0x39,
257 DESC_RATEVHT2SS_MCS4 = 0x3a,
258 DESC_RATEVHT2SS_MCS5 = 0x3b,
259 DESC_RATEVHT2SS_MCS6 = 0x3c,
260 DESC_RATEVHT2SS_MCS7 = 0x3d,
261 DESC_RATEVHT2SS_MCS8 = 0x3e,
262 DESC_RATEVHT2SS_MCS9 = 0x3f,
263
264 DESC_RATEVHT3SS_MCS0 = 0x40,
265 DESC_RATEVHT3SS_MCS1 = 0x41,
266 DESC_RATEVHT3SS_MCS2 = 0x42,
267 DESC_RATEVHT3SS_MCS3 = 0x43,
268 DESC_RATEVHT3SS_MCS4 = 0x44,
269 DESC_RATEVHT3SS_MCS5 = 0x45,
270 DESC_RATEVHT3SS_MCS6 = 0x46,
271 DESC_RATEVHT3SS_MCS7 = 0x47,
272 DESC_RATEVHT3SS_MCS8 = 0x48,
273 DESC_RATEVHT3SS_MCS9 = 0x49,
274
275 DESC_RATEVHT4SS_MCS0 = 0x4a,
276 DESC_RATEVHT4SS_MCS1 = 0x4b,
277 DESC_RATEVHT4SS_MCS2 = 0x4c,
278 DESC_RATEVHT4SS_MCS3 = 0x4d,
279 DESC_RATEVHT4SS_MCS4 = 0x4e,
280 DESC_RATEVHT4SS_MCS5 = 0x4f,
281 DESC_RATEVHT4SS_MCS6 = 0x50,
282 DESC_RATEVHT4SS_MCS7 = 0x51,
283 DESC_RATEVHT4SS_MCS8 = 0x52,
284 DESC_RATEVHT4SS_MCS9 = 0x53,
285
286 DESC_RATE_MAX,
287};
288
289enum rtw_regulatory_domains {
290 RTW_REGD_FCC = 0,
291 RTW_REGD_MKK = 1,
292 RTW_REGD_ETSI = 2,
293 RTW_REGD_WW = 3,
294
295 RTW_REGD_MAX
296};
297
298enum rtw_flags {
299 RTW_FLAG_RUNNING,
300 RTW_FLAG_FW_RUNNING,
301 RTW_FLAG_SCANNING,
302 RTW_FLAG_INACTIVE_PS,
303 RTW_FLAG_LEISURE_PS,
304 RTW_FLAG_DIG_DISABLE,
305
306 NUM_OF_RTW_FLAGS,
307};
308
309
310
311
312struct rtw_2g_1s_pwr_idx_diff {
313#ifdef __LITTLE_ENDIAN
314 s8 ofdm:4;
315 s8 bw20:4;
316#else
317 s8 bw20:4;
318 s8 ofdm:4;
319#endif
320} __packed;
321
322struct rtw_2g_ns_pwr_idx_diff {
323#ifdef __LITTLE_ENDIAN
324 s8 bw20:4;
325 s8 bw40:4;
326 s8 cck:4;
327 s8 ofdm:4;
328#else
329 s8 ofdm:4;
330 s8 cck:4;
331 s8 bw40:4;
332 s8 bw20:4;
333#endif
334} __packed;
335
336struct rtw_2g_txpwr_idx {
337 u8 cck_base[6];
338 u8 bw40_base[5];
339 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
340 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
341 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
342 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
343};
344
345struct rtw_5g_ht_1s_pwr_idx_diff {
346#ifdef __LITTLE_ENDIAN
347 s8 ofdm:4;
348 s8 bw20:4;
349#else
350 s8 bw20:4;
351 s8 ofdm:4;
352#endif
353} __packed;
354
355struct rtw_5g_ht_ns_pwr_idx_diff {
356#ifdef __LITTLE_ENDIAN
357 s8 bw20:4;
358 s8 bw40:4;
359#else
360 s8 bw40:4;
361 s8 bw20:4;
362#endif
363} __packed;
364
365struct rtw_5g_ofdm_ns_pwr_idx_diff {
366#ifdef __LITTLE_ENDIAN
367 s8 ofdm_3s:4;
368 s8 ofdm_2s:4;
369 s8 ofdm_4s:4;
370 s8 res:4;
371#else
372 s8 res:4;
373 s8 ofdm_4s:4;
374 s8 ofdm_2s:4;
375 s8 ofdm_3s:4;
376#endif
377} __packed;
378
379struct rtw_5g_vht_ns_pwr_idx_diff {
380#ifdef __LITTLE_ENDIAN
381 s8 bw160:4;
382 s8 bw80:4;
383#else
384 s8 bw80:4;
385 s8 bw160:4;
386#endif
387} __packed;
388
389struct rtw_5g_txpwr_idx {
390 u8 bw40_base[14];
391 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
392 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
393 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
394 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
395 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
396 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
397 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
398 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
399 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
400};
401
402struct rtw_txpwr_idx {
403 struct rtw_2g_txpwr_idx pwr_idx_2g;
404 struct rtw_5g_txpwr_idx pwr_idx_5g;
405};
406
407struct rtw_timer_list {
408 struct timer_list timer;
409 void (*function)(void *data);
410 void *args;
411};
412
413struct rtw_channel_params {
414 u8 center_chan;
415 u8 bandwidth;
416 u8 primary_chan_idx;
417};
418
419struct rtw_hw_reg {
420 u32 addr;
421 u32 mask;
422};
423
424struct rtw_backup_info {
425 u8 len;
426 u32 reg;
427 u32 val;
428};
429
430enum rtw_vif_port_set {
431 PORT_SET_MAC_ADDR = BIT(0),
432 PORT_SET_BSSID = BIT(1),
433 PORT_SET_NET_TYPE = BIT(2),
434 PORT_SET_AID = BIT(3),
435};
436
437struct rtw_vif_port {
438 struct rtw_hw_reg mac_addr;
439 struct rtw_hw_reg bssid;
440 struct rtw_hw_reg net_type;
441 struct rtw_hw_reg aid;
442};
443
444struct rtw_tx_pkt_info {
445 u32 tx_pkt_size;
446 u8 offset;
447 u8 pkt_offset;
448 u8 mac_id;
449 u8 rate_id;
450 u8 rate;
451 u8 qsel;
452 u8 bw;
453 u8 sec_type;
454 u8 sn;
455 bool ampdu_en;
456 u8 ampdu_factor;
457 u8 ampdu_density;
458 u16 seq;
459 bool stbc;
460 bool ldpc;
461 bool dis_rate_fallback;
462 bool bmc;
463 bool use_rate;
464 bool ls;
465 bool fs;
466 bool short_gi;
467 bool report;
468};
469
470struct rtw_rx_pkt_stat {
471 bool phy_status;
472 bool icv_err;
473 bool crc_err;
474 bool decrypted;
475 bool is_c2h;
476
477 s32 signal_power;
478 u16 pkt_len;
479 u8 bw;
480 u8 drv_info_sz;
481 u8 shift;
482 u8 rate;
483 u8 mac_id;
484 u8 cam_id;
485 u8 ppdu_cnt;
486 u32 tsf_low;
487 s8 rx_power[RTW_RF_PATH_MAX];
488 u8 rssi;
489 u8 rxsc;
490 struct rtw_sta_info *si;
491 struct ieee80211_vif *vif;
492};
493
494struct rtw_traffic_stats {
495
496 u64 tx_unicast;
497 u64 rx_unicast;
498
499
500 u64 tx_cnt;
501 u64 rx_cnt;
502
503
504 u32 tx_throughput;
505 u32 rx_throughput;
506};
507
508enum rtw_lps_mode {
509 RTW_MODE_ACTIVE = 0,
510 RTW_MODE_LPS = 1,
511 RTW_MODE_WMM_PS = 2,
512};
513
514enum rtw_pwr_state {
515 RTW_RF_OFF = 0x0,
516 RTW_RF_ON = 0x4,
517 RTW_ALL_ON = 0xc,
518};
519
520struct rtw_lps_conf {
521
522 struct rtw_vif *rtwvif;
523 enum rtw_lps_mode mode;
524 enum rtw_pwr_state state;
525 u8 awake_interval;
526 u8 rlbm;
527 u8 smart_ps;
528 u8 port_id;
529};
530
531enum rtw_hw_key_type {
532 RTW_CAM_NONE = 0,
533 RTW_CAM_WEP40 = 1,
534 RTW_CAM_TKIP = 2,
535 RTW_CAM_AES = 4,
536 RTW_CAM_WEP104 = 5,
537};
538
539struct rtw_cam_entry {
540 bool valid;
541 bool group;
542 u8 addr[ETH_ALEN];
543 u8 hw_key_type;
544 struct ieee80211_key_conf *key;
545};
546
547struct rtw_sec_desc {
548
549 bool default_key_search;
550
551 u32 total_cam_num;
552 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
553 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
554};
555
556struct rtw_tx_report {
557
558 spinlock_t q_lock;
559 struct sk_buff_head queue;
560 atomic_t sn;
561 struct timer_list purge_timer;
562};
563
564#define RTW_BC_MC_MACID 1
565#if 0
566DECLARE_EWMA(rssi, 10, 16)
567#else
568DECLARE_EWMA(rssi, 1024, 16)
569#endif
570
571struct rtw_sta_info {
572 struct ieee80211_sta *sta;
573 struct ieee80211_vif *vif;
574
575 struct ewma_rssi avg_rssi;
576 u8 rssi_level;
577
578 u8 mac_id;
579 u8 rate_id;
580 enum rtw_bandwidth bw_mode;
581 enum rtw_rf_type rf_type;
582 enum rtw_wireless_set wireless_set;
583 u8 stbc_en:2;
584 u8 ldpc_en:2;
585 bool sgi_enable;
586 bool vht_enable;
587 bool updated;
588 u8 init_ra_lv;
589 u64 ra_mask;
590};
591
592struct rtw_vif {
593 struct ieee80211_vif *vif;
594 enum rtw_net_type net_type;
595 u16 aid;
596 u8 mac_addr[ETH_ALEN];
597 u8 bssid[ETH_ALEN];
598 u8 port;
599 const struct rtw_vif_port *conf;
600
601 struct rtw_traffic_stats stats;
602 bool in_lps;
603};
604
605struct rtw_regulatory {
606 char alpha2[2];
607 u8 chplan;
608 u8 txpwr_regd;
609};
610
611struct rtw_chip_ops {
612 int (*mac_init)(struct rtw_dev *rtwdev);
613 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
614 void (*phy_set_param)(struct rtw_dev *rtwdev);
615 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
616 u8 bandwidth, u8 primary_chan_idx);
617 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
618 struct rtw_rx_pkt_stat *pkt_stat,
619 struct ieee80211_rx_status *rx_status);
620 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
621 u32 addr, u32 mask);
622 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
623 u32 addr, u32 mask, u32 data);
624 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
625 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
626 u32 size);
627 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx,
628 u8 antenna_rx);
629 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
630 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
631 void (*do_iqk)(struct rtw_dev *rtwdev);
632};
633
634#define RTW_PWR_POLLING_CNT 20000
635
636#define RTW_PWR_CMD_READ 0x00
637#define RTW_PWR_CMD_WRITE 0x01
638#define RTW_PWR_CMD_POLLING 0x02
639#define RTW_PWR_CMD_DELAY 0x03
640#define RTW_PWR_CMD_END 0x04
641
642
643#define RTW_PWR_ADDR_MAC 0x00
644#define RTW_PWR_ADDR_USB 0x01
645#define RTW_PWR_ADDR_PCIE 0x02
646#define RTW_PWR_ADDR_SDIO 0x03
647
648#define RTW_PWR_INTF_SDIO_MSK BIT(0)
649#define RTW_PWR_INTF_USB_MSK BIT(1)
650#define RTW_PWR_INTF_PCI_MSK BIT(2)
651#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
652
653#define RTW_PWR_CUT_A_MSK BIT(1)
654#define RTW_PWR_CUT_B_MSK BIT(2)
655#define RTW_PWR_CUT_C_MSK BIT(3)
656#define RTW_PWR_CUT_D_MSK BIT(4)
657#define RTW_PWR_CUT_E_MSK BIT(5)
658#define RTW_PWR_CUT_F_MSK BIT(6)
659#define RTW_PWR_CUT_G_MSK BIT(7)
660#define RTW_PWR_CUT_ALL_MSK 0xFF
661
662enum rtw_pwr_seq_cmd_delay_unit {
663 RTW_PWR_DELAY_US,
664 RTW_PWR_DELAY_MS,
665};
666
667struct rtw_pwr_seq_cmd {
668 u16 offset;
669 u8 cut_mask;
670 u8 intf_mask;
671 u8 base:4;
672 u8 cmd:4;
673 u8 mask;
674 u8 value;
675};
676
677enum rtw_chip_ver {
678 RTW_CHIP_VER_CUT_A = 0x00,
679 RTW_CHIP_VER_CUT_B = 0x01,
680 RTW_CHIP_VER_CUT_C = 0x02,
681 RTW_CHIP_VER_CUT_D = 0x03,
682 RTW_CHIP_VER_CUT_E = 0x04,
683 RTW_CHIP_VER_CUT_F = 0x05,
684 RTW_CHIP_VER_CUT_G = 0x06,
685};
686
687#define RTW_INTF_PHY_PLATFORM_ALL 0
688
689enum rtw_intf_phy_cut {
690 RTW_INTF_PHY_CUT_A = BIT(0),
691 RTW_INTF_PHY_CUT_B = BIT(1),
692 RTW_INTF_PHY_CUT_C = BIT(2),
693 RTW_INTF_PHY_CUT_D = BIT(3),
694 RTW_INTF_PHY_CUT_E = BIT(4),
695 RTW_INTF_PHY_CUT_F = BIT(5),
696 RTW_INTF_PHY_CUT_G = BIT(6),
697 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
698};
699
700enum rtw_ip_sel {
701 RTW_IP_SEL_PHY = 0,
702 RTW_IP_SEL_MAC = 1,
703 RTW_IP_SEL_DBI = 2,
704
705 RTW_IP_SEL_UNDEF = 0xFFFF
706};
707
708enum rtw_pq_map_id {
709 RTW_PQ_MAP_VO = 0x0,
710 RTW_PQ_MAP_VI = 0x1,
711 RTW_PQ_MAP_BE = 0x2,
712 RTW_PQ_MAP_BK = 0x3,
713 RTW_PQ_MAP_MG = 0x4,
714 RTW_PQ_MAP_HI = 0x5,
715 RTW_PQ_MAP_NUM = 0x6,
716
717 RTW_PQ_MAP_UNDEF,
718};
719
720enum rtw_dma_mapping {
721 RTW_DMA_MAPPING_EXTRA = 0,
722 RTW_DMA_MAPPING_LOW = 1,
723 RTW_DMA_MAPPING_NORMAL = 2,
724 RTW_DMA_MAPPING_HIGH = 3,
725
726 RTW_DMA_MAPPING_UNDEF,
727};
728
729struct rtw_rqpn {
730 enum rtw_dma_mapping dma_map_vo;
731 enum rtw_dma_mapping dma_map_vi;
732 enum rtw_dma_mapping dma_map_be;
733 enum rtw_dma_mapping dma_map_bk;
734 enum rtw_dma_mapping dma_map_mg;
735 enum rtw_dma_mapping dma_map_hi;
736};
737
738struct rtw_page_table {
739 u16 hq_num;
740 u16 nq_num;
741 u16 lq_num;
742 u16 exq_num;
743 u16 gapq_num;
744};
745
746struct rtw_intf_phy_para {
747 u16 offset;
748 u16 value;
749 u16 ip_sel;
750 u16 cut_mask;
751 u16 platform;
752};
753
754struct rtw_intf_phy_para_table {
755 struct rtw_intf_phy_para *usb2_para;
756 struct rtw_intf_phy_para *usb3_para;
757 struct rtw_intf_phy_para *gen1_para;
758 struct rtw_intf_phy_para *gen2_para;
759 u8 n_usb2_para;
760 u8 n_usb3_para;
761 u8 n_gen1_para;
762 u8 n_gen2_para;
763};
764
765struct rtw_table {
766 const void *data;
767 const u32 size;
768 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
769 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
770 u32 addr, u32 data);
771 enum rtw_rf_path rf_path;
772};
773
774static inline void rtw_load_table(struct rtw_dev *rtwdev,
775 const struct rtw_table *tbl)
776{
777 (*tbl->parse)(rtwdev, tbl);
778}
779
780enum rtw_rfe_fem {
781 RTW_RFE_IFEM,
782 RTW_RFE_EFEM,
783 RTW_RFE_IFEM2G_EFEM5G,
784 RTW_RFE_NUM,
785};
786
787struct rtw_rfe_def {
788 const struct rtw_table *phy_pg_tbl;
789 const struct rtw_table *txpwr_lmt_tbl;
790};
791
792#define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
793 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
794 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
795 }
796
797
798struct rtw_chip_info {
799 struct rtw_chip_ops *ops;
800 u8 id;
801
802 const char *fw_name;
803 u8 tx_pkt_desc_sz;
804 u8 tx_buf_desc_sz;
805 u8 rx_pkt_desc_sz;
806 u8 rx_buf_desc_sz;
807 u32 phy_efuse_size;
808 u32 log_efuse_size;
809 u32 ptct_efuse_size;
810 u32 txff_size;
811 u32 rxff_size;
812 u8 band;
813 u8 page_size;
814 u8 csi_buf_pg_num;
815 u8 dig_max;
816 u8 dig_min;
817 u8 txgi_factor;
818 bool is_pwr_by_rate_dec;
819 u8 max_power_index;
820
821 bool ht_supported;
822 bool vht_supported;
823
824
825 u8 sys_func_en;
826 struct rtw_pwr_seq_cmd **pwr_on_seq;
827 struct rtw_pwr_seq_cmd **pwr_off_seq;
828 struct rtw_rqpn *rqpn_table;
829 struct rtw_page_table *page_table;
830 struct rtw_intf_phy_para_table *intf_table;
831
832 struct rtw_hw_reg *dig;
833 u32 rf_base_addr[2];
834 u32 rf_sipi_addr[2];
835
836 const struct rtw_table *mac_tbl;
837 const struct rtw_table *agc_tbl;
838 const struct rtw_table *bb_tbl;
839 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
840 const struct rtw_table *rfk_init_tbl;
841
842 const struct rtw_rfe_def *rfe_defs;
843 u32 rfe_defs_size;
844};
845
846struct rtw_dm_info {
847 u32 cck_fa_cnt;
848 u32 ofdm_fa_cnt;
849 u32 total_fa_cnt;
850 u8 min_rssi;
851 u8 pre_min_rssi;
852 u16 fa_history[4];
853 u8 igi_history[4];
854 u8 igi_bitmap;
855 bool damping;
856 u8 damping_cnt;
857 u8 damping_rssi;
858
859 u8 cck_gi_u_bnd;
860 u8 cck_gi_l_bnd;
861};
862
863struct rtw_efuse {
864 u32 size;
865 u32 physical_size;
866 u32 logical_size;
867 u32 protect_size;
868
869 u8 addr[ETH_ALEN];
870 u8 channel_plan;
871 u8 country_code[2];
872 u8 rfe_option;
873 u8 thermal_meter;
874 u8 crystal_cap;
875 u8 ant_div_cfg;
876 u8 ant_div_type;
877 u8 regd;
878
879 u8 lna_type_2g;
880 u8 lna_type_5g;
881 u8 glna_type;
882 u8 alna_type;
883 bool ext_lna_2g;
884 bool ext_lna_5g;
885 u8 pa_type_2g;
886 u8 pa_type_5g;
887 u8 gpa_type;
888 u8 apa_type;
889 bool ext_pa_2g;
890 bool ext_pa_5g;
891
892 bool btcoex;
893
894 bool share_ant;
895 u8 bt_setting;
896
897 struct {
898 u8 hci;
899 u8 bw;
900 u8 ptcl;
901 u8 nss;
902 u8 ant_num;
903 } hw_cap;
904
905 struct rtw_txpwr_idx txpwr_idx_table[4];
906};
907
908struct rtw_phy_cond {
909#ifdef __LITTLE_ENDIAN
910 u32 rfe:8;
911 u32 intf:4;
912 u32 pkg:4;
913 u32 plat:4;
914 u32 intf_rsvd:4;
915 u32 cut:4;
916 u32 branch:2;
917 u32 neg:1;
918 u32 pos:1;
919#else
920 u32 pos:1;
921 u32 neg:1;
922 u32 branch:2;
923 u32 cut:4;
924 u32 intf_rsvd:4;
925 u32 plat:4;
926 u32 pkg:4;
927 u32 intf:4;
928 u32 rfe:8;
929#endif
930
931 #define INTF_PCIE BIT(0)
932 #define INTF_USB BIT(1)
933 #define INTF_SDIO BIT(2)
934
935 #define BRANCH_IF 0
936 #define BRANCH_ELIF 1
937 #define BRANCH_ELSE 2
938 #define BRANCH_ENDIF 3
939};
940
941struct rtw_fifo_conf {
942
943 u16 rsvd_boundary;
944 u16 rsvd_pg_num;
945 u16 rsvd_drv_pg_num;
946 u16 txff_pg_num;
947 u16 acq_pg_num;
948 u16 rsvd_drv_addr;
949 u16 rsvd_h2c_info_addr;
950 u16 rsvd_h2c_sta_info_addr;
951 u16 rsvd_h2cq_addr;
952 u16 rsvd_cpu_instr_addr;
953 u16 rsvd_fw_txbuf_addr;
954 u16 rsvd_csibuf_addr;
955 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM];
956};
957
958struct rtw_fw_state {
959 const struct firmware *firmware;
960 struct completion completion;
961 u16 version;
962 u8 sub_version;
963 u8 sub_index;
964 u16 h2c_version;
965};
966
967struct rtw_hal {
968 u32 rcr;
969
970 u32 chip_version;
971 u8 fab_version;
972 u8 cut_version;
973 u8 mp_chip;
974 u8 oem_id;
975 struct rtw_phy_cond phy_cond;
976
977 u8 ps_mode;
978 u8 current_channel;
979 u8 current_band_width;
980 u8 current_band_type;
981 u8 sec_ch_offset;
982 u8 rf_type;
983 u8 rf_path_num;
984 u8 antenna_tx;
985 u8 antenna_rx;
986
987
988 struct mutex tx_power_mutex;
989 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
990 [DESC_RATE_MAX];
991 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
992 [DESC_RATE_MAX];
993 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
994 [RTW_RATE_SECTION_MAX];
995 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
996 [RTW_RATE_SECTION_MAX];
997 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
998 [RTW_CHANNEL_WIDTH_MAX]
999 [RTW_RATE_SECTION_MAX]
1000 [RTW_MAX_CHANNEL_NUM_2G];
1001 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1002 [RTW_CHANNEL_WIDTH_MAX]
1003 [RTW_RATE_SECTION_MAX]
1004 [RTW_MAX_CHANNEL_NUM_5G];
1005 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1006 [DESC_RATE_MAX];
1007};
1008
1009struct rtw_dev {
1010 struct ieee80211_hw *hw;
1011 struct device *dev;
1012
1013 struct rtw_hci hci;
1014
1015 struct rtw_chip_info *chip;
1016 struct rtw_hal hal;
1017 struct rtw_fifo_conf fifo;
1018 struct rtw_fw_state fw;
1019 struct rtw_efuse efuse;
1020 struct rtw_sec_desc sec;
1021 struct rtw_traffic_stats stats;
1022 struct rtw_regulatory regd;
1023
1024 struct rtw_dm_info dm_info;
1025
1026
1027 struct mutex mutex;
1028
1029
1030 spinlock_t dm_lock;
1031
1032
1033 spinlock_t rf_lock;
1034
1035
1036 struct delayed_work watch_dog_work;
1037 u32 watch_dog_cnt;
1038
1039 struct list_head rsvd_page_list;
1040
1041
1042 struct sk_buff_head c2h_queue;
1043 struct work_struct c2h_work;
1044
1045 struct rtw_tx_report tx_report;
1046
1047 struct {
1048
1049 u8 last_box_num;
1050
1051 spinlock_t lock;
1052 u32 seq;
1053 } h2c;
1054
1055
1056 struct rtw_lps_conf lps_conf;
1057 struct delayed_work lps_work;
1058
1059 struct dentry *debugfs;
1060
1061 u8 sta_cnt;
1062
1063 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1064 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1065
1066 u8 mp_mode;
1067
1068
1069 u8 priv[0] __aligned(sizeof(void *));
1070};
1071
1072#include "hci.h"
1073
1074static inline bool rtw_flag_check(struct rtw_dev *rtwdev, enum rtw_flags flag)
1075{
1076 return test_bit(flag, rtwdev->flags);
1077}
1078
1079static inline void rtw_flag_clear(struct rtw_dev *rtwdev, enum rtw_flags flag)
1080{
1081 clear_bit(flag, rtwdev->flags);
1082}
1083
1084static inline void rtw_flag_set(struct rtw_dev *rtwdev, enum rtw_flags flag)
1085{
1086 set_bit(flag, rtwdev->flags);
1087}
1088
1089void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1090 struct rtw_channel_params *ch_param);
1091bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1092bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1093bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1094void rtw_restore_reg(struct rtw_dev *rtwdev,
1095 struct rtw_backup_info *bckp, u32 num);
1096void rtw_set_channel(struct rtw_dev *rtwdev);
1097void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1098 u32 config);
1099void rtw_tx_report_purge_timer(struct timer_list *t);
1100void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1101int rtw_core_start(struct rtw_dev *rtwdev);
1102void rtw_core_stop(struct rtw_dev *rtwdev);
1103int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1104int rtw_core_init(struct rtw_dev *rtwdev);
1105void rtw_core_deinit(struct rtw_dev *rtwdev);
1106int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1107void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1108
1109#endif
1110
