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35#ifndef __CSIO_HW_H__
36#define __CSIO_HW_H__
37
38#include <linux/kernel.h>
39#include <linux/pci.h>
40#include <linux/device.h>
41#include <linux/workqueue.h>
42#include <linux/compiler.h>
43#include <linux/cdev.h>
44#include <linux/list.h>
45#include <linux/mempool.h>
46#include <linux/io.h>
47#include <linux/spinlock_types.h>
48#include <scsi/scsi_device.h>
49#include <scsi/scsi_transport_fc.h>
50
51#include "t4_hw.h"
52#include "csio_hw_chip.h"
53#include "csio_wr.h"
54#include "csio_mb.h"
55#include "csio_scsi.h"
56#include "csio_defs.h"
57#include "t4_regs.h"
58#include "t4_msg.h"
59
60
61
62
63#define FW_HOSTERROR 255
64
65#define CSIO_HW_NAME "Chelsio FCoE Adapter"
66#define CSIO_MAX_PFN 8
67#define CSIO_MAX_PPORTS 4
68
69#define CSIO_MAX_LUN 0xFFFF
70#define CSIO_MAX_QUEUE 2048
71#define CSIO_MAX_CMD_PER_LUN 32
72#define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
73#define CSIO_MAX_SECTOR_SIZE 128
74#define CSIO_MIN_T6_FW 0x01102D00
75
76
77#define CSIO_EXTRA_MSI_IQS 2
78
79#define CSIO_EXTRA_VECS 2
80#define CSIO_MAX_SCSI_CPU 128
81#define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
82#define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
83
84
85enum {
86 CSIO_INTR_WRSIZE = 128,
87 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
88 CSIO_FWEVT_WRSIZE = 128,
89 CSIO_FWEVT_IQLEN = 128,
90 CSIO_FWEVT_FLBUFS = 64,
91 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
92 CSIO_HW_NIQ = 1,
93 CSIO_HW_NFLQ = 1,
94 CSIO_HW_NEQ = 1,
95 CSIO_HW_NINTXQ = 1,
96};
97
98struct csio_msix_entries {
99 unsigned short vector;
100 void *dev_id;
101 char desc[24];
102};
103
104struct csio_scsi_qset {
105 int iq_idx;
106 int eq_idx;
107 uint32_t intr_idx;
108};
109
110struct csio_scsi_cpu_info {
111 int16_t max_cpus;
112};
113
114extern int csio_dbg_level;
115extern unsigned int csio_port_mask;
116extern int csio_msi;
117
118#define CSIO_VENDOR_ID 0x1425
119#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
120#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
121
122#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
123 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
124 PM_TX_F | PM_RX_F | ULP_RX_F | \
125 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
126
127
128
129
130
131enum {
132
133 CSIO_SGE_DBFIFO_INT_THRESH = 10,
134
135 CSIO_SGE_RX_DMA_OFFSET = 2,
136
137 CSIO_SGE_FLBUF_SIZE1 = 65536,
138 CSIO_SGE_FLBUF_SIZE2 = 1536,
139 CSIO_SGE_FLBUF_SIZE3 = 9024,
140 CSIO_SGE_FLBUF_SIZE4 = 9216,
141 CSIO_SGE_FLBUF_SIZE5 = 2048,
142 CSIO_SGE_FLBUF_SIZE6 = 128,
143 CSIO_SGE_FLBUF_SIZE7 = 8192,
144 CSIO_SGE_FLBUF_SIZE8 = 16384,
145
146 CSIO_SGE_TIMER_VAL_0 = 5,
147 CSIO_SGE_TIMER_VAL_1 = 10,
148 CSIO_SGE_TIMER_VAL_2 = 20,
149 CSIO_SGE_TIMER_VAL_3 = 50,
150 CSIO_SGE_TIMER_VAL_4 = 100,
151 CSIO_SGE_TIMER_VAL_5 = 200,
152
153 CSIO_SGE_INT_CNT_VAL_0 = 1,
154 CSIO_SGE_INT_CNT_VAL_1 = 4,
155 CSIO_SGE_INT_CNT_VAL_2 = 8,
156 CSIO_SGE_INT_CNT_VAL_3 = 16,
157};
158
159
160enum csio_evt {
161 CSIO_EVT_FW = 0,
162 CSIO_EVT_MBX,
163 CSIO_EVT_SCN,
164 CSIO_EVT_DEV_LOSS,
165 CSIO_EVT_MAX,
166};
167
168#define CSIO_EVT_MSG_SIZE 512
169#define CSIO_EVTQ_SIZE 512
170
171
172struct csio_evt_msg {
173 struct list_head list;
174 enum csio_evt type;
175 uint8_t data[CSIO_EVT_MSG_SIZE];
176};
177
178enum {
179 SERNUM_LEN = 16,
180 EC_LEN = 16,
181 ID_LEN = 16,
182};
183
184enum {
185 SF_SIZE = SF_SEC_SIZE * 16,
186};
187
188
189enum {
190 SF_ATTEMPTS = 10,
191
192
193 SF_PROG_PAGE = 2,
194 SF_WR_DISABLE = 4,
195 SF_RD_STATUS = 5,
196 SF_WR_ENABLE = 6,
197 SF_RD_DATA_FAST = 0xb,
198 SF_RD_ID = 0x9f,
199 SF_ERASE_SECTOR = 0xd8,
200};
201
202
203enum {
204 CSIO_MGMT_EQ_WRSIZE = 512,
205 CSIO_MGMT_IQ_WRSIZE = 128,
206 CSIO_MGMT_EQLEN = 64,
207 CSIO_MGMT_IQLEN = 64,
208};
209
210#define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
211#define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
212
213
214struct csio_mgmtm_stats {
215 uint32_t n_abort_req;
216 uint32_t n_abort_rsp;
217 uint32_t n_close_req;
218 uint32_t n_close_rsp;
219 uint32_t n_err;
220 uint32_t n_drop;
221 uint32_t n_active;
222 uint32_t n_cbfn;
223};
224
225
226struct csio_mgmtm {
227 struct csio_hw *hw;
228 int eq_idx;
229 int iq_idx;
230 int msi_vec;
231 struct list_head active_q;
232 struct list_head abort_q;
233 struct list_head cbfn_q;
234 struct list_head mgmt_req_freelist;
235
236 struct timer_list mgmt_timer;
237 struct csio_mgmtm_stats stats;
238};
239
240struct csio_adap_desc {
241 char model_no[16];
242 char description[32];
243};
244
245struct pci_params {
246 uint16_t vendor_id;
247 uint16_t device_id;
248 int vpd_cap_addr;
249 uint16_t speed;
250 uint8_t width;
251};
252
253
254struct csio_hw_params {
255 uint32_t sf_size;
256
257
258 uint32_t sf_nsec;
259 struct pci_params pci;
260 uint32_t log_level;
261
262
263};
264
265struct csio_vpd {
266 uint32_t cclk;
267 uint8_t ec[EC_LEN + 1];
268 uint8_t sn[SERNUM_LEN + 1];
269 uint8_t id[ID_LEN + 1];
270};
271
272
273
274typedef u16 fw_port_cap16_t;
275typedef u32 fw_port_cap32_t;
276
277enum fw_caps {
278 FW_CAPS_UNKNOWN = 0,
279 FW_CAPS16 = 1,
280 FW_CAPS32 = 2,
281};
282
283enum cc_pause {
284 PAUSE_RX = 1 << 0,
285 PAUSE_TX = 1 << 1,
286 PAUSE_AUTONEG = 1 << 2
287};
288
289enum cc_fec {
290 FEC_AUTO = 1 << 0,
291 FEC_RS = 1 << 1,
292 FEC_BASER_RS = 1 << 2
293};
294
295struct link_config {
296 fw_port_cap32_t pcaps;
297 fw_port_cap32_t def_acaps;
298 fw_port_cap32_t acaps;
299 fw_port_cap32_t lpacaps;
300
301 fw_port_cap32_t speed_caps;
302 unsigned int speed;
303
304 enum cc_pause requested_fc;
305 enum cc_pause fc;
306
307 enum cc_fec requested_fec;
308 enum cc_fec fec;
309
310 unsigned char autoneg;
311
312 unsigned char link_ok;
313 unsigned char link_down_rc;
314};
315
316#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
317
318#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
319 FW_PORT_CAP32_ANEG)
320
321
322#define AUTONEG_DISABLE 0x00
323#define AUTONEG_ENABLE 0x01
324
325struct csio_pport {
326 uint16_t pcap;
327 uint16_t acap;
328 uint8_t portid;
329 uint8_t link_status;
330 uint16_t link_speed;
331 uint8_t mac[6];
332 uint8_t mod_type;
333 uint8_t rsvd1;
334 uint8_t rsvd2;
335 uint8_t rsvd3;
336 struct link_config link_cfg;
337};
338
339
340struct csio_fcoe_res_info {
341 uint16_t e_d_tov;
342 uint16_t r_a_tov_seq;
343 uint16_t r_a_tov_els;
344 uint16_t r_r_tov;
345 uint32_t max_xchgs;
346 uint32_t max_ssns;
347 uint32_t used_xchgs;
348 uint32_t used_ssns;
349 uint32_t max_fcfs;
350 uint32_t max_vnps;
351 uint32_t used_fcfs;
352 uint32_t used_vnps;
353};
354
355
356enum csio_hw_ev {
357 CSIO_HWE_CFG = (uint32_t)1,
358 CSIO_HWE_INIT,
359 CSIO_HWE_INIT_DONE,
360 CSIO_HWE_FATAL,
361 CSIO_HWE_PCIERR_DETECTED,
362 CSIO_HWE_PCIERR_SLOT_RESET,
363 CSIO_HWE_PCIERR_RESUME,
364 CSIO_HWE_QUIESCED,
365 CSIO_HWE_HBA_RESET,
366 CSIO_HWE_HBA_RESET_DONE,
367 CSIO_HWE_FW_DLOAD,
368 CSIO_HWE_PCI_REMOVE,
369 CSIO_HWE_SUSPEND,
370 CSIO_HWE_RESUME,
371 CSIO_HWE_MAX,
372};
373
374
375struct csio_hw_stats {
376 uint32_t n_evt_activeq;
377 uint32_t n_evt_freeq;
378 uint32_t n_evt_drop;
379 uint32_t n_evt_unexp;
380 uint32_t n_pcich_offline;
381 uint32_t n_lnlkup_miss;
382 uint32_t n_cpl_fw6_msg;
383 uint32_t n_cpl_fw6_pld;
384 uint32_t n_cpl_unexp;
385 uint32_t n_mbint_unexp;
386
387 uint32_t n_plint_unexp;
388
389 uint32_t n_plint_cnt;
390 uint32_t n_int_stray;
391 uint32_t n_err;
392 uint32_t n_err_fatal;
393 uint32_t n_err_nomem;
394 uint32_t n_err_io;
395 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX];
396 uint64_t n_reset_start;
397 uint32_t rsvd1;
398};
399
400
401#define CSIO_HWF_MASTER 0x00000001
402
403
404
405#define CSIO_HWF_HW_INTR_ENABLED 0x00000002
406
407
408#define CSIO_HWF_FWEVT_PENDING 0x00000004
409#define CSIO_HWF_Q_MEM_ALLOCED 0x00000008
410
411
412#define CSIO_HWF_Q_FW_ALLOCED 0x00000010
413
414
415#define CSIO_HWF_VPD_VALID 0x00000020
416#define CSIO_HWF_DEVID_CACHED 0X00000040
417
418#define CSIO_HWF_FWEVT_STOP 0x00000080
419
420
421#define CSIO_HWF_USING_SOFT_PARAMS 0x00000100
422
423
424#define CSIO_HWF_HOST_INTR_ENABLED 0x00000200
425
426
427#define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400
428
429
430
431#define csio_is_hw_intr_enabled(__hw) \
432 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
433#define csio_is_host_intr_enabled(__hw) \
434 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
435#define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
436#define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
437#define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
438#define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
439#define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
440
441
442enum csio_intr_mode {
443 CSIO_IM_NONE = 0,
444 CSIO_IM_INTX = 1,
445 CSIO_IM_MSI = 2,
446 CSIO_IM_MSIX = 3,
447};
448
449
450struct csio_hw {
451 struct csio_sm sm;
452
453
454 spinlock_t lock;
455
456 struct csio_scsim scsim;
457 struct csio_wrm wrm;
458 struct pci_dev *pdev;
459
460 void __iomem *regstart;
461
462
463
464 uint32_t num_sqsets;
465
466 uint32_t num_scsi_msix_cpus;
467
468
469
470
471
472 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
473 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
474
475 uint32_t evtflag;
476 uint32_t flags;
477
478 struct csio_mgmtm mgmtm;
479 struct csio_mbm mbm;
480
481
482 uint32_t num_lns;
483 struct csio_lnode *rln;
484 struct list_head sln_head;
485
486
487 int intr_iq_idx;
488
489
490 int fwevt_iq_idx;
491 struct work_struct evtq_work;
492
493
494 struct list_head evt_free_q;
495
496
497 struct list_head evt_active_q;
498
499
500 char name[32];
501 char hw_ver[16];
502 char model_desc[32];
503 char drv_version[32];
504 char fwrev_str[32];
505 uint32_t optrom_ver;
506 uint32_t fwrev;
507 uint32_t tp_vers;
508 char chip_ver;
509 uint16_t chip_id;
510 enum csio_dev_state fw_state;
511 struct csio_vpd vpd;
512
513 uint8_t pfn;
514
515
516 uint32_t port_vec;
517 uint8_t num_pports;
518
519
520 uint8_t rst_retries;
521 uint8_t cur_evt;
522 uint8_t prev_evt;
523 uint32_t dev_num;
524 struct csio_pport pport[CSIO_MAX_PPORTS];
525 struct csio_hw_params params;
526
527 struct pci_pool *scsi_pci_pool;
528 mempool_t *mb_mempool;
529 mempool_t *rnode_mempool;
530
531
532 enum csio_intr_mode intr_mode;
533 uint32_t fwevt_intr_idx;
534
535
536 uint32_t nondata_intr_idx;
537
538
539
540 uint8_t cfg_neq;
541
542
543 uint8_t cfg_niq;
544
545
546
547 struct csio_fcoe_res_info fres_info;
548 struct csio_hw_chip_ops *chip_ops;
549
550
551
552
553 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
554
555 struct dentry *debugfs_root;
556 struct csio_hw_stats stats;
557};
558
559
560#define csio_reg(_b, _r) ((_b) + (_r))
561
562#define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
563#define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
564#define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
565#define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
566
567#define csio_wr_reg8(_h, _v, _r) writeb((_v), \
568 csio_reg((_h)->regstart, (_r)))
569#define csio_wr_reg16(_h, _v, _r) writew((_v), \
570 csio_reg((_h)->regstart, (_r)))
571#define csio_wr_reg32(_h, _v, _r) writel((_v), \
572 csio_reg((_h)->regstart, (_r)))
573#define csio_wr_reg64(_h, _v, _r) writeq((_v), \
574 csio_reg((_h)->regstart, (_r)))
575
576void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
577
578
579static inline uint32_t
580csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
581{
582
583 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
584}
585
586static inline uint32_t
587csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
588{
589 return (us * hw->vpd.cclk) / 1000;
590}
591
592
593#define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
594#define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
595#define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
596#define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
597
598#define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
599#define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
600#define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
601
602#define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
603#define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
604#define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
605#define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
606
607
608#define CSIO_DEVID(__dev) ((__dev)->dev_num)
609#define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
610#define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
611
612#define csio_info(__hw, __fmt, ...) \
613 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
614
615#define csio_fatal(__hw, __fmt, ...) \
616 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
617
618#define csio_err(__hw, __fmt, ...) \
619 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
620
621#define csio_warn(__hw, __fmt, ...) \
622 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
623
624#ifdef __CSIO_DEBUG__
625#define csio_dbg(__hw, __fmt, ...) \
626 csio_info((__hw), __fmt, ##__VA_ARGS__);
627#else
628#define csio_dbg(__hw, __fmt, ...)
629#endif
630
631int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
632 int, int, uint32_t *);
633void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
634 unsigned int, unsigned int);
635int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
636void csio_hw_intr_disable(struct csio_hw *);
637int csio_hw_slow_intr_handler(struct csio_hw *);
638int csio_handle_intr_status(struct csio_hw *, unsigned int,
639 const struct intr_info *);
640
641fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps);
642fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
643fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32);
644fw_port_cap32_t lstatus_to_fwcap(u32 lstatus);
645
646int csio_hw_start(struct csio_hw *);
647int csio_hw_stop(struct csio_hw *);
648int csio_hw_reset(struct csio_hw *);
649int csio_is_hw_ready(struct csio_hw *);
650int csio_is_hw_removing(struct csio_hw *);
651
652int csio_fwevtq_handler(struct csio_hw *);
653void csio_evtq_worker(struct work_struct *);
654int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
655void csio_evtq_flush(struct csio_hw *hw);
656
657int csio_request_irqs(struct csio_hw *);
658void csio_intr_enable(struct csio_hw *);
659void csio_intr_disable(struct csio_hw *, bool);
660void csio_hw_fatal_err(struct csio_hw *);
661
662struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
663int csio_config_queues(struct csio_hw *);
664
665int csio_hw_init(struct csio_hw *);
666void csio_hw_exit(struct csio_hw *);
667#endif
668