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8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27#include <linux/aer.h>
28#include <linux/bsg-lib.h>
29
30#include <net/tcp.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_host.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_transport.h>
36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_bsg_iscsi.h>
38#include <scsi/scsi_netlink.h>
39#include <scsi/libiscsi.h>
40
41#include "ql4_dbg.h"
42#include "ql4_nx.h"
43#include "ql4_fw.h"
44#include "ql4_nvram.h"
45#include "ql4_83xx.h"
46
47#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49#endif
50
51#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53#endif
54
55#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57#endif
58
59#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61#endif
62
63#ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64#define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65#endif
66
67#ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68#define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
69#endif
70
71#define ISP4XXX_PCI_FN_1 0x1
72#define ISP4XXX_PCI_FN_2 0x3
73
74#define QLA_SUCCESS 0
75#define QLA_ERROR 1
76#define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
77
78
79
80
81#define BIT_0 0x1
82#define BIT_1 0x2
83#define BIT_2 0x4
84#define BIT_3 0x8
85#define BIT_4 0x10
86#define BIT_5 0x20
87#define BIT_6 0x40
88#define BIT_7 0x80
89#define BIT_8 0x100
90#define BIT_9 0x200
91#define BIT_10 0x400
92#define BIT_11 0x800
93#define BIT_12 0x1000
94#define BIT_13 0x2000
95#define BIT_14 0x4000
96#define BIT_15 0x8000
97#define BIT_16 0x10000
98#define BIT_17 0x20000
99#define BIT_18 0x40000
100#define BIT_19 0x80000
101#define BIT_20 0x100000
102#define BIT_21 0x200000
103#define BIT_22 0x400000
104#define BIT_23 0x800000
105#define BIT_24 0x1000000
106#define BIT_25 0x2000000
107#define BIT_26 0x4000000
108#define BIT_27 0x8000000
109#define BIT_28 0x10000000
110#define BIT_29 0x20000000
111#define BIT_30 0x40000000
112#define BIT_31 0x80000000
113
114
115
116
117#define ql4_printk(level, ha, format, arg...) \
118 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
119
120
121
122
123
124#define MAX_HBAS 16
125#define MAX_BUSES 1
126#define MAX_TARGETS MAX_DEV_DB_ENTRIES
127#define MAX_LUNS 0xffff
128#define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
129#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
130#define MAX_PDU_ENTRIES 32
131#define INVALID_ENTRY 0xFFFF
132#define MAX_CMDS_TO_RISC 1024
133#define MAX_SRBS MAX_CMDS_TO_RISC
134#define MBOX_AEN_REG_COUNT 8
135#define MAX_INIT_RETRIES 5
136
137
138
139
140#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
141#define RESPONSE_QUEUE_DEPTH 64
142#define QUEUE_SIZE 64
143#define DMA_BUFFER_SIZE 512
144#define IOCB_HIWAT_CUSHION 4
145
146
147
148
149#define MAC_ADDR_LEN 6
150#define IP_ADDR_LEN 4
151#define IPv6_ADDR_LEN 16
152#define DRIVER_NAME "qla4xxx"
153
154#define MAX_LINKED_CMDS_PER_LUN 3
155#define MAX_REQS_SERVICED_PER_INTR 1
156
157#define ISCSI_IPADDR_SIZE 4
158#define ISCSI_ALIAS_SIZE 32
159#define ISCSI_NAME_SIZE 0xE0
160
161#define QL4_SESS_RECOVERY_TMO 120
162
163
164#define LSDW(x) ((u32)((u64)(x)))
165#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
166
167#define DEV_DB_NON_PERSISTENT 0
168#define DEV_DB_PERSISTENT 1
169
170#define QL4_ISP_REG_DISCONNECT 0xffffffffU
171
172#define COPY_ISID(dst_isid, src_isid) { \
173 int i, j; \
174 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
175 dst_isid[i++] = src_isid[j--]; \
176}
177
178#define SET_BITVAL(o, n, v) { \
179 if (o) \
180 n |= v; \
181 else \
182 n &= ~v; \
183}
184
185#define OP_STATE(o, f, p) { \
186 p = (o & f) ? "enable" : "disable"; \
187}
188
189
190
191
192#define MBOX_TOV 60
193#define SOFT_RESET_TOV 30
194#define RESET_INTR_TOV 3
195#define SEMAPHORE_TOV 10
196#define ADAPTER_INIT_TOV 30
197#define ADAPTER_RESET_TOV 180
198#define EXTEND_CMD_TOV 60
199#define WAIT_CMD_TOV 5
200#define EH_WAIT_CMD_TOV 120
201#define FIRMWARE_UP_TOV 60
202#define RESET_FIRMWARE_TOV 30
203#define LOGOUT_TOV 10
204#define IOCB_TOV_MARGIN 10
205#define RELOGIN_TOV 18
206#define ISNS_DEREG_TOV 5
207#define HBA_ONLINE_TOV 30
208#define DISABLE_ACB_TOV 30
209#define IP_CONFIG_TOV 30
210#define LOGIN_TOV 12
211#define BOOT_LOGIN_RESP_TOV 60
212
213#define MAX_RESET_HA_RETRIES 2
214#define FW_ALIVE_WAIT_TOV 3
215#define IDC_EXTEND_TOV 8
216#define IDC_COMP_TOV 5
217#define LINK_UP_COMP_TOV 30
218
219#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
220
221
222
223
224
225struct srb {
226 struct list_head list;
227 struct scsi_qla_host *ha;
228 struct ddb_entry *ddb;
229 uint16_t flags;
230
231#define SRB_DMA_VALID BIT_3
232#define SRB_GOT_SENSE BIT_4
233 uint8_t state;
234
235#define SRB_NO_QUEUE_STATE 0
236#define SRB_FREE_STATE 1
237#define SRB_ACTIVE_STATE 3
238#define SRB_ACTIVE_TIMEOUT_STATE 4
239#define SRB_SUSPENDED_STATE 7
240
241 struct scsi_cmnd *cmd;
242 dma_addr_t dma_handle;
243 struct kref srb_ref;
244 uint8_t err_id;
245#define SRB_ERR_PORT 1
246#define SRB_ERR_LOOP 2
247#define SRB_ERR_DEVICE 3
248#define SRB_ERR_OTHER 4
249
250 uint16_t reserved;
251 uint16_t iocb_tov;
252 uint16_t iocb_cnt;
253 uint16_t cc_stat;
254
255
256 uint8_t *req_sense_ptr;
257 uint16_t req_sense_len;
258 uint16_t reserved2;
259};
260
261
262struct mrb {
263 struct scsi_qla_host *ha;
264 struct mbox_cmd_iocb *mbox;
265 uint32_t mbox_cmd;
266 uint16_t iocb_cnt;
267 uint32_t pid;
268};
269
270
271
272
273struct aen {
274 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
275};
276
277struct ql4_aen_log {
278 int count;
279 struct aen entry[MAX_AEN_ENTRIES];
280};
281
282
283
284
285struct ddb_entry {
286 struct scsi_qla_host *ha;
287 struct iscsi_cls_session *sess;
288 struct iscsi_cls_conn *conn;
289
290 uint16_t fw_ddb_index;
291 uint32_t fw_ddb_device_state;
292 uint16_t ddb_type;
293#define FLASH_DDB 0x01
294
295 struct dev_db_entry fw_ddb_entry;
296 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
297 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
298 struct ddb_entry *ddb_entry, uint32_t state);
299
300
301 unsigned long flags;
302#define DDB_CONN_CLOSE_FAILURE 0
303
304 uint16_t default_relogin_timeout;
305
306 atomic_t retry_relogin_timer;
307
308 atomic_t relogin_timer;
309
310 atomic_t relogin_retry_count;
311
312 uint32_t default_time2wait;
313
314 uint16_t chap_tbl_idx;
315};
316
317struct qla_ddb_index {
318 struct list_head list;
319 uint16_t fw_ddb_idx;
320 uint16_t flash_ddb_idx;
321 struct dev_db_entry fw_ddb;
322 uint8_t flash_isid[6];
323};
324
325#define DDB_IPADDR_LEN 64
326
327struct ql4_tuple_ddb {
328 int port;
329 int tpgt;
330 char ip_addr[DDB_IPADDR_LEN];
331 char iscsi_name[ISCSI_NAME_SIZE];
332 uint16_t options;
333#define DDB_OPT_IPV6 0x0e0e
334#define DDB_OPT_IPV4 0x0f0f
335 uint8_t isid[6];
336};
337
338
339
340
341#define DDB_STATE_DEAD 0
342
343#define DDB_STATE_ONLINE 1
344
345#define DDB_STATE_MISSING 2
346
347
348
349
350
351#define DF_RELOGIN 0
352#define DF_BOOT_TGT 1
353#define DF_ISNS_DISCOVERED 2
354#define DF_FO_MASKED 3
355#define DF_DISABLE_RELOGIN 4
356
357enum qla4_work_type {
358 QLA4_EVENT_AEN,
359 QLA4_EVENT_PING_STATUS,
360};
361
362struct qla4_work_evt {
363 struct list_head list;
364 enum qla4_work_type type;
365 union {
366 struct {
367 enum iscsi_host_event_code code;
368 uint32_t data_size;
369 uint8_t data[0];
370 } aen;
371 struct {
372 uint32_t status;
373 uint32_t pid;
374 uint32_t data_size;
375 uint8_t data[0];
376 } ping;
377 } u;
378};
379
380struct ql82xx_hw_data {
381
382 uint32_t flash_conf_off;
383 uint32_t flash_data_off;
384
385 uint32_t fdt_wrt_disable;
386 uint32_t fdt_erase_cmd;
387 uint32_t fdt_block_size;
388 uint32_t fdt_unprotect_sec_cmd;
389 uint32_t fdt_protect_sec_cmd;
390
391 uint32_t flt_region_flt;
392 uint32_t flt_region_fdt;
393 uint32_t flt_region_boot;
394 uint32_t flt_region_bootload;
395 uint32_t flt_region_fw;
396
397 uint32_t flt_iscsi_param;
398 uint32_t flt_region_chap;
399 uint32_t flt_chap_size;
400 uint32_t flt_region_ddb;
401 uint32_t flt_ddb_size;
402};
403
404struct qla4_8xxx_legacy_intr_set {
405 uint32_t int_vec_bit;
406 uint32_t tgt_status_reg;
407 uint32_t tgt_mask_reg;
408 uint32_t pci_int_reg;
409};
410
411
412
413#define QLA_MSIX_DEFAULT 0x00
414#define QLA_MSIX_RSP_Q 0x01
415
416#define QLA_MSIX_ENTRIES 2
417#define QLA_MIDX_DEFAULT 0
418#define QLA_MIDX_RSP_Q 1
419
420struct ql4_msix_entry {
421 int have_irq;
422 uint16_t msix_vector;
423 uint16_t msix_entry;
424};
425
426
427
428
429struct isp_operations {
430 int (*iospace_config) (struct scsi_qla_host *ha);
431 void (*pci_config) (struct scsi_qla_host *);
432 void (*disable_intrs) (struct scsi_qla_host *);
433 void (*enable_intrs) (struct scsi_qla_host *);
434 int (*start_firmware) (struct scsi_qla_host *);
435 int (*restart_firmware) (struct scsi_qla_host *);
436 irqreturn_t (*intr_handler) (int , void *);
437 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
438 int (*need_reset) (struct scsi_qla_host *);
439 int (*reset_chip) (struct scsi_qla_host *);
440 int (*reset_firmware) (struct scsi_qla_host *);
441 void (*queue_iocb) (struct scsi_qla_host *);
442 void (*complete_iocb) (struct scsi_qla_host *);
443 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
444 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
445 int (*get_sys_info) (struct scsi_qla_host *);
446 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
447 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
448 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
449 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
450 int (*idc_lock) (struct scsi_qla_host *);
451 void (*idc_unlock) (struct scsi_qla_host *);
452 void (*rom_lock_recovery) (struct scsi_qla_host *);
453 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
454 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
455};
456
457struct ql4_mdump_size_table {
458 uint32_t size;
459 uint32_t size_cmask_02;
460 uint32_t size_cmask_04;
461 uint32_t size_cmask_08;
462 uint32_t size_cmask_10;
463 uint32_t size_cmask_FF;
464 uint32_t version;
465};
466
467
468struct ipaddress_config {
469 uint16_t ipv4_options;
470 uint16_t tcp_options;
471 uint16_t ipv4_vlan_tag;
472 uint8_t ipv4_addr_state;
473 uint8_t ip_address[IP_ADDR_LEN];
474 uint8_t subnet_mask[IP_ADDR_LEN];
475 uint8_t gateway[IP_ADDR_LEN];
476 uint32_t ipv6_options;
477 uint32_t ipv6_addl_options;
478 uint8_t ipv6_link_local_state;
479 uint8_t ipv6_addr0_state;
480 uint8_t ipv6_addr1_state;
481 uint8_t ipv6_default_router_state;
482 uint16_t ipv6_vlan_tag;
483 struct in6_addr ipv6_link_local_addr;
484 struct in6_addr ipv6_addr0;
485 struct in6_addr ipv6_addr1;
486 struct in6_addr ipv6_default_router_addr;
487 uint16_t eth_mtu_size;
488 uint16_t ipv4_port;
489 uint16_t ipv6_port;
490 uint8_t control;
491 uint16_t ipv6_tcp_options;
492 uint8_t tcp_wsf;
493 uint8_t ipv6_tcp_wsf;
494 uint8_t ipv4_tos;
495 uint8_t ipv4_cache_id;
496 uint8_t ipv6_cache_id;
497 uint8_t ipv4_alt_cid_len;
498 uint8_t ipv4_alt_cid[11];
499 uint8_t ipv4_vid_len;
500 uint8_t ipv4_vid[11];
501 uint8_t ipv4_ttl;
502 uint16_t ipv6_flow_lbl;
503 uint8_t ipv6_traffic_class;
504 uint8_t ipv6_hop_limit;
505 uint32_t ipv6_nd_reach_time;
506 uint32_t ipv6_nd_rexmit_timer;
507 uint32_t ipv6_nd_stale_timeout;
508 uint8_t ipv6_dup_addr_detect_count;
509 uint32_t ipv6_gw_advrt_mtu;
510 uint16_t def_timeout;
511 uint8_t abort_timer;
512 uint16_t iscsi_options;
513 uint16_t iscsi_max_pdu_size;
514 uint16_t iscsi_first_burst_len;
515 uint16_t iscsi_max_outstnd_r2t;
516 uint16_t iscsi_max_burst_len;
517 uint8_t iscsi_name[224];
518};
519
520#define QL4_CHAP_MAX_NAME_LEN 256
521#define QL4_CHAP_MAX_SECRET_LEN 100
522#define LOCAL_CHAP 0
523#define BIDI_CHAP 1
524
525struct ql4_chap_format {
526 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
527 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
528 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
529 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
530 u16 intr_chap_name_length;
531 u16 intr_secret_length;
532 u16 target_chap_name_length;
533 u16 target_secret_length;
534};
535
536struct ip_address_format {
537 u8 ip_type;
538 u8 ip_address[16];
539};
540
541struct ql4_conn_info {
542 u16 dest_port;
543 struct ip_address_format dest_ipaddr;
544 struct ql4_chap_format chap;
545};
546
547struct ql4_boot_session_info {
548 u8 target_name[224];
549 struct ql4_conn_info conn_list[1];
550};
551
552struct ql4_boot_tgt_info {
553 struct ql4_boot_session_info boot_pri_sess;
554 struct ql4_boot_session_info boot_sec_sess;
555};
556
557
558
559
560struct scsi_qla_host {
561
562 unsigned long flags;
563
564#define AF_ONLINE 0
565#define AF_INIT_DONE 1
566#define AF_MBOX_COMMAND 2
567#define AF_MBOX_COMMAND_DONE 3
568#define AF_ST_DISCOVERY_IN_PROGRESS 4
569#define AF_INTERRUPTS_ON 6
570#define AF_GET_CRASH_RECORD 7
571#define AF_LINK_UP 8
572#define AF_LOOPBACK 9
573#define AF_IRQ_ATTACHED 10
574#define AF_DISABLE_ACB_COMPLETE 11
575#define AF_HA_REMOVAL 12
576#define AF_INTx_ENABLED 15
577#define AF_MSI_ENABLED 16
578#define AF_MSIX_ENABLED 17
579#define AF_MBOX_COMMAND_NOPOLL 18
580#define AF_FW_RECOVERY 19
581#define AF_EEH_BUSY 20
582#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21
583#define AF_BUILD_DDB_LIST 22
584#define AF_82XX_FW_DUMPED 24
585#define AF_8XXX_RST_OWNER 25
586#define AF_82XX_DUMP_READING 26
587#define AF_83XX_IOCB_INTR_ON 28
588#define AF_83XX_MBOX_INTR_ON 29
589
590 unsigned long dpc_flags;
591
592#define DPC_RESET_HA 1
593#define DPC_RETRY_RESET_HA 2
594#define DPC_RELOGIN_DEVICE 3
595#define DPC_RESET_HA_FW_CONTEXT 4
596#define DPC_RESET_HA_INTR 5
597#define DPC_ISNS_RESTART 7
598#define DPC_AEN 9
599#define DPC_GET_DHCP_IP_ADDR 15
600#define DPC_LINK_CHANGED 18
601#define DPC_RESET_ACTIVE 20
602#define DPC_HA_UNRECOVERABLE 21
603#define DPC_HA_NEED_QUIESCENT 22
604#define DPC_POST_IDC_ACK 23
605#define DPC_RESTORE_ACB 24
606#define DPC_SYSFS_DDB_EXPORT 25
607
608 struct Scsi_Host *host;
609 uint32_t tot_ddbs;
610
611 uint16_t iocb_cnt;
612 uint16_t iocb_hiwat;
613
614
615#define SRB_MIN_REQ 128
616 mempool_t *srb_mempool;
617
618
619 struct pci_dev *pdev;
620
621 struct isp_reg __iomem *reg;
622 unsigned long pio_address;
623 unsigned long pio_length;
624#define MIN_IOBASE_LEN 0x100
625
626 uint16_t req_q_count;
627
628 unsigned long host_no;
629
630
631 struct eeprom_data *nvram;
632 spinlock_t hardware_lock ____cacheline_aligned;
633 uint32_t eeprom_cmd_data;
634
635
636 uint64_t isr_count;
637 uint64_t adapter_error_count;
638 uint64_t device_error_count;
639 uint64_t total_io_count;
640 uint64_t total_mbytes_xferred;
641 uint64_t link_failure_count;
642 uint64_t invalid_crc_count;
643 uint32_t bytes_xfered;
644 uint32_t spurious_int_count;
645 uint32_t aborted_io_count;
646 uint32_t io_timeout_count;
647 uint32_t mailbox_timeout_count;
648 uint32_t seconds_since_last_intr;
649 uint32_t seconds_since_last_heartbeat;
650 uint32_t mac_index;
651
652
653
654 uint32_t firmware_version[2];
655 uint32_t patch_number;
656 uint32_t build_number;
657 uint32_t board_id;
658
659
660
661 uint16_t firmware_options;
662 uint8_t alias[32];
663 uint8_t name_string[256];
664 uint8_t heartbeat_interval;
665
666
667 uint8_t my_mac[MAC_ADDR_LEN];
668 uint8_t serial_number[16];
669 uint16_t port_num;
670
671 uint32_t firmware_state;
672 uint32_t addl_fw_state;
673
674
675 struct workqueue_struct *dpc_thread;
676 struct work_struct dpc_work;
677
678
679 struct timer_list timer;
680 uint32_t timer_active;
681
682
683 atomic_t check_relogin_timeouts;
684 uint32_t retry_reset_ha_cnt;
685 uint32_t isp_reset_timer;
686 uint32_t nic_reset_timer;
687 int eh_start;
688 struct list_head free_srb_q;
689 uint16_t free_srb_q_count;
690 uint16_t num_srbs_allocated;
691
692
693 void *queues;
694 dma_addr_t queues_dma;
695 unsigned long queues_len;
696
697#define MEM_ALIGN_VALUE \
698 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
699 sizeof(struct queue_entry))
700
701 dma_addr_t request_dma;
702 struct queue_entry *request_ring;
703 struct queue_entry *request_ptr;
704 dma_addr_t response_dma;
705 struct queue_entry *response_ring;
706 struct queue_entry *response_ptr;
707 dma_addr_t shadow_regs_dma;
708 struct shadow_regs *shadow_regs;
709 uint16_t request_in;
710 uint16_t request_out;
711 uint16_t response_in;
712 uint16_t response_out;
713
714
715 uint16_t aen_q_count;
716 uint16_t aen_in;
717 uint16_t aen_out;
718 struct aen aen_q[MAX_AEN_ENTRIES];
719
720 struct ql4_aen_log aen_log;
721
722
723
724
725 struct mutex mbox_sem;
726
727
728 volatile uint8_t mbox_status_count;
729 volatile uint32_t mbox_status[MBOX_REG_COUNT];
730
731
732 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
733
734
735 struct srb *status_srb;
736
737 uint8_t acb_version;
738
739
740 struct device_reg_82xx __iomem *qla4_82xx_reg;
741 unsigned long nx_pcibase;
742 uint8_t *nx_db_rd_ptr;
743 unsigned long nx_db_wr_ptr;
744 unsigned long first_page_group_start;
745 unsigned long first_page_group_end;
746
747 uint32_t crb_win;
748 uint32_t curr_window;
749 uint32_t ddr_mn_window;
750 unsigned long mn_win_crb;
751 unsigned long ms_win_crb;
752 int qdr_sn_window;
753 rwlock_t hw_lock;
754 uint16_t func_num;
755 int link_width;
756
757 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
758 u32 nx_crb_mask;
759
760 uint8_t revision_id;
761 uint32_t fw_heartbeat_counter;
762
763 struct isp_operations *isp_ops;
764 struct ql82xx_hw_data hw;
765
766 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
767
768 uint32_t nx_dev_init_timeout;
769 uint32_t nx_reset_timeout;
770 void *fw_dump;
771 uint32_t fw_dump_size;
772 uint32_t fw_dump_capture_mask;
773 void *fw_dump_tmplt_hdr;
774 uint32_t fw_dump_tmplt_size;
775 uint32_t fw_dump_skip_size;
776
777 struct completion mbx_intr_comp;
778
779 struct ipaddress_config ip_config;
780 struct iscsi_iface *iface_ipv4;
781 struct iscsi_iface *iface_ipv6_0;
782 struct iscsi_iface *iface_ipv6_1;
783
784
785 struct about_fw_info fw_info;
786 uint32_t fw_uptime_secs;
787 uint32_t fw_uptime_msecs;
788 uint16_t def_timeout;
789
790 uint32_t flash_state;
791#define QLFLASH_WAITING 0
792#define QLFLASH_READING 1
793#define QLFLASH_WRITING 2
794 struct dma_pool *chap_dma_pool;
795 uint8_t *chap_list;
796 struct mutex chap_sem;
797
798#define CHAP_DMA_BLOCK_SIZE 512
799 struct workqueue_struct *task_wq;
800 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
801#define SYSFS_FLAG_FW_SEL_BOOT 2
802 struct iscsi_boot_kset *boot_kset;
803 struct ql4_boot_tgt_info boot_tgt;
804 uint16_t phy_port_num;
805 uint16_t phy_port_cnt;
806 uint16_t iscsi_pci_func_cnt;
807 uint8_t model_name[16];
808 struct completion disable_acb_comp;
809 struct dma_pool *fw_ddb_dma_pool;
810#define DDB_DMA_BLOCK_SIZE 512
811 uint16_t pri_ddb_idx;
812 uint16_t sec_ddb_idx;
813 int is_reset;
814 uint16_t temperature;
815
816
817 struct list_head work_list;
818 spinlock_t work_lock;
819
820
821#define MAX_MRB 128
822 struct mrb *active_mrb_array[MAX_MRB];
823 uint32_t mrb_index;
824
825 uint32_t *reg_tbl;
826 struct qla4_83xx_reset_template reset_tmplt;
827 struct device_reg_83xx __iomem *qla4_83xx_reg;
828
829
830 uint32_t pf_bit;
831 struct qla4_83xx_idc_information idc_info;
832 struct addr_ctrl_blk *saved_acb;
833 int notify_idc_comp;
834 int notify_link_up_comp;
835 int idc_extend_tmo;
836 struct completion idc_comp;
837 struct completion link_up_comp;
838};
839
840struct ql4_task_data {
841 struct scsi_qla_host *ha;
842 uint8_t iocb_req_cnt;
843 dma_addr_t data_dma;
844 void *req_buffer;
845 dma_addr_t req_dma;
846 uint32_t req_len;
847 void *resp_buffer;
848 dma_addr_t resp_dma;
849 uint32_t resp_len;
850 struct iscsi_task *task;
851 struct passthru_status sts;
852 struct work_struct task_work;
853};
854
855struct qla_endpoint {
856 struct Scsi_Host *host;
857 struct sockaddr_storage dst_addr;
858};
859
860struct qla_conn {
861 struct qla_endpoint *qla_ep;
862};
863
864static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
865{
866 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
867}
868
869static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
870{
871 return ((ha->ip_config.ipv6_options &
872 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
873}
874
875static inline int is_qla4010(struct scsi_qla_host *ha)
876{
877 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
878}
879
880static inline int is_qla4022(struct scsi_qla_host *ha)
881{
882 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
883}
884
885static inline int is_qla4032(struct scsi_qla_host *ha)
886{
887 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
888}
889
890static inline int is_qla40XX(struct scsi_qla_host *ha)
891{
892 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
893}
894
895static inline int is_qla8022(struct scsi_qla_host *ha)
896{
897 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
898}
899
900static inline int is_qla8032(struct scsi_qla_host *ha)
901{
902 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
903}
904
905static inline int is_qla8042(struct scsi_qla_host *ha)
906{
907 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
908}
909
910static inline int is_qla80XX(struct scsi_qla_host *ha)
911{
912 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
913}
914
915static inline int is_aer_supported(struct scsi_qla_host *ha)
916{
917 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
918 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) ||
919 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042));
920}
921
922static inline int adapter_up(struct scsi_qla_host *ha)
923{
924 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
925 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
926 (!test_bit(AF_LOOPBACK, &ha->flags));
927}
928
929static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
930{
931 return (struct scsi_qla_host *)iscsi_host_priv(shost);
932}
933
934static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
935{
936 return (is_qla4010(ha) ?
937 &ha->reg->u1.isp4010.nvram :
938 &ha->reg->u1.isp4022.semaphore);
939}
940
941static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
942{
943 return (is_qla4010(ha) ?
944 &ha->reg->u1.isp4010.nvram :
945 &ha->reg->u1.isp4022.nvram);
946}
947
948static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
949{
950 return (is_qla4010(ha) ?
951 &ha->reg->u2.isp4010.ext_hw_conf :
952 &ha->reg->u2.isp4022.p0.ext_hw_conf);
953}
954
955static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
956{
957 return (is_qla4010(ha) ?
958 &ha->reg->u2.isp4010.port_status :
959 &ha->reg->u2.isp4022.p0.port_status);
960}
961
962static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
963{
964 return (is_qla4010(ha) ?
965 &ha->reg->u2.isp4010.port_ctrl :
966 &ha->reg->u2.isp4022.p0.port_ctrl);
967}
968
969static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
970{
971 return (is_qla4010(ha) ?
972 &ha->reg->u2.isp4010.port_err_status :
973 &ha->reg->u2.isp4022.p0.port_err_status);
974}
975
976static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
977{
978 return (is_qla4010(ha) ?
979 &ha->reg->u2.isp4010.gp_out :
980 &ha->reg->u2.isp4022.p0.gp_out);
981}
982
983static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
984{
985 return (is_qla4010(ha) ?
986 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
987 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
988}
989
990int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
991void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
992int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
993
994static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
995{
996 if (is_qla4010(a))
997 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
998 QL4010_FLASH_SEM_BITS);
999 else
1000 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
1001 (QL4022_RESOURCE_BITS_BASE_CODE |
1002 (a->mac_index)) << 13);
1003}
1004
1005static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
1006{
1007 if (is_qla4010(a))
1008 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
1009 else
1010 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
1011}
1012
1013static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
1014{
1015 if (is_qla4010(a))
1016 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
1017 QL4010_NVRAM_SEM_BITS);
1018 else
1019 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
1020 (QL4022_RESOURCE_BITS_BASE_CODE |
1021 (a->mac_index)) << 10);
1022}
1023
1024static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
1025{
1026 if (is_qla4010(a))
1027 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
1028 else
1029 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
1030}
1031
1032static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
1033{
1034 if (is_qla4010(a))
1035 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
1036 QL4010_DRVR_SEM_BITS);
1037 else
1038 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
1039 (QL4022_RESOURCE_BITS_BASE_CODE |
1040 (a->mac_index)) << 1);
1041}
1042
1043static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
1044{
1045 if (is_qla4010(a))
1046 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1047 else
1048 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1049}
1050
1051static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1052{
1053 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1054 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1055 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1056 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1057 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1058 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1059
1060}
1061
1062static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1063 const uint32_t crb_reg)
1064{
1065 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1066}
1067
1068static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1069 const uint32_t crb_reg,
1070 const uint32_t value)
1071{
1072 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1073}
1074
1075
1076
1077
1078
1079#define INIT_ADAPTER 0
1080#define RESET_ADAPTER 1
1081
1082#define PRESERVE_DDB_LIST 0
1083#define REBUILD_DDB_LIST 1
1084
1085
1086#define PROCESS_ALL_AENS 0
1087#define FLUSH_DDB_CHANGED_AENS 1
1088
1089
1090#define QL4_UEVENT_CODE_FW_DUMP 0
1091
1092#endif
1093
