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18#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/device.h>
23#include <linux/module.h>
24#include <linux/ioport.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/platform_device.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <mach/hardware.h>
37#include <mach/netx-regs.h>
38
39
40#define SERIAL_NX_MAJOR 204
41#define MINOR_START 170
42
43enum uart_regs {
44 UART_DR = 0x00,
45 UART_SR = 0x04,
46 UART_LINE_CR = 0x08,
47 UART_BAUDDIV_MSB = 0x0c,
48 UART_BAUDDIV_LSB = 0x10,
49 UART_CR = 0x14,
50 UART_FR = 0x18,
51 UART_IIR = 0x1c,
52 UART_ILPR = 0x20,
53 UART_RTS_CR = 0x24,
54 UART_RTS_LEAD = 0x28,
55 UART_RTS_TRAIL = 0x2c,
56 UART_DRV_ENABLE = 0x30,
57 UART_BRM_CR = 0x34,
58 UART_RXFIFO_IRQLEVEL = 0x38,
59 UART_TXFIFO_IRQLEVEL = 0x3c,
60};
61
62#define SR_FE (1<<0)
63#define SR_PE (1<<1)
64#define SR_BE (1<<2)
65#define SR_OE (1<<3)
66
67#define LINE_CR_BRK (1<<0)
68#define LINE_CR_PEN (1<<1)
69#define LINE_CR_EPS (1<<2)
70#define LINE_CR_STP2 (1<<3)
71#define LINE_CR_FEN (1<<4)
72#define LINE_CR_5BIT (0<<5)
73#define LINE_CR_6BIT (1<<5)
74#define LINE_CR_7BIT (2<<5)
75#define LINE_CR_8BIT (3<<5)
76#define LINE_CR_BITS_MASK (3<<5)
77
78#define CR_UART_EN (1<<0)
79#define CR_SIREN (1<<1)
80#define CR_SIRLP (1<<2)
81#define CR_MSIE (1<<3)
82#define CR_RIE (1<<4)
83#define CR_TIE (1<<5)
84#define CR_RTIE (1<<6)
85#define CR_LBE (1<<7)
86
87#define FR_CTS (1<<0)
88#define FR_DSR (1<<1)
89#define FR_DCD (1<<2)
90#define FR_BUSY (1<<3)
91#define FR_RXFE (1<<4)
92#define FR_TXFF (1<<5)
93#define FR_RXFF (1<<6)
94#define FR_TXFE (1<<7)
95
96#define IIR_MIS (1<<0)
97#define IIR_RIS (1<<1)
98#define IIR_TIS (1<<2)
99#define IIR_RTIS (1<<3)
100#define IIR_MASK 0xf
101
102#define RTS_CR_AUTO (1<<0)
103#define RTS_CR_RTS (1<<1)
104#define RTS_CR_COUNT (1<<2)
105#define RTS_CR_MOD2 (1<<3)
106#define RTS_CR_RTS_POL (1<<4)
107#define RTS_CR_CTS_CTR (1<<5)
108#define RTS_CR_CTS_POL (1<<6)
109#define RTS_CR_STICK (1<<7)
110
111#define UART_PORT_SIZE 0x40
112#define DRIVER_NAME "netx-uart"
113
114struct netx_port {
115 struct uart_port port;
116};
117
118static void netx_stop_tx(struct uart_port *port)
119{
120 unsigned int val;
121 val = readl(port->membase + UART_CR);
122 writel(val & ~CR_TIE, port->membase + UART_CR);
123}
124
125static void netx_stop_rx(struct uart_port *port)
126{
127 unsigned int val;
128 val = readl(port->membase + UART_CR);
129 writel(val & ~CR_RIE, port->membase + UART_CR);
130}
131
132static void netx_enable_ms(struct uart_port *port)
133{
134 unsigned int val;
135 val = readl(port->membase + UART_CR);
136 writel(val | CR_MSIE, port->membase + UART_CR);
137}
138
139static inline void netx_transmit_buffer(struct uart_port *port)
140{
141 struct circ_buf *xmit = &port->state->xmit;
142
143 if (port->x_char) {
144 writel(port->x_char, port->membase + UART_DR);
145 port->icount.tx++;
146 port->x_char = 0;
147 return;
148 }
149
150 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
151 netx_stop_tx(port);
152 return;
153 }
154
155 do {
156
157
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
159 xmit->tail = (xmit->tail + 1) &
160 (UART_XMIT_SIZE - 1);
161 port->icount.tx++;
162 if (uart_circ_empty(xmit))
163 break;
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
165
166 if (uart_circ_empty(xmit))
167 netx_stop_tx(port);
168}
169
170static void netx_start_tx(struct uart_port *port)
171{
172 writel(
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
174
175 if (!(readl(port->membase + UART_FR) & FR_TXFF))
176 netx_transmit_buffer(port);
177}
178
179static unsigned int netx_tx_empty(struct uart_port *port)
180{
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
182}
183
184static void netx_txint(struct uart_port *port)
185{
186 struct circ_buf *xmit = &port->state->xmit;
187
188 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
189 netx_stop_tx(port);
190 return;
191 }
192
193 netx_transmit_buffer(port);
194
195 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
196 uart_write_wakeup(port);
197}
198
199static void netx_rxint(struct uart_port *port)
200{
201 unsigned char rx, flg, status;
202
203 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
204 rx = readl(port->membase + UART_DR);
205 flg = TTY_NORMAL;
206 port->icount.rx++;
207 status = readl(port->membase + UART_SR);
208 if (status & SR_BE) {
209 writel(0, port->membase + UART_SR);
210 if (uart_handle_break(port))
211 continue;
212 }
213
214 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
215
216 if (status & SR_PE)
217 port->icount.parity++;
218 else if (status & SR_FE)
219 port->icount.frame++;
220 if (status & SR_OE)
221 port->icount.overrun++;
222
223 status &= port->read_status_mask;
224
225 if (status & SR_BE)
226 flg = TTY_BREAK;
227 else if (status & SR_PE)
228 flg = TTY_PARITY;
229 else if (status & SR_FE)
230 flg = TTY_FRAME;
231 }
232
233 if (uart_handle_sysrq_char(port, rx))
234 continue;
235
236 uart_insert_char(port, status, SR_OE, rx, flg);
237 }
238
239 tty_flip_buffer_push(&port->state->port);
240}
241
242static irqreturn_t netx_int(int irq, void *dev_id)
243{
244 struct uart_port *port = dev_id;
245 unsigned long flags;
246 unsigned char status;
247
248 spin_lock_irqsave(&port->lock,flags);
249
250 status = readl(port->membase + UART_IIR) & IIR_MASK;
251 while (status) {
252 if (status & IIR_RIS)
253 netx_rxint(port);
254 if (status & IIR_TIS)
255 netx_txint(port);
256 if (status & IIR_MIS) {
257 if (readl(port->membase + UART_FR) & FR_CTS)
258 uart_handle_cts_change(port, 1);
259 else
260 uart_handle_cts_change(port, 0);
261 }
262 writel(0, port->membase + UART_IIR);
263 status = readl(port->membase + UART_IIR) & IIR_MASK;
264 }
265
266 spin_unlock_irqrestore(&port->lock,flags);
267 return IRQ_HANDLED;
268}
269
270static unsigned int netx_get_mctrl(struct uart_port *port)
271{
272 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
273
274 if (readl(port->membase + UART_FR) & FR_CTS)
275 ret |= TIOCM_CTS;
276
277 return ret;
278}
279
280static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
281{
282 unsigned int val;
283
284
285 if (mctrl & TIOCM_RTS) {
286 val = readl(port->membase + UART_RTS_CR);
287 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
288 }
289}
290
291static void netx_break_ctl(struct uart_port *port, int break_state)
292{
293 unsigned int line_cr;
294 spin_lock_irq(&port->lock);
295
296 line_cr = readl(port->membase + UART_LINE_CR);
297 if (break_state != 0)
298 line_cr |= LINE_CR_BRK;
299 else
300 line_cr &= ~LINE_CR_BRK;
301 writel(line_cr, port->membase + UART_LINE_CR);
302
303 spin_unlock_irq(&port->lock);
304}
305
306static int netx_startup(struct uart_port *port)
307{
308 int ret;
309
310 ret = request_irq(port->irq, netx_int, 0,
311 DRIVER_NAME, port);
312 if (ret) {
313 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
314 goto exit;
315 }
316
317 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
318 port->membase + UART_LINE_CR);
319
320 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
321 port->membase + UART_CR);
322
323exit:
324 return ret;
325}
326
327static void netx_shutdown(struct uart_port *port)
328{
329 writel(0, port->membase + UART_CR) ;
330
331 free_irq(port->irq, port);
332}
333
334static void
335netx_set_termios(struct uart_port *port, struct ktermios *termios,
336 struct ktermios *old)
337{
338 unsigned int baud, quot;
339 unsigned char old_cr;
340 unsigned char line_cr = LINE_CR_FEN;
341 unsigned char rts_cr = 0;
342
343 switch (termios->c_cflag & CSIZE) {
344 case CS5:
345 line_cr |= LINE_CR_5BIT;
346 break;
347 case CS6:
348 line_cr |= LINE_CR_6BIT;
349 break;
350 case CS7:
351 line_cr |= LINE_CR_7BIT;
352 break;
353 case CS8:
354 line_cr |= LINE_CR_8BIT;
355 break;
356 }
357
358 if (termios->c_cflag & CSTOPB)
359 line_cr |= LINE_CR_STP2;
360
361 if (termios->c_cflag & PARENB) {
362 line_cr |= LINE_CR_PEN;
363 if (!(termios->c_cflag & PARODD))
364 line_cr |= LINE_CR_EPS;
365 }
366
367 if (termios->c_cflag & CRTSCTS)
368 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
369
370 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
371 quot = baud * 4096;
372 quot /= 1000;
373 quot *= 256;
374 quot /= 100000;
375
376 spin_lock_irq(&port->lock);
377
378 uart_update_timeout(port, termios->c_cflag, baud);
379
380 old_cr = readl(port->membase + UART_CR);
381
382
383 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
384 port->membase + UART_CR);
385
386
387 while (readl(port->membase + UART_FR) & FR_BUSY);
388
389
390 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
391
392
393 old_cr &= ~CR_MSIE;
394 if (UART_ENABLE_MS(port, termios->c_cflag))
395 old_cr |= CR_MSIE;
396
397 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
398 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
399 writel(line_cr, port->membase + UART_LINE_CR);
400
401 writel(rts_cr, port->membase + UART_RTS_CR);
402
403
404
405
406 port->ignore_status_mask = 0;
407 if (termios->c_iflag & IGNPAR)
408 port->ignore_status_mask |= SR_PE;
409 if (termios->c_iflag & IGNBRK) {
410 port->ignore_status_mask |= SR_BE;
411
412
413
414
415 if (termios->c_iflag & IGNPAR)
416 port->ignore_status_mask |= SR_PE;
417 }
418
419 port->read_status_mask = 0;
420 if (termios->c_iflag & (BRKINT | PARMRK))
421 port->read_status_mask |= SR_BE;
422 if (termios->c_iflag & INPCK)
423 port->read_status_mask |= SR_PE | SR_FE;
424
425 writel(old_cr, port->membase + UART_CR);
426
427 spin_unlock_irq(&port->lock);
428}
429
430static const char *netx_type(struct uart_port *port)
431{
432 return port->type == PORT_NETX ? "NETX" : NULL;
433}
434
435static void netx_release_port(struct uart_port *port)
436{
437 release_mem_region(port->mapbase, UART_PORT_SIZE);
438}
439
440static int netx_request_port(struct uart_port *port)
441{
442 return request_mem_region(port->mapbase, UART_PORT_SIZE,
443 DRIVER_NAME) != NULL ? 0 : -EBUSY;
444}
445
446static void netx_config_port(struct uart_port *port, int flags)
447{
448 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
449 port->type = PORT_NETX;
450}
451
452static int
453netx_verify_port(struct uart_port *port, struct serial_struct *ser)
454{
455 int ret = 0;
456
457 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
458 ret = -EINVAL;
459
460 return ret;
461}
462
463static struct uart_ops netx_pops = {
464 .tx_empty = netx_tx_empty,
465 .set_mctrl = netx_set_mctrl,
466 .get_mctrl = netx_get_mctrl,
467 .stop_tx = netx_stop_tx,
468 .start_tx = netx_start_tx,
469 .stop_rx = netx_stop_rx,
470 .enable_ms = netx_enable_ms,
471 .break_ctl = netx_break_ctl,
472 .startup = netx_startup,
473 .shutdown = netx_shutdown,
474 .set_termios = netx_set_termios,
475 .type = netx_type,
476 .release_port = netx_release_port,
477 .request_port = netx_request_port,
478 .config_port = netx_config_port,
479 .verify_port = netx_verify_port,
480};
481
482static struct netx_port netx_ports[] = {
483 {
484 .port = {
485 .type = PORT_NETX,
486 .iotype = UPIO_MEM,
487 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
488 .mapbase = NETX_PA_UART0,
489 .irq = NETX_IRQ_UART0,
490 .uartclk = 100000000,
491 .fifosize = 16,
492 .flags = UPF_BOOT_AUTOCONF,
493 .ops = &netx_pops,
494 .line = 0,
495 },
496 }, {
497 .port = {
498 .type = PORT_NETX,
499 .iotype = UPIO_MEM,
500 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
501 .mapbase = NETX_PA_UART1,
502 .irq = NETX_IRQ_UART1,
503 .uartclk = 100000000,
504 .fifosize = 16,
505 .flags = UPF_BOOT_AUTOCONF,
506 .ops = &netx_pops,
507 .line = 1,
508 },
509 }, {
510 .port = {
511 .type = PORT_NETX,
512 .iotype = UPIO_MEM,
513 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
514 .mapbase = NETX_PA_UART2,
515 .irq = NETX_IRQ_UART2,
516 .uartclk = 100000000,
517 .fifosize = 16,
518 .flags = UPF_BOOT_AUTOCONF,
519 .ops = &netx_pops,
520 .line = 2,
521 },
522 }
523};
524
525#ifdef CONFIG_SERIAL_NETX_CONSOLE
526
527static void netx_console_putchar(struct uart_port *port, int ch)
528{
529 while (readl(port->membase + UART_FR) & FR_BUSY);
530 writel(ch, port->membase + UART_DR);
531}
532
533static void
534netx_console_write(struct console *co, const char *s, unsigned int count)
535{
536 struct uart_port *port = &netx_ports[co->index].port;
537 unsigned char cr_save;
538
539 cr_save = readl(port->membase + UART_CR);
540 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
541
542 uart_console_write(port, s, count, netx_console_putchar);
543
544 while (readl(port->membase + UART_FR) & FR_BUSY);
545 writel(cr_save, port->membase + UART_CR);
546}
547
548static void __init
549netx_console_get_options(struct uart_port *port, int *baud,
550 int *parity, int *bits, int *flow)
551{
552 unsigned char line_cr;
553
554 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
555 readl(port->membase + UART_BAUDDIV_LSB);
556 *baud *= 1000;
557 *baud /= 4096;
558 *baud *= 1000;
559 *baud /= 256;
560 *baud *= 100;
561
562 line_cr = readl(port->membase + UART_LINE_CR);
563 *parity = 'n';
564 if (line_cr & LINE_CR_PEN) {
565 if (line_cr & LINE_CR_EPS)
566 *parity = 'e';
567 else
568 *parity = 'o';
569 }
570
571 switch (line_cr & LINE_CR_BITS_MASK) {
572 case LINE_CR_8BIT:
573 *bits = 8;
574 break;
575 case LINE_CR_7BIT:
576 *bits = 7;
577 break;
578 case LINE_CR_6BIT:
579 *bits = 6;
580 break;
581 case LINE_CR_5BIT:
582 *bits = 5;
583 break;
584 }
585
586 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
587 *flow = 'r';
588}
589
590static int __init
591netx_console_setup(struct console *co, char *options)
592{
593 struct netx_port *sport;
594 int baud = 9600;
595 int bits = 8;
596 int parity = 'n';
597 int flow = 'n';
598
599
600
601
602
603
604 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
605 co->index = 0;
606 sport = &netx_ports[co->index];
607
608 if (options) {
609 uart_parse_options(options, &baud, &parity, &bits, &flow);
610 } else {
611
612
613
614 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
615 netx_console_get_options(&sport->port, &baud,
616 &parity, &bits, &flow);
617 }
618
619 }
620
621 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
622}
623
624static struct uart_driver netx_reg;
625static struct console netx_console = {
626 .name = "ttyNX",
627 .write = netx_console_write,
628 .device = uart_console_device,
629 .setup = netx_console_setup,
630 .flags = CON_PRINTBUFFER,
631 .index = -1,
632 .data = &netx_reg,
633};
634
635static int __init netx_console_init(void)
636{
637 register_console(&netx_console);
638 return 0;
639}
640console_initcall(netx_console_init);
641
642#define NETX_CONSOLE &netx_console
643#else
644#define NETX_CONSOLE NULL
645#endif
646
647static struct uart_driver netx_reg = {
648 .owner = THIS_MODULE,
649 .driver_name = DRIVER_NAME,
650 .dev_name = "ttyNX",
651 .major = SERIAL_NX_MAJOR,
652 .minor = MINOR_START,
653 .nr = ARRAY_SIZE(netx_ports),
654 .cons = NETX_CONSOLE,
655};
656
657static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
658{
659 struct netx_port *sport = platform_get_drvdata(pdev);
660
661 if (sport)
662 uart_suspend_port(&netx_reg, &sport->port);
663
664 return 0;
665}
666
667static int serial_netx_resume(struct platform_device *pdev)
668{
669 struct netx_port *sport = platform_get_drvdata(pdev);
670
671 if (sport)
672 uart_resume_port(&netx_reg, &sport->port);
673
674 return 0;
675}
676
677static int serial_netx_probe(struct platform_device *pdev)
678{
679 struct uart_port *port = &netx_ports[pdev->id].port;
680
681 dev_info(&pdev->dev, "initialising\n");
682
683 port->dev = &pdev->dev;
684
685 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
686 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
687 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
688
689 return 0;
690}
691
692static int serial_netx_remove(struct platform_device *pdev)
693{
694 struct netx_port *sport = platform_get_drvdata(pdev);
695
696 platform_set_drvdata(pdev, NULL);
697
698 if (sport)
699 uart_remove_one_port(&netx_reg, &sport->port);
700
701 return 0;
702}
703
704static struct platform_driver serial_netx_driver = {
705 .probe = serial_netx_probe,
706 .remove = serial_netx_remove,
707
708 .suspend = serial_netx_suspend,
709 .resume = serial_netx_resume,
710
711 .driver = {
712 .name = DRIVER_NAME,
713 .owner = THIS_MODULE,
714 },
715};
716
717static int __init netx_serial_init(void)
718{
719 int ret;
720
721 printk(KERN_INFO "Serial: NetX driver\n");
722
723 ret = uart_register_driver(&netx_reg);
724 if (ret)
725 return ret;
726
727 ret = platform_driver_register(&serial_netx_driver);
728 if (ret != 0)
729 uart_unregister_driver(&netx_reg);
730
731 return 0;
732}
733
734static void __exit netx_serial_exit(void)
735{
736 platform_driver_unregister(&serial_netx_driver);
737 uart_unregister_driver(&netx_reg);
738}
739
740module_init(netx_serial_init);
741module_exit(netx_serial_exit);
742
743MODULE_AUTHOR("Sascha Hauer");
744MODULE_DESCRIPTION("NetX serial port driver");
745MODULE_LICENSE("GPL");
746MODULE_ALIAS("platform:" DRIVER_NAME);
747
