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45#undef DEBUG
46
47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/errno.h>
50#include <linux/string.h>
51#include <linux/mm.h>
52#include <linux/slab.h>
53#include <linux/delay.h>
54#include <linux/interrupt.h>
55#include <linux/fb.h>
56#include <linux/init.h>
57#include <linux/pci.h>
58
59#ifdef CONFIG_SH_DREAMCAST
60#include <asm/machvec.h>
61#include <mach-dreamcast/mach/sysasic.h>
62#endif
63
64#ifdef CONFIG_PVR2_DMA
65#include <linux/pagemap.h>
66#include <mach/dma.h>
67#include <asm/dma.h>
68#endif
69
70#ifdef CONFIG_SH_STORE_QUEUES
71#include <linux/uaccess.h>
72#include <cpu/sq.h>
73#endif
74
75#ifndef PCI_DEVICE_ID_NEC_NEON250
76# define PCI_DEVICE_ID_NEC_NEON250 0x0067
77#endif
78
79
80#define DISP_BASE par->mmio_base
81#define DISP_BRDRCOLR (DISP_BASE + 0x40)
82#define DISP_DIWMODE (DISP_BASE + 0x44)
83#define DISP_DIWADDRL (DISP_BASE + 0x50)
84#define DISP_DIWADDRS (DISP_BASE + 0x54)
85#define DISP_DIWSIZE (DISP_BASE + 0x5c)
86#define DISP_SYNCCONF (DISP_BASE + 0xd0)
87#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
88#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
89#define DISP_BRDRVERT (DISP_BASE + 0xdc)
90#define DISP_DIWCONF (DISP_BASE + 0xe8)
91#define DISP_DIWHSTRT (DISP_BASE + 0xec)
92#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
93#define DISP_PIXDEPTH (DISP_BASE + 0x108)
94
95
96#define TV_CLK 74239
97#define VGA_CLK 37119
98
99
100#define PAL_HTOTAL 863
101#define PAL_VTOTAL 312
102#define NTSC_HTOTAL 857
103#define NTSC_VTOTAL 262
104
105
106enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
107
108
109enum { VO_PAL, VO_NTSC, VO_VGA };
110
111
112enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
113
114struct pvr2_params { unsigned int val; char *name; };
115static struct pvr2_params cables[] = {
116 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
117};
118
119static struct pvr2_params outputs[] = {
120 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
121};
122
123
124
125
126
127static struct pvr2fb_par {
128 unsigned int hsync_total;
129 unsigned int vsync_total;
130 unsigned int borderstart_h;
131 unsigned int borderstop_h;
132 unsigned int borderstart_v;
133 unsigned int borderstop_v;
134 unsigned int diwstart_h;
135 unsigned int diwstart_v;
136
137 unsigned long disp_start;
138 unsigned char is_interlaced;
139 unsigned char is_doublescan;
140 unsigned char is_lowres;
141
142 unsigned long mmio_base;
143 u32 palette[16];
144} *currentpar;
145
146static struct fb_info *fb_info;
147
148static struct fb_fix_screeninfo pvr2_fix = {
149 .id = "NEC PowerVR2",
150 .type = FB_TYPE_PACKED_PIXELS,
151 .visual = FB_VISUAL_TRUECOLOR,
152 .ypanstep = 1,
153 .ywrapstep = 1,
154 .accel = FB_ACCEL_NONE,
155};
156
157static struct fb_var_screeninfo pvr2_var = {
158 .xres = 640,
159 .yres = 480,
160 .xres_virtual = 640,
161 .yres_virtual = 480,
162 .bits_per_pixel =16,
163 .red = { 11, 5, 0 },
164 .green = { 5, 6, 0 },
165 .blue = { 0, 5, 0 },
166 .activate = FB_ACTIVATE_NOW,
167 .height = -1,
168 .width = -1,
169 .vmode = FB_VMODE_NONINTERLACED,
170};
171
172static int cable_type = CT_VGA;
173static int video_output = VO_VGA;
174
175static int nopan = 0;
176static int nowrap = 1;
177
178
179
180
181static unsigned int do_vmode_full = 0;
182static unsigned int do_vmode_pan = 0;
183static short do_blank = 0;
184
185static unsigned int is_blanked = 0;
186
187#ifdef CONFIG_SH_STORE_QUEUES
188static unsigned long pvr2fb_map;
189#endif
190
191#ifdef CONFIG_PVR2_DMA
192static unsigned int shdma = PVR2_CASCADE_CHAN;
193static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
194#endif
195
196static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
197 unsigned int transp, struct fb_info *info);
198static int pvr2fb_blank(int blank, struct fb_info *info);
199static unsigned long get_line_length(int xres_virtual, int bpp);
200static void set_color_bitfields(struct fb_var_screeninfo *var);
201static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
202static int pvr2fb_set_par(struct fb_info *info);
203static void pvr2_update_display(struct fb_info *info);
204static void pvr2_init_display(struct fb_info *info);
205static void pvr2_do_blank(void);
206static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
207static int pvr2_init_cable(void);
208static int pvr2_get_param(const struct pvr2_params *p, const char *s,
209 int val, int size);
210#ifdef CONFIG_PVR2_DMA
211static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
212 size_t count, loff_t *ppos);
213#endif
214
215static struct fb_ops pvr2fb_ops = {
216 .owner = THIS_MODULE,
217 .fb_setcolreg = pvr2fb_setcolreg,
218 .fb_blank = pvr2fb_blank,
219 .fb_check_var = pvr2fb_check_var,
220 .fb_set_par = pvr2fb_set_par,
221#ifdef CONFIG_PVR2_DMA
222 .fb_write = pvr2fb_write,
223#endif
224 .fb_fillrect = cfb_fillrect,
225 .fb_copyarea = cfb_copyarea,
226 .fb_imageblit = cfb_imageblit,
227};
228
229static struct fb_videomode pvr2_modedb[] = {
230
231
232
233
234
235
236 {
237
238 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
239 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
240 }, {
241
242
243 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
244 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
245 }, {
246
247 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
248 0, FB_VMODE_YWRAP
249 },
250};
251
252#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
253
254#define DEFMODE_NTSC 0
255#define DEFMODE_PAL 0
256#define DEFMODE_VGA 2
257
258static int defmode = DEFMODE_NTSC;
259static char *mode_option = NULL;
260
261static inline void pvr2fb_set_pal_type(unsigned int type)
262{
263 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
264
265 fb_writel(type, par->mmio_base + 0x108);
266}
267
268static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
269 unsigned int regno,
270 unsigned int val)
271{
272 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
273}
274
275static int pvr2fb_blank(int blank, struct fb_info *info)
276{
277 do_blank = blank ? blank : -1;
278 return 0;
279}
280
281static inline unsigned long get_line_length(int xres_virtual, int bpp)
282{
283 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
284}
285
286static void set_color_bitfields(struct fb_var_screeninfo *var)
287{
288 switch (var->bits_per_pixel) {
289 case 16:
290 pvr2fb_set_pal_type(PAL_RGB565);
291 var->red.offset = 11; var->red.length = 5;
292 var->green.offset = 5; var->green.length = 6;
293 var->blue.offset = 0; var->blue.length = 5;
294 var->transp.offset = 0; var->transp.length = 0;
295 break;
296 case 24:
297 var->red.offset = 16; var->red.length = 8;
298 var->green.offset = 8; var->green.length = 8;
299 var->blue.offset = 0; var->blue.length = 8;
300 var->transp.offset = 0; var->transp.length = 0;
301 break;
302 case 32:
303 pvr2fb_set_pal_type(PAL_ARGB8888);
304 var->red.offset = 16; var->red.length = 8;
305 var->green.offset = 8; var->green.length = 8;
306 var->blue.offset = 0; var->blue.length = 8;
307 var->transp.offset = 24; var->transp.length = 8;
308 break;
309 }
310}
311
312static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
313 unsigned int green, unsigned int blue,
314 unsigned int transp, struct fb_info *info)
315{
316 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
317 unsigned int tmp;
318
319 if (regno > info->cmap.len)
320 return 1;
321
322
323
324
325
326
327 switch (info->var.bits_per_pixel) {
328 case 16:
329 tmp = (red & 0xf800) |
330 ((green & 0xfc00) >> 5) |
331 ((blue & 0xf800) >> 11);
332
333 pvr2fb_set_pal_entry(par, regno, tmp);
334 break;
335 case 24:
336 red >>= 8; green >>= 8; blue >>= 8;
337 tmp = (red << 16) | (green << 8) | blue;
338 break;
339 case 32:
340 red >>= 8; green >>= 8; blue >>= 8;
341 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
342
343 pvr2fb_set_pal_entry(par, regno, tmp);
344 break;
345 default:
346 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
347 return 1;
348 }
349
350 if (regno < 16)
351 ((u32*)(info->pseudo_palette))[regno] = tmp;
352
353 return 0;
354}
355
356static int pvr2fb_set_par(struct fb_info *info)
357{
358 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
359 struct fb_var_screeninfo *var = &info->var;
360 unsigned long line_length;
361 unsigned int vtotal;
362
363
364
365
366
367
368
369
370 cable_type = pvr2_init_cable();
371 if (cable_type == CT_VGA && video_output != VO_VGA)
372 video_output = VO_VGA;
373
374 var->vmode &= FB_VMODE_MASK;
375 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
376 par->is_interlaced = 1;
377
378
379
380
381 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
382 par->is_doublescan = 1;
383
384 par->hsync_total = var->left_margin + var->xres + var->right_margin +
385 var->hsync_len;
386 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
387 var->vsync_len;
388
389 if (var->sync & FB_SYNC_BROADCAST) {
390 vtotal = par->vsync_total;
391 if (par->is_interlaced)
392 vtotal /= 2;
393 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
394
395
396 par->borderstart_h = 116;
397 par->borderstart_v = 44;
398 } else {
399
400 par->borderstart_h = 126;
401 par->borderstart_v = 18;
402 }
403 } else {
404
405
406
407
408
409
410 par->borderstart_h = 126;
411 par->borderstart_v = 40;
412 }
413
414
415 par->diwstart_h = par->borderstart_h + var->left_margin;
416 par->diwstart_v = par->borderstart_v + var->upper_margin;
417 par->borderstop_h = par->diwstart_h + var->xres +
418 var->right_margin;
419 par->borderstop_v = par->diwstart_v + var->yres +
420 var->lower_margin;
421
422 if (!par->is_interlaced)
423 par->borderstop_v /= 2;
424 if (info->var.xres < 640)
425 par->is_lowres = 1;
426
427 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
428 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
429 info->fix.line_length = line_length;
430 return 0;
431}
432
433static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
434{
435 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
436 unsigned int vtotal, hsync_total;
437 unsigned long line_length;
438
439 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
440 pr_debug("Invalid pixclock value %d\n", var->pixclock);
441 return -EINVAL;
442 }
443
444 if (var->xres < 320)
445 var->xres = 320;
446 if (var->yres < 240)
447 var->yres = 240;
448 if (var->xres_virtual < var->xres)
449 var->xres_virtual = var->xres;
450 if (var->yres_virtual < var->yres)
451 var->yres_virtual = var->yres;
452
453 if (var->bits_per_pixel <= 16)
454 var->bits_per_pixel = 16;
455 else if (var->bits_per_pixel <= 24)
456 var->bits_per_pixel = 24;
457 else if (var->bits_per_pixel <= 32)
458 var->bits_per_pixel = 32;
459
460 set_color_bitfields(var);
461
462 if (var->vmode & FB_VMODE_YWRAP) {
463 if (var->xoffset || var->yoffset < 0 ||
464 var->yoffset >= var->yres_virtual) {
465 var->xoffset = var->yoffset = 0;
466 } else {
467 if (var->xoffset > var->xres_virtual - var->xres ||
468 var->yoffset > var->yres_virtual - var->yres ||
469 var->xoffset < 0 || var->yoffset < 0)
470 var->xoffset = var->yoffset = 0;
471 }
472 } else {
473 var->xoffset = var->yoffset = 0;
474 }
475
476
477
478
479
480 if (var->yres < 480 && video_output == VO_VGA)
481 var->vmode |= FB_VMODE_DOUBLE;
482
483 if (video_output != VO_VGA) {
484 var->sync |= FB_SYNC_BROADCAST;
485 var->vmode |= FB_VMODE_INTERLACED;
486 } else {
487 var->sync &= ~FB_SYNC_BROADCAST;
488 var->vmode &= ~FB_VMODE_INTERLACED;
489 var->vmode |= FB_VMODE_NONINTERLACED;
490 }
491
492 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
493 var->right_margin = par->borderstop_h -
494 (par->diwstart_h + var->xres);
495 var->left_margin = par->diwstart_h - par->borderstart_h;
496 var->hsync_len = par->borderstart_h +
497 (par->hsync_total - par->borderstop_h);
498
499 var->upper_margin = par->diwstart_v - par->borderstart_v;
500 var->lower_margin = par->borderstop_v -
501 (par->diwstart_v + var->yres);
502 var->vsync_len = par->borderstop_v +
503 (par->vsync_total - par->borderstop_v);
504 }
505
506 hsync_total = var->left_margin + var->xres + var->right_margin +
507 var->hsync_len;
508 vtotal = var->upper_margin + var->yres + var->lower_margin +
509 var->vsync_len;
510
511 if (var->sync & FB_SYNC_BROADCAST) {
512 if (var->vmode & FB_VMODE_INTERLACED)
513 vtotal /= 2;
514 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
515
516
517 if (hsync_total != PAL_HTOTAL) {
518 pr_debug("invalid hsync total for PAL\n");
519 return -EINVAL;
520 }
521 } else {
522
523 if (hsync_total != NTSC_HTOTAL) {
524 pr_debug("invalid hsync total for NTSC\n");
525 return -EINVAL;
526 }
527 }
528 }
529
530
531 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
532 if (line_length * var->yres_virtual > info->fix.smem_len)
533 return -ENOMEM;
534
535 return 0;
536}
537
538static void pvr2_update_display(struct fb_info *info)
539{
540 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
541 struct fb_var_screeninfo *var = &info->var;
542
543
544 fb_writel(par->disp_start, DISP_DIWADDRL);
545 fb_writel(par->disp_start +
546 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
547 DISP_DIWADDRS);
548}
549
550
551
552
553
554
555
556static void pvr2_init_display(struct fb_info *info)
557{
558 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
559 struct fb_var_screeninfo *var = &info->var;
560 unsigned int diw_height, diw_width, diw_modulo = 1;
561 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
562
563
564 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
565
566
567
568
569 if (video_output != VO_VGA && par->is_interlaced)
570 diw_modulo += info->fix.line_length / 4;
571 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
572 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
573 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
574 DISP_DIWSIZE);
575
576
577 fb_writel(par->disp_start, DISP_DIWADDRL);
578 fb_writel(par->disp_start +
579 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
580 DISP_DIWADDRS);
581
582
583 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
584 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
585 fb_writel(0, DISP_BRDRCOLR);
586
587
588 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
589 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
590
591
592 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
593
594
595 fb_writel(((video_output == VO_VGA) << 23) |
596 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
597
598
599 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
600 fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
601
602
603
604 fb_writel(0x100 | ((par->is_interlaced ) << 4), DISP_SYNCCONF);
605}
606
607
608
609#define BLANK_BIT (1<<3)
610
611static void pvr2_do_blank(void)
612{
613 struct pvr2fb_par *par = currentpar;
614 unsigned long diwconf;
615
616 diwconf = fb_readl(DISP_DIWCONF);
617 if (do_blank > 0)
618 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
619 else
620 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
621
622 is_blanked = do_blank > 0 ? do_blank : 0;
623}
624
625static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
626{
627 struct fb_info *info = dev_id;
628
629 if (do_vmode_pan || do_vmode_full)
630 pvr2_update_display(info);
631 if (do_vmode_full)
632 pvr2_init_display(info);
633 if (do_vmode_pan)
634 do_vmode_pan = 0;
635 if (do_vmode_full)
636 do_vmode_full = 0;
637 if (do_blank) {
638 pvr2_do_blank();
639 do_blank = 0;
640 }
641 return IRQ_HANDLED;
642}
643
644
645
646
647
648
649#define PCTRA 0xff80002c
650#define PDTRA 0xff800030
651#define VOUTC 0xa0702c00
652
653static int pvr2_init_cable(void)
654{
655 if (cable_type < 0) {
656 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
657 PCTRA);
658 cable_type = (fb_readw(PDTRA) >> 8) & 3;
659 }
660
661
662
663
664 if (cable_type == CT_COMPOSITE)
665 fb_writel(3 << 8, VOUTC);
666 else if (cable_type == CT_RGB)
667 fb_writel(1 << 9, VOUTC);
668 else
669 fb_writel(0, VOUTC);
670
671 return cable_type;
672}
673
674#ifdef CONFIG_PVR2_DMA
675static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
676 size_t count, loff_t *ppos)
677{
678 unsigned long dst, start, end, len;
679 unsigned int nr_pages;
680 struct page **pages;
681 int ret, i;
682
683 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
684
685 pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
686 if (!pages)
687 return -ENOMEM;
688
689 ret = get_user_pages_unlocked(current, current->mm, (unsigned long)buf,
690 nr_pages, WRITE, 0, pages);
691
692 if (ret < nr_pages) {
693 nr_pages = ret;
694 ret = -EINVAL;
695 goto out_unmap;
696 }
697
698 dma_configure_channel(shdma, 0x12c1);
699
700 dst = (unsigned long)fb_info->screen_base + *ppos;
701 start = (unsigned long)page_address(pages[0]);
702 end = (unsigned long)page_address(pages[nr_pages]);
703 len = nr_pages << PAGE_SHIFT;
704
705
706 if (start + len == end) {
707
708 if ((*ppos + len) > fb_info->fix.smem_len) {
709 ret = -ENOSPC;
710 goto out_unmap;
711 }
712
713 dma_write(shdma, start, 0, len);
714 dma_write(pvr2dma, 0, dst, len);
715 dma_wait_for_completion(pvr2dma);
716
717 goto out;
718 }
719
720
721 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
722 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
723 ret = -ENOSPC;
724 goto out_unmap;
725 }
726
727 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
728 dma_write_page(pvr2dma, 0, dst);
729 dma_wait_for_completion(pvr2dma);
730 }
731
732out:
733 *ppos += count;
734 ret = count;
735
736out_unmap:
737 for (i = 0; i < nr_pages; i++)
738 page_cache_release(pages[i]);
739
740 kfree(pages);
741
742 return ret;
743}
744#endif
745
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758
759
760
761
762
763
764static int pvr2fb_common_init(void)
765{
766 struct pvr2fb_par *par = currentpar;
767 unsigned long modememused, rev;
768
769 fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
770 pvr2_fix.smem_len);
771
772 if (!fb_info->screen_base) {
773 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
774 goto out_err;
775 }
776
777 par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
778 pvr2_fix.mmio_len);
779 if (!par->mmio_base) {
780 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
781 goto out_err;
782 }
783
784 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
785
786 pvr2_fix.ypanstep = nopan ? 0 : 1;
787 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
788
789 fb_info->fbops = &pvr2fb_ops;
790 fb_info->fix = pvr2_fix;
791 fb_info->par = currentpar;
792 fb_info->pseudo_palette = currentpar->palette;
793 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
794
795 if (video_output == VO_VGA)
796 defmode = DEFMODE_VGA;
797
798 if (!mode_option)
799 mode_option = "640x480@60";
800
801 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
802 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
803 fb_info->var = pvr2_var;
804
805 fb_alloc_cmap(&fb_info->cmap, 256, 0);
806
807 if (register_framebuffer(fb_info) < 0)
808 goto out_err;
809
810 pvr2_init_display(fb_info);
811
812 modememused = get_line_length(fb_info->var.xres_virtual,
813 fb_info->var.bits_per_pixel);
814 modememused *= fb_info->var.yres_virtual;
815
816 rev = fb_readl(par->mmio_base + 0x04);
817
818 printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
819 fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
820 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
821 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
822 fb_info->node, fb_info->var.xres, fb_info->var.yres,
823 fb_info->var.bits_per_pixel,
824 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
825 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
826 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
827
828#ifdef CONFIG_SH_STORE_QUEUES
829 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
830
831 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
832 fb_info->fix.id, PAGE_SHARED);
833
834 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
835 fb_info->node, pvr2fb_map);
836#endif
837
838 return 0;
839
840out_err:
841 if (fb_info->screen_base)
842 iounmap(fb_info->screen_base);
843 if (par->mmio_base)
844 iounmap((void *)par->mmio_base);
845
846 return -ENXIO;
847}
848
849#ifdef CONFIG_SH_DREAMCAST
850static int __init pvr2fb_dc_init(void)
851{
852 if (!mach_is_dreamcast())
853 return -ENXIO;
854
855
856 if (pvr2_init_cable() == CT_VGA) {
857 fb_info->monspecs.hfmin = 30000;
858 fb_info->monspecs.hfmax = 70000;
859 fb_info->monspecs.vfmin = 60;
860 fb_info->monspecs.vfmax = 60;
861 } else {
862
863 fb_info->monspecs.hfmin = 15469;
864 fb_info->monspecs.hfmax = 15781;
865 fb_info->monspecs.vfmin = 49;
866 fb_info->monspecs.vfmax = 51;
867 }
868
869
870
871
872 if (video_output < 0) {
873 if (cable_type == CT_VGA) {
874 video_output = VO_VGA;
875 } else {
876 video_output = VO_NTSC;
877 }
878 }
879
880
881
882
883 pvr2_fix.smem_start = 0xa5000000;
884 pvr2_fix.smem_len = 8 << 20;
885
886 pvr2_fix.mmio_start = 0xa05f8000;
887 pvr2_fix.mmio_len = 0x2000;
888
889 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
890 "pvr2 VBL handler", fb_info)) {
891 return -EBUSY;
892 }
893
894#ifdef CONFIG_PVR2_DMA
895 if (request_dma(pvr2dma, "pvr2") != 0) {
896 free_irq(HW_EVENT_VSYNC, fb_info);
897 return -EBUSY;
898 }
899#endif
900
901 return pvr2fb_common_init();
902}
903
904static void __exit pvr2fb_dc_exit(void)
905{
906 if (fb_info->screen_base) {
907 iounmap(fb_info->screen_base);
908 fb_info->screen_base = NULL;
909 }
910 if (currentpar->mmio_base) {
911 iounmap((void *)currentpar->mmio_base);
912 currentpar->mmio_base = 0;
913 }
914
915 free_irq(HW_EVENT_VSYNC, fb_info);
916#ifdef CONFIG_PVR2_DMA
917 free_dma(pvr2dma);
918#endif
919}
920#endif
921
922#ifdef CONFIG_PCI
923static int pvr2fb_pci_probe(struct pci_dev *pdev,
924 const struct pci_device_id *ent)
925{
926 int ret;
927
928 ret = pci_enable_device(pdev);
929 if (ret) {
930 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
931 return ret;
932 }
933
934 ret = pci_request_regions(pdev, "pvr2fb");
935 if (ret) {
936 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
937 return ret;
938 }
939
940
941
942
943 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
944 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
945
946 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
947 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
948
949 fb_info->device = &pdev->dev;
950
951 return pvr2fb_common_init();
952}
953
954static void pvr2fb_pci_remove(struct pci_dev *pdev)
955{
956 if (fb_info->screen_base) {
957 iounmap(fb_info->screen_base);
958 fb_info->screen_base = NULL;
959 }
960 if (currentpar->mmio_base) {
961 iounmap((void *)currentpar->mmio_base);
962 currentpar->mmio_base = 0;
963 }
964
965 pci_release_regions(pdev);
966}
967
968static struct pci_device_id pvr2fb_pci_tbl[] = {
969 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
971 { 0, },
972};
973
974MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
975
976static struct pci_driver pvr2fb_pci_driver = {
977 .name = "pvr2fb",
978 .id_table = pvr2fb_pci_tbl,
979 .probe = pvr2fb_pci_probe,
980 .remove = pvr2fb_pci_remove,
981};
982
983static int __init pvr2fb_pci_init(void)
984{
985 return pci_register_driver(&pvr2fb_pci_driver);
986}
987
988static void __exit pvr2fb_pci_exit(void)
989{
990 pci_unregister_driver(&pvr2fb_pci_driver);
991}
992#endif
993
994static int pvr2_get_param(const struct pvr2_params *p, const char *s, int val,
995 int size)
996{
997 int i;
998
999 for (i = 0 ; i < size ; i++ ) {
1000 if (s != NULL) {
1001 if (!strnicmp(p[i].name, s, strlen(s)))
1002 return p[i].val;
1003 } else {
1004 if (p[i].val == val)
1005 return (int)p[i].name;
1006 }
1007 }
1008 return -1;
1009}
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021#ifndef MODULE
1022static int __init pvr2fb_setup(char *options)
1023{
1024 char *this_opt;
1025 char cable_arg[80];
1026 char output_arg[80];
1027
1028 if (!options || !*options)
1029 return 0;
1030
1031 while ((this_opt = strsep(&options, ","))) {
1032 if (!*this_opt)
1033 continue;
1034 if (!strcmp(this_opt, "inverse")) {
1035 fb_invert_cmaps();
1036 } else if (!strncmp(this_opt, "cable:", 6)) {
1037 strcpy(cable_arg, this_opt + 6);
1038 } else if (!strncmp(this_opt, "output:", 7)) {
1039 strcpy(output_arg, this_opt + 7);
1040 } else if (!strncmp(this_opt, "nopan", 5)) {
1041 nopan = 1;
1042 } else if (!strncmp(this_opt, "nowrap", 6)) {
1043 nowrap = 1;
1044 } else {
1045 mode_option = this_opt;
1046 }
1047 }
1048
1049 if (*cable_arg)
1050 cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
1051 if (*output_arg)
1052 video_output = pvr2_get_param(outputs, output_arg, 0, 3);
1053
1054 return 0;
1055}
1056#endif
1057
1058static struct pvr2_board {
1059 int (*init)(void);
1060 void (*exit)(void);
1061 char name[16];
1062} board_driver[] __refdata = {
1063#ifdef CONFIG_SH_DREAMCAST
1064 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1065#endif
1066#ifdef CONFIG_PCI
1067 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1068#endif
1069 { 0, },
1070};
1071
1072static int __init pvr2fb_init(void)
1073{
1074 int i, ret = -ENODEV;
1075 int size;
1076
1077#ifndef MODULE
1078 char *option = NULL;
1079
1080 if (fb_get_options("pvr2fb", &option))
1081 return -ENODEV;
1082 pvr2fb_setup(option);
1083#endif
1084 size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
1085
1086 fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1087
1088 if (!fb_info) {
1089 printk(KERN_ERR "Failed to allocate memory for fb_info\n");
1090 return -ENOMEM;
1091 }
1092
1093
1094 currentpar = fb_info->par;
1095
1096 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1097 struct pvr2_board *pvr_board = board_driver + i;
1098
1099 if (!pvr_board->init)
1100 continue;
1101
1102 ret = pvr_board->init();
1103
1104 if (ret != 0) {
1105 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1106 pvr_board->name);
1107 framebuffer_release(fb_info);
1108 break;
1109 }
1110 }
1111
1112 return ret;
1113}
1114
1115static void __exit pvr2fb_exit(void)
1116{
1117 int i;
1118
1119 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1120 struct pvr2_board *pvr_board = board_driver + i;
1121
1122 if (pvr_board->exit)
1123 pvr_board->exit();
1124 }
1125
1126#ifdef CONFIG_SH_STORE_QUEUES
1127 sq_unmap(pvr2fb_map);
1128#endif
1129
1130 unregister_framebuffer(fb_info);
1131 framebuffer_release(fb_info);
1132}
1133
1134module_init(pvr2fb_init);
1135module_exit(pvr2fb_exit);
1136
1137MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1138MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1139MODULE_LICENSE("GPL");
1140