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21#ifndef LINUX_CPER_H
22#define LINUX_CPER_H
23
24#include <linux/uuid.h>
25#include <linux/trace_seq.h>
26
27
28#define CPER_SIG_RECORD "CPER"
29#define CPER_SIG_SIZE 4
30
31#define CPER_SIG_END 0xffffffff
32
33
34
35
36
37#define CPER_RECORD_REV 0x0100
38
39
40
41
42
43
44
45#define CPER_REC_LEN 256
46
47
48
49
50enum {
51 CPER_SEV_RECOVERABLE,
52 CPER_SEV_FATAL,
53 CPER_SEV_CORRECTED,
54 CPER_SEV_INFORMATIONAL,
55};
56
57
58
59
60
61
62
63
64#define CPER_VALID_PLATFORM_ID 0x0001
65
66#define CPER_VALID_TIMESTAMP 0x0002
67
68#define CPER_VALID_PARTITION_ID 0x0004
69
70
71
72
73
74
75
76#define CPER_NOTIFY_CMC \
77 UUID_LE(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
78 0xEB, 0xD4, 0xF8, 0x90)
79
80#define CPER_NOTIFY_CPE \
81 UUID_LE(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
82 0xF2, 0x7E, 0xBE, 0xEE)
83
84#define CPER_NOTIFY_MCE \
85 UUID_LE(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
86 0xE1, 0x49, 0x13, 0xBB)
87
88#define CPER_NOTIFY_PCIE \
89 UUID_LE(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
90 0xAF, 0x67, 0xC1, 0x04)
91
92#define CPER_NOTIFY_INIT \
93 UUID_LE(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
94 0xD3, 0x9B, 0xC9, 0x8E)
95
96#define CPER_NOTIFY_NMI \
97 UUID_LE(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
98 0x85, 0xD6, 0xE9, 0x8A)
99
100#define CPER_NOTIFY_BOOT \
101 UUID_LE(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
102 0xD4, 0x64, 0xB3, 0x8F)
103
104#define CPER_NOTIFY_DMAR \
105 UUID_LE(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
106 0x72, 0x2D, 0xEB, 0x41)
107
108
109
110
111
112#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
113
114#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
115
116#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
117
118
119
120
121
122#define CPER_SEC_REV 0x0100
123
124
125
126
127
128
129
130
131#define CPER_SEC_VALID_FRU_ID 0x1
132
133#define CPER_SEC_VALID_FRU_TEXT 0x2
134
135
136
137
138
139
140
141#define CPER_SEC_PRIMARY 0x0001
142
143
144
145
146
147#define CPER_SEC_CONTAINMENT_WARNING 0x0002
148
149#define CPER_SEC_RESET 0x0004
150
151#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
152
153
154
155
156
157#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
158
159
160
161
162
163
164#define CPER_SEC_LATENT_ERROR 0x0020
165
166
167
168
169
170
171
172#define CPER_SEC_PROC_GENERIC \
173 UUID_LE(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
174 0x93, 0xC4, 0xF3, 0xDB)
175
176#define CPER_SEC_PROC_IA \
177 UUID_LE(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
178 0x24, 0x2B, 0x6E, 0x1D)
179
180#define CPER_SEC_PROC_IPF \
181 UUID_LE(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
182 0x80, 0xC7, 0x3C, 0x88, 0x81)
183
184#define CPER_SEC_PLATFORM_MEM \
185 UUID_LE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
186 0xED, 0x7C, 0x83, 0xB1)
187#define CPER_SEC_PCIE \
188 UUID_LE(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
189 0xCB, 0x3C, 0x6F, 0x35)
190
191#define CPER_SEC_FW_ERR_REC_REF \
192 UUID_LE(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
193 0x9C, 0x8E, 0x69, 0xED)
194
195#define CPER_SEC_PCI_X_BUS \
196 UUID_LE(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
197 0xD3, 0xF9, 0xC9, 0xDD)
198
199#define CPER_SEC_PCI_DEV \
200 UUID_LE(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
201 0x8B, 0x00, 0x13, 0x26)
202#define CPER_SEC_DMAR_GENERIC \
203 UUID_LE(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
204 0xDE, 0x3E, 0x2C, 0x64)
205
206#define CPER_SEC_DMAR_VT \
207 UUID_LE(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
208 0xDD, 0x93, 0xE8, 0xCF)
209
210#define CPER_SEC_DMAR_IOMMU \
211 UUID_LE(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
212 0xDF, 0xAA, 0x84, 0xEC)
213
214#define CPER_PROC_VALID_TYPE 0x0001
215#define CPER_PROC_VALID_ISA 0x0002
216#define CPER_PROC_VALID_ERROR_TYPE 0x0004
217#define CPER_PROC_VALID_OPERATION 0x0008
218#define CPER_PROC_VALID_FLAGS 0x0010
219#define CPER_PROC_VALID_LEVEL 0x0020
220#define CPER_PROC_VALID_VERSION 0x0040
221#define CPER_PROC_VALID_BRAND_INFO 0x0080
222#define CPER_PROC_VALID_ID 0x0100
223#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
224#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
225#define CPER_PROC_VALID_RESPONDER_ID 0x0800
226#define CPER_PROC_VALID_IP 0x1000
227
228#define CPER_MEM_VALID_ERROR_STATUS 0x0001
229#define CPER_MEM_VALID_PA 0x0002
230#define CPER_MEM_VALID_PA_MASK 0x0004
231#define CPER_MEM_VALID_NODE 0x0008
232#define CPER_MEM_VALID_CARD 0x0010
233#define CPER_MEM_VALID_MODULE 0x0020
234#define CPER_MEM_VALID_BANK 0x0040
235#define CPER_MEM_VALID_DEVICE 0x0080
236#define CPER_MEM_VALID_ROW 0x0100
237#define CPER_MEM_VALID_COLUMN 0x0200
238#define CPER_MEM_VALID_BIT_POSITION 0x0400
239#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
240#define CPER_MEM_VALID_RESPONDER_ID 0x1000
241#define CPER_MEM_VALID_TARGET_ID 0x2000
242#define CPER_MEM_VALID_ERROR_TYPE 0x4000
243#define CPER_MEM_VALID_RANK_NUMBER 0x8000
244#define CPER_MEM_VALID_CARD_HANDLE 0x10000
245#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
246
247#define CPER_PCIE_VALID_PORT_TYPE 0x0001
248#define CPER_PCIE_VALID_VERSION 0x0002
249#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
250#define CPER_PCIE_VALID_DEVICE_ID 0x0008
251#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
252#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
253#define CPER_PCIE_VALID_CAPABILITY 0x0040
254#define CPER_PCIE_VALID_AER_INFO 0x0080
255
256#define CPER_PCIE_SLOT_SHIFT 3
257
258
259
260
261
262#pragma pack(1)
263
264struct cper_record_header {
265 char signature[CPER_SIG_SIZE];
266 __u16 revision;
267 __u32 signature_end;
268 __u16 section_count;
269 __u32 error_severity;
270 __u32 validation_bits;
271 __u32 record_length;
272 __u64 timestamp;
273 uuid_le platform_id;
274 uuid_le partition_id;
275 uuid_le creator_id;
276 uuid_le notification_type;
277 __u64 record_id;
278 __u32 flags;
279 __u64 persistence_information;
280 __u8 reserved[12];
281};
282
283struct cper_section_descriptor {
284 __u32 section_offset;
285
286
287 __u32 section_length;
288 __u16 revision;
289 __u8 validation_bits;
290 __u8 reserved;
291 __u32 flags;
292 uuid_le section_type;
293 uuid_le fru_id;
294 __u32 section_severity;
295 __u8 fru_text[20];
296};
297
298
299struct cper_sec_proc_generic {
300 __u64 validation_bits;
301 __u8 proc_type;
302 __u8 proc_isa;
303 __u8 proc_error_type;
304 __u8 operation;
305 __u8 flags;
306 __u8 level;
307 __u16 reserved;
308 __u64 cpu_version;
309 char cpu_brand[128];
310 __u64 proc_id;
311 __u64 target_addr;
312 __u64 requestor_id;
313 __u64 responder_id;
314 __u64 ip;
315};
316
317
318struct cper_sec_proc_ia {
319 __u64 validation_bits;
320 __u8 lapic_id;
321 __u8 cpuid[48];
322};
323
324
325struct cper_ia_err_info {
326 uuid_le err_type;
327 __u64 validation_bits;
328 __u64 check_info;
329 __u64 target_id;
330 __u64 requestor_id;
331 __u64 responder_id;
332 __u64 ip;
333};
334
335
336struct cper_ia_proc_ctx {
337 __u16 reg_ctx_type;
338 __u16 reg_arr_size;
339 __u32 msr_addr;
340 __u64 mm_reg_addr;
341};
342
343
344struct cper_sec_mem_err {
345 __u64 validation_bits;
346 __u64 error_status;
347 __u64 physical_addr;
348 __u64 physical_addr_mask;
349 __u16 node;
350 __u16 card;
351 __u16 module;
352 __u16 bank;
353 __u16 device;
354 __u16 row;
355 __u16 column;
356 __u16 bit_pos;
357 __u64 requestor_id;
358 __u64 responder_id;
359 __u64 target_id;
360 __u8 error_type;
361 __u8 reserved;
362 __u16 rank;
363 __u16 mem_array_handle;
364 __u16 mem_dev_handle;
365};
366
367struct cper_mem_err_compact {
368 __u64 validation_bits;
369 __u16 node;
370 __u16 card;
371 __u16 module;
372 __u16 bank;
373 __u16 device;
374 __u16 row;
375 __u16 column;
376 __u16 bit_pos;
377 __u64 requestor_id;
378 __u64 responder_id;
379 __u64 target_id;
380 __u16 rank;
381 __u16 mem_array_handle;
382 __u16 mem_dev_handle;
383};
384
385struct cper_sec_pcie {
386 __u64 validation_bits;
387 __u32 port_type;
388 struct {
389 __u8 minor;
390 __u8 major;
391 __u8 reserved[2];
392 } version;
393 __u16 command;
394 __u16 status;
395 __u32 reserved;
396 struct {
397 __u16 vendor_id;
398 __u16 device_id;
399 __u8 class_code[3];
400 __u8 function;
401 __u8 device;
402 __u16 segment;
403 __u8 bus;
404 __u8 secondary_bus;
405 __u16 slot;
406 __u8 reserved;
407 } device_id;
408 struct {
409 __u32 lower;
410 __u32 upper;
411 } serial_number;
412 struct {
413 __u16 secondary_status;
414 __u16 control;
415 } bridge;
416 __u8 capability[60];
417 __u8 aer_info[96];
418};
419
420
421#pragma pack()
422
423u64 cper_next_record_id(void);
424const char *cper_severity_str(unsigned int);
425const char *cper_mem_err_type_str(unsigned int);
426void cper_print_bits(const char *prefix, unsigned int bits,
427 const char * const strs[], unsigned int strs_size);
428void cper_mem_err_pack(const struct cper_sec_mem_err *,
429 struct cper_mem_err_compact *);
430const char *cper_mem_err_unpack(struct trace_seq *,
431 struct cper_mem_err_compact *);
432
433#endif
434