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16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
19
20#include <linux/mod_devicetable.h>
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/compiler.h>
27#include <linux/errno.h>
28#include <linux/kobject.h>
29#include <linux/atomic.h>
30#include <linux/device.h>
31#ifndef __GENKSYMS__
32#include <linux/interrupt.h>
33#endif
34#include <linux/io.h>
35#include <linux/resource_ext.h>
36#include <uapi/linux/pci.h>
37
38#include <linux/pci_ids.h>
39
40#include <linux/rh_kabi.h>
41
42#ifndef msi_controller
43#define msi_controller msi_chip
44#endif
45
46
47
48
49
50
51
52
53
54
55
56
57
58#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
59
60#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
61
62
63struct pci_slot {
64 struct pci_bus *bus;
65 struct list_head list;
66 struct hotplug_slot *hotplug;
67 unsigned char number;
68 struct kobject kobj;
69};
70
71static inline const char *pci_slot_name(const struct pci_slot *slot)
72{
73 return kobject_name(&slot->kobj);
74}
75
76
77enum pci_mmap_state {
78 pci_mmap_io,
79 pci_mmap_mem
80};
81
82
83
84
85enum {
86
87 PCI_STD_RESOURCES,
88 PCI_STD_RESOURCE_END = 5,
89
90
91 PCI_ROM_RESOURCE,
92
93
94#ifdef CONFIG_PCI_IOV
95 PCI_IOV_RESOURCES,
96 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
97#endif
98
99
100#define PCI_BRIDGE_RESOURCE_NUM 4
101
102 PCI_BRIDGE_RESOURCES,
103 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
104 PCI_BRIDGE_RESOURCE_NUM - 1,
105
106
107 PCI_NUM_RESOURCES,
108
109
110 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
111};
112
113typedef int __bitwise pci_power_t;
114
115#define PCI_D0 ((pci_power_t __force) 0)
116#define PCI_D1 ((pci_power_t __force) 1)
117#define PCI_D2 ((pci_power_t __force) 2)
118#define PCI_D3hot ((pci_power_t __force) 3)
119#define PCI_D3cold ((pci_power_t __force) 4)
120#define PCI_UNKNOWN ((pci_power_t __force) 5)
121#define PCI_POWER_ERROR ((pci_power_t __force) -1)
122
123
124extern const char *pci_power_names[];
125
126static inline const char *pci_power_name(pci_power_t state)
127{
128 return pci_power_names[1 + (int) state];
129}
130
131#define PCI_PM_D2_DELAY 200
132#define PCI_PM_D3_WAIT 10
133#define PCI_PM_D3COLD_WAIT 100
134#define PCI_PM_BUS_WAIT 50
135
136
137
138
139
140typedef unsigned int __bitwise pci_channel_state_t;
141
142enum pci_channel_state {
143
144 pci_channel_io_normal = (__force pci_channel_state_t) 1,
145
146
147 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
148
149
150 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
151};
152
153typedef unsigned int __bitwise pcie_reset_state_t;
154
155enum pcie_reset_state {
156
157 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
158
159
160 pcie_warm_reset = (__force pcie_reset_state_t) 2,
161
162
163 pcie_hot_reset = (__force pcie_reset_state_t) 3
164};
165
166typedef unsigned short __bitwise pci_dev_flags_t;
167enum pci_dev_flags {
168
169
170
171 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
172
173 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
174
175 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
176
177 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
178
179 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
180
181 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
182
183 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
184
185 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
186
187 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
188
189 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
190};
191
192enum pci_irq_reroute_variant {
193 INTEL_IRQ_REROUTE_VARIANT = 1,
194 MAX_IRQ_REROUTE_VARIANTS = 3
195};
196
197typedef unsigned short __bitwise pci_bus_flags_t;
198enum pci_bus_flags {
199 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
200 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
201};
202
203
204enum pcie_link_width {
205 PCIE_LNK_WIDTH_RESRV = 0x00,
206 PCIE_LNK_X1 = 0x01,
207 PCIE_LNK_X2 = 0x02,
208 PCIE_LNK_X4 = 0x04,
209 PCIE_LNK_X8 = 0x08,
210 PCIE_LNK_X12 = 0x0C,
211 PCIE_LNK_X16 = 0x10,
212 PCIE_LNK_X32 = 0x20,
213 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
214};
215
216
217enum pci_bus_speed {
218 PCI_SPEED_33MHz = 0x00,
219 PCI_SPEED_66MHz = 0x01,
220 PCI_SPEED_66MHz_PCIX = 0x02,
221 PCI_SPEED_100MHz_PCIX = 0x03,
222 PCI_SPEED_133MHz_PCIX = 0x04,
223 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
224 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
225 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
226 PCI_SPEED_66MHz_PCIX_266 = 0x09,
227 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
228 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
229 AGP_UNKNOWN = 0x0c,
230 AGP_1X = 0x0d,
231 AGP_2X = 0x0e,
232 AGP_4X = 0x0f,
233 AGP_8X = 0x10,
234 PCI_SPEED_66MHz_PCIX_533 = 0x11,
235 PCI_SPEED_100MHz_PCIX_533 = 0x12,
236 PCI_SPEED_133MHz_PCIX_533 = 0x13,
237 PCIE_SPEED_2_5GT = 0x14,
238 PCIE_SPEED_5_0GT = 0x15,
239 PCIE_SPEED_8_0GT = 0x16,
240 PCIE_SPEED_16_0GT = 0x17,
241 PCI_SPEED_UNKNOWN = 0xff,
242};
243
244enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
245enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
246
247struct pci_cap_saved_data {
248 u16 cap_nr;
249 bool cap_extended;
250 unsigned int size;
251 u32 data[0];
252};
253
254struct pci_cap_saved_state {
255 struct hlist_node next;
256 struct pci_cap_saved_data cap;
257};
258
259struct irq_affinity;
260struct pcie_link_state;
261struct pci_vpd;
262struct pci_sriov;
263struct pci_ats;
264#ifdef CONFIG_PPC64
265struct pci_dn;
266#endif
267
268
269
270
271struct pci_dev {
272 struct list_head bus_list;
273 struct pci_bus *bus;
274 struct pci_bus *subordinate;
275
276 void *sysdata;
277 struct proc_dir_entry *procent;
278 struct pci_slot *slot;
279
280 unsigned int devfn;
281 unsigned short vendor;
282 unsigned short device;
283 unsigned short subsystem_vendor;
284 unsigned short subsystem_device;
285 unsigned int class;
286 u8 revision;
287 u8 hdr_type;
288 u8 pcie_cap;
289 u8 msi_cap;
290 u8 msix_cap;
291 u8 pcie_mpss:3;
292 u8 rom_base_reg;
293 u8 pin;
294 u16 pcie_flags_reg;
295
296 struct pci_driver *driver;
297 u64 dma_mask;
298
299
300
301
302
303 struct device_dma_parameters dma_parms;
304
305 pci_power_t current_state;
306
307
308 u8 pm_cap;
309 unsigned int pme_support:5;
310
311 unsigned int pme_interrupt:1;
312 unsigned int pme_poll:1;
313 unsigned int d1_support:1;
314 unsigned int d2_support:1;
315 unsigned int no_d1d2:1;
316 unsigned int no_d3cold:1;
317 unsigned int d3cold_allowed:1;
318 unsigned int mmio_always_on:1;
319
320 unsigned int wakeup_prepared:1;
321 unsigned int runtime_d3cold:1;
322
323
324
325 RH_KABI_FILL_HOLE(unsigned int ignore_hotplug:1)
326 RH_KABI_FILL_HOLE(unsigned int hotplug_user_indicators:1)
327 RH_KABI_FILL_HOLE(unsigned int bridge_d3:1)
328 RH_KABI_FILL_HOLE(unsigned int clear_retrain_link:1)
329 unsigned int d3_delay;
330 unsigned int d3cold_delay;
331
332#ifdef CONFIG_PCIEASPM
333 struct pcie_link_state *link_state;
334#endif
335
336 pci_channel_state_t error_state;
337 struct device dev;
338
339 int cfg_size;
340
341
342
343
344
345 unsigned int irq;
346 struct resource resource[DEVICE_COUNT_RESOURCE];
347
348 bool match_driver;
349
350 unsigned int transparent:1;
351 unsigned int multifunction:1;
352
353 unsigned int is_added:1;
354 unsigned int is_busmaster:1;
355 unsigned int no_msi:1;
356 unsigned int block_cfg_access:1;
357 unsigned int broken_parity_status:1;
358 unsigned int irq_reroute_variant:2;
359 unsigned int msi_enabled:1;
360 unsigned int msix_enabled:1;
361 unsigned int ari_enabled:1;
362 unsigned int is_managed:1;
363 unsigned int needs_freset:1;
364 unsigned int state_saved:1;
365 unsigned int is_physfn:1;
366 unsigned int is_virtfn:1;
367 unsigned int reset_fn:1;
368 unsigned int is_hotplug_bridge:1;
369 unsigned int __aer_firmware_first_valid:1;
370 unsigned int __aer_firmware_first:1;
371 unsigned int broken_intx_masking:1;
372 unsigned int io_window_1k:1;
373 RH_KABI_FILL_HOLE(unsigned int no_64bit_msi:1)
374 RH_KABI_FILL_HOLE(unsigned int irq_managed:1)
375 RH_KABI_FILL_HOLE(unsigned int has_secondary_link:1)
376 RH_KABI_FILL_HOLE(unsigned int non_compliant_bars:1)
377 RH_KABI_FILL_HOLE(unsigned int is_thunderbolt:1)
378 RH_KABI_FILL_HOLE(unsigned int shpc_managed:1)
379 pci_dev_flags_t dev_flags;
380 atomic_t enable_cnt;
381
382 u32 saved_config_space[16];
383 struct hlist_head saved_cap_space;
384 struct bin_attribute *rom_attr;
385 int rom_attr_enabled;
386 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
387 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
388#ifdef CONFIG_PCI_MSI
389 struct list_head msi_list;
390 struct kset *msi_kset;
391 const struct attribute_group **msi_irq_groups;
392#endif
393 struct pci_vpd *vpd;
394#ifdef CONFIG_PCI_ATS
395 union {
396 struct pci_sriov *sriov;
397 struct pci_dev *physfn;
398 };
399 struct pci_ats *ats;
400#endif
401 phys_addr_t rom;
402 size_t romlen;
403
404
405
406
407 struct pci_dev_rh *pci_dev_rh;
408};
409
410
411
412
413
414struct pci_dev_rh {
415 RH_KABI_EXTEND(unsigned long *dma_alias_mask)
416 RH_KABI_EXTEND(char *driver_override)
417#ifdef CONFIG_PPC64
418 RH_KABI_EXTEND(struct pci_dn *pci_data)
419#endif
420 RH_KABI_EXTEND(unsigned int ats_enabled:1)
421#ifdef CONFIG_PCI_ATS
422 RH_KABI_EXTEND(u16 ats_cap)
423 RH_KABI_EXTEND(u8 ats_stu)
424 RH_KABI_EXTEND(atomic_t ats_ref_cnt)
425#endif
426 RH_KABI_EXTEND(unsigned long priv_flags)
427};
428
429static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
430{
431#ifdef CONFIG_PCI_IOV
432 if (dev->is_virtfn)
433 dev = dev->physfn;
434#endif
435 return dev;
436}
437
438struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
439
440#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
441#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
442
443static inline int pci_channel_offline(struct pci_dev *pdev)
444{
445 return (pdev->error_state != pci_channel_io_normal);
446}
447
448struct pci_host_bridge {
449 struct device dev;
450 struct pci_bus *bus;
451 struct list_head windows;
452 void (*release_fn)(struct pci_host_bridge *);
453 void *release_data;
454 unsigned int ignore_reset_delay:1;
455 unsigned int native_aer:1;
456 unsigned int native_pcie_hotplug:1;
457 unsigned int native_shpc_hotplug:1;
458 unsigned int native_pme:1;
459
460 resource_size_t (*align_resource)(struct pci_dev *dev,
461 const struct resource *res,
462 resource_size_t start,
463 resource_size_t size,
464 resource_size_t align);
465};
466
467#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
468
469struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
470
471void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
472 void (*release_fn)(struct pci_host_bridge *),
473 void *release_data);
474
475int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
476
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487
488
489
490#define PCI_SUBTRACTIVE_DECODE 0x1
491
492struct pci_bus_resource {
493 struct list_head list;
494 struct resource *res;
495 unsigned int flags;
496};
497
498#define PCI_REGION_FLAG_MASK 0x0fU
499
500struct pci_bus {
501 struct list_head node;
502 struct pci_bus *parent;
503 struct list_head children;
504 struct list_head devices;
505 struct pci_dev *self;
506 struct list_head slots;
507
508 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
509 struct list_head resources;
510 struct resource busn_res;
511
512 struct pci_ops *ops;
513 struct msi_controller *msi;
514 void *sysdata;
515 struct proc_dir_entry *procdir;
516
517 unsigned char number;
518 unsigned char primary;
519 unsigned char max_bus_speed;
520 unsigned char cur_bus_speed;
521#ifdef CONFIG_PCI_DOMAINS_GENERIC
522 int domain_nr;
523#endif
524
525 char name[48];
526
527 unsigned short bridge_ctl;
528 pci_bus_flags_t bus_flags;
529 struct device *bridge;
530 struct device dev;
531 struct bin_attribute *legacy_io;
532 struct bin_attribute *legacy_mem;
533 unsigned int is_added:1;
534
535
536
537
538 struct pci_bus_rh *pci_bus_rh;
539};
540
541
542
543
544
545struct pci_bus_rh {
546#ifndef __GENKSYMS__
547#endif
548};
549
550#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
551
552
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558
559
560static inline bool pci_is_root_bus(struct pci_bus *pbus)
561{
562 return !(pbus->parent);
563}
564
565
566
567
568
569
570
571
572static inline bool pci_is_bridge(struct pci_dev *dev)
573{
574 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
575 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
576}
577
578#define for_each_pci_bridge(dev, bus) \
579 list_for_each_entry(dev, &bus->devices, bus_list) \
580 if (!pci_is_bridge(dev)) {} else
581
582static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
583{
584 dev = pci_physfn(dev);
585 if (pci_is_root_bus(dev->bus))
586 return NULL;
587
588 return dev->bus->self;
589}
590
591struct device *pci_get_host_bridge_device(struct pci_dev *dev);
592void pci_put_host_bridge_device(struct device *dev);
593
594#ifdef CONFIG_PCI_MSI
595static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
596{
597 return pci_dev->msi_enabled || pci_dev->msix_enabled;
598}
599#else
600static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
601#endif
602
603
604
605
606#define PCIBIOS_SUCCESSFUL 0x00
607#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
608#define PCIBIOS_BAD_VENDOR_ID 0x83
609#define PCIBIOS_DEVICE_NOT_FOUND 0x86
610#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
611#define PCIBIOS_SET_FAILED 0x88
612#define PCIBIOS_BUFFER_TOO_SMALL 0x89
613
614
615
616
617static inline int pcibios_err_to_errno(int err)
618{
619 if (err <= PCIBIOS_SUCCESSFUL)
620 return err;
621
622 switch (err) {
623 case PCIBIOS_FUNC_NOT_SUPPORTED:
624 return -ENOENT;
625 case PCIBIOS_BAD_VENDOR_ID:
626 return -ENOTTY;
627 case PCIBIOS_DEVICE_NOT_FOUND:
628 return -ENODEV;
629 case PCIBIOS_BAD_REGISTER_NUMBER:
630 return -EFAULT;
631 case PCIBIOS_SET_FAILED:
632 return -EIO;
633 case PCIBIOS_BUFFER_TOO_SMALL:
634 return -ENOSPC;
635 }
636
637 return -ERANGE;
638}
639
640
641
642struct pci_ops {
643 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
644 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
645};
646
647
648
649
650
651int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
652 int reg, int len, u32 *val);
653int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
654 int reg, int len, u32 val);
655
656#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
657typedef u64 pci_bus_addr_t;
658#else
659typedef u32 pci_bus_addr_t;
660#endif
661
662struct pci_bus_region {
663 pci_bus_addr_t start;
664 pci_bus_addr_t end;
665};
666
667struct pci_dynids {
668 spinlock_t lock;
669 struct list_head list;
670};
671
672
673
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675
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677
678
679
680typedef unsigned int __bitwise pci_ers_result_t;
681
682enum pci_ers_result {
683
684 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
685
686
687 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
688
689
690 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
691
692
693 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
694
695
696 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
697
698
699 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
700};
701
702
703struct pci_error_handlers {
704
705 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
706 enum pci_channel_state error);
707
708
709 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
710
711
712 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
713
714
715 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
716
717
718 void (*resume)(struct pci_dev *dev);
719};
720
721
722struct module;
723struct pci_driver {
724 struct list_head node;
725 const char *name;
726 const struct pci_device_id *id_table;
727 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
728 void (*remove) (struct pci_dev *dev);
729 int (*suspend) (struct pci_dev *dev, pm_message_t state);
730 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
731 int (*resume_early) (struct pci_dev *dev);
732 int (*resume) (struct pci_dev *dev);
733 void (*shutdown) (struct pci_dev *dev);
734 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
735 const struct pci_error_handlers *err_handler;
736 struct device_driver driver;
737 struct pci_dynids dynids;
738
739
740
741
742 struct pci_driver_rh *pci_driver_rh;
743};
744
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756
757
758struct pci_driver_rh {
759 unsigned int size;
760#ifndef __GENKSYMS__
761
762 void (*reset_notify)(struct pci_dev *dev, bool prepare);
763#endif
764};
765
766
767#define set_pci_driver_rh_size(ptr) \
768 ptr.size = sizeof(struct pci_driver_rh)
769
770#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
771
772
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775
776
777
778#define DEFINE_PCI_DEVICE_TABLE(_table) \
779 const struct pci_device_id _table[]
780
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784
785
786
787
788
789
790#define PCI_DEVICE(vend,dev) \
791 .vendor = (vend), .device = (dev), \
792 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
793
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795
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802
803
804#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
805 .vendor = (vend), .device = (dev), \
806 .subvendor = (subvend), .subdevice = (subdev)
807
808
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815
816
817#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
818 .class = (dev_class), .class_mask = (dev_class_mask), \
819 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
821
822
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832
833#define PCI_VDEVICE(vend, dev) \
834 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
835 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
836
837enum {
838 PCI_REASSIGN_ALL_RSRC = 0x00000001,
839 PCI_REASSIGN_ALL_BUS = 0x00000002,
840 PCI_PROBE_ONLY = 0x00000004,
841 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
842 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
843 PCI_COMPAT_DOMAIN_0 = 0x00000020,
844 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
845};
846
847
848#ifdef CONFIG_PCI
849
850extern unsigned int pci_flags;
851
852static inline void pci_set_flags(int flags) { pci_flags = flags; }
853static inline void pci_add_flags(int flags) { pci_flags |= flags; }
854static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
855static inline int pci_has_flag(int flag) { return pci_flags & flag; }
856
857void pcie_bus_configure_settings(struct pci_bus *bus);
858
859enum pcie_bus_config_types {
860 PCIE_BUS_TUNE_OFF,
861 PCIE_BUS_DEFAULT,
862 PCIE_BUS_SAFE,
863 PCIE_BUS_PERFORMANCE,
864 PCIE_BUS_PEER2PEER,
865};
866
867extern enum pcie_bus_config_types pcie_bus_config;
868
869extern struct bus_type pci_bus_type;
870
871
872
873extern struct list_head pci_root_buses;
874
875int no_pci_devices(void);
876
877void pcibios_resource_survey_bus(struct pci_bus *bus);
878void pcibios_bus_add_device(struct pci_dev *pdev);
879void pcibios_add_bus(struct pci_bus *bus);
880void pcibios_remove_bus(struct pci_bus *bus);
881void pcibios_fixup_bus(struct pci_bus *);
882int __must_check pcibios_enable_device(struct pci_dev *, int mask);
883
884char *pcibios_setup(char *str);
885
886
887resource_size_t pcibios_align_resource(void *, const struct resource *,
888 resource_size_t,
889 resource_size_t);
890void pcibios_update_irq(struct pci_dev *, int irq);
891
892
893void pci_fixup_cardbus(struct pci_bus *);
894
895
896
897void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
898 struct resource *res);
899void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
900 struct pci_bus_region *region);
901void pcibios_scan_specific_bus(int busn);
902struct pci_bus *pci_find_bus(int domain, int busnr);
903void pci_bus_add_devices(const struct pci_bus *bus);
904struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
905struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
906 struct pci_ops *ops, void *sysdata,
907 struct list_head *resources);
908int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
909int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
910void pci_bus_release_busn_res(struct pci_bus *b);
911struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
912 struct pci_ops *ops, void *sysdata,
913 struct list_head *resources,
914 struct msi_controller *msi);
915struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
916 struct pci_ops *ops, void *sysdata,
917 struct list_head *resources);
918struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
919 int busnr);
920void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
921struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
922 const char *name,
923 struct hotplug_slot *hotplug);
924void pci_destroy_slot(struct pci_slot *slot);
925#ifdef CONFIG_SYSFS
926void pci_dev_assign_slot(struct pci_dev *dev);
927#else
928static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
929#endif
930int pci_scan_slot(struct pci_bus *bus, int devfn);
931struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
932void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
933unsigned int pci_scan_child_bus(struct pci_bus *bus);
934void pci_bus_add_device(struct pci_dev *dev);
935void pci_read_bridge_bases(struct pci_bus *child);
936struct resource *pci_find_parent_resource(const struct pci_dev *dev,
937 struct resource *res);
938struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
939u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
940int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
941u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
942struct pci_dev *pci_dev_get(struct pci_dev *dev);
943void pci_dev_put(struct pci_dev *dev);
944void pci_remove_bus(struct pci_bus *b);
945void pci_stop_and_remove_bus_device(struct pci_dev *dev);
946void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
947void pci_stop_root_bus(struct pci_bus *bus);
948void pci_remove_root_bus(struct pci_bus *bus);
949void pci_setup_cardbus(struct pci_bus *bus);
950void pci_sort_breadthfirst(void);
951#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
952bool dev_is_pf(struct device *dev);
953int dev_num_vf(struct device *dev);
954
955
956
957enum pci_lost_interrupt_reason {
958 PCI_LOST_IRQ_NO_INFORMATION = 0,
959 PCI_LOST_IRQ_DISABLE_MSI,
960 PCI_LOST_IRQ_DISABLE_MSIX,
961 PCI_LOST_IRQ_DISABLE_ACPI,
962};
963enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
964int pci_find_capability(struct pci_dev *dev, int cap);
965int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
966int pci_find_ext_capability(struct pci_dev *dev, int cap);
967int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
968int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
969int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
970struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
971
972struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
973 struct pci_dev *from);
974struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
975 unsigned int ss_vendor, unsigned int ss_device,
976 struct pci_dev *from);
977struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
978struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
979 unsigned int devfn);
980struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
981struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
982int pci_dev_present(const struct pci_device_id *ids);
983
984int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
985 int where, u8 *val);
986int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
987 int where, u16 *val);
988int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
989 int where, u32 *val);
990int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
991 int where, u8 val);
992int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
993 int where, u16 val);
994int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
995 int where, u32 val);
996struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
997
998int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
999int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1000int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1001int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1002int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1003int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1004
1005int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1006int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1007int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1008int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1009int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1010 u16 clear, u16 set);
1011int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1012 u32 clear, u32 set);
1013int pcie_capability_set_word(struct pci_dev *dev, int pos, u16 set);
1014int pcie_capability_clear_word(struct pci_dev *dev, int pos, u16 clear);
1015
1016static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1017 u32 set)
1018{
1019 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1020}
1021
1022static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1023 u32 clear)
1024{
1025 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1026}
1027
1028
1029int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1030int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1031int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1032int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1033int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1034int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1035
1036int __must_check pci_enable_device(struct pci_dev *dev);
1037int __must_check pci_enable_device_io(struct pci_dev *dev);
1038int __must_check pci_enable_device_mem(struct pci_dev *dev);
1039int __must_check pci_reenable_device(struct pci_dev *);
1040int __must_check pcim_enable_device(struct pci_dev *pdev);
1041void pcim_pin_device(struct pci_dev *pdev);
1042int pci_is_enabled(struct pci_dev *pdev);
1043
1044static inline int pci_is_managed(struct pci_dev *pdev)
1045{
1046 return pdev->is_managed;
1047}
1048
1049void pci_disable_device(struct pci_dev *dev);
1050
1051extern unsigned int pcibios_max_latency;
1052void pci_set_master(struct pci_dev *dev);
1053void pci_clear_master(struct pci_dev *dev);
1054
1055int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1056int pci_set_cacheline_size(struct pci_dev *dev);
1057#define HAVE_PCI_SET_MWI
1058int __must_check pci_set_mwi(struct pci_dev *dev);
1059int __must_check pcim_set_mwi(struct pci_dev *dev);
1060int pci_try_set_mwi(struct pci_dev *dev);
1061void pci_clear_mwi(struct pci_dev *dev);
1062void pci_intx(struct pci_dev *dev, int enable);
1063bool pci_intx_mask_supported(struct pci_dev *dev);
1064bool pci_check_and_mask_intx(struct pci_dev *dev);
1065bool pci_check_and_unmask_intx(struct pci_dev *dev);
1066int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1067int pci_wait_for_pending_transaction(struct pci_dev *dev);
1068int pcix_get_max_mmrbc(struct pci_dev *dev);
1069int pcix_get_mmrbc(struct pci_dev *dev);
1070int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1071int pcie_get_readrq(struct pci_dev *dev);
1072int pcie_set_readrq(struct pci_dev *dev, int rq);
1073int pcie_get_mps(struct pci_dev *dev);
1074int pcie_set_mps(struct pci_dev *dev, int mps);
1075int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1076 enum pcie_link_width *width);
1077u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1078 enum pci_bus_speed *speed,
1079 enum pcie_link_width *width);
1080void pcie_print_link_status(struct pci_dev *dev);
1081bool pcie_has_flr(struct pci_dev *dev);
1082void pcie_flr(struct pci_dev *dev);
1083int __pci_reset_function(struct pci_dev *dev);
1084int __pci_reset_function_locked(struct pci_dev *dev);
1085int pci_reset_function(struct pci_dev *dev);
1086int pci_reset_function_locked(struct pci_dev *dev);
1087int pci_try_reset_function(struct pci_dev *dev);
1088int pci_probe_reset_slot(struct pci_slot *slot);
1089int pci_reset_slot(struct pci_slot *slot);
1090int pci_try_reset_slot(struct pci_slot *slot);
1091int pci_probe_reset_bus(struct pci_bus *bus);
1092int pci_reset_bus(struct pci_bus *bus);
1093int pci_try_reset_bus(struct pci_bus *bus);
1094void pci_reset_secondary_bus(struct pci_dev *dev);
1095void pcibios_reset_secondary_bus(struct pci_dev *dev);
1096void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1097void pci_update_resource(struct pci_dev *dev, int resno);
1098int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1099int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1100void pci_release_resource(struct pci_dev *dev, int resno);
1101int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1102int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1103bool pci_device_is_present(struct pci_dev *pdev);
1104void pci_ignore_hotplug(struct pci_dev *dev);
1105
1106int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1107 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1108 const char *fmt, ...);
1109void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1110
1111
1112int pci_enable_rom(struct pci_dev *pdev);
1113void pci_disable_rom(struct pci_dev *pdev);
1114void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1115void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1116size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1117void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1118
1119
1120int pci_save_state(struct pci_dev *dev);
1121void pci_restore_state(struct pci_dev *dev);
1122struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1123int pci_load_saved_state(struct pci_dev *dev,
1124 struct pci_saved_state *state);
1125int pci_load_and_free_saved_state(struct pci_dev *dev,
1126 struct pci_saved_state **state);
1127struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1128struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1129 u16 cap);
1130int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1131int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1132 u16 cap, unsigned int size);
1133int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1134int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1135pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1136bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1137void pci_pme_active(struct pci_dev *dev, bool enable);
1138int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1139 bool runtime, bool enable);
1140int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1141int pci_prepare_to_sleep(struct pci_dev *dev);
1142int pci_back_from_sleep(struct pci_dev *dev);
1143bool pci_dev_run_wake(struct pci_dev *dev);
1144bool pci_check_pme_status(struct pci_dev *dev);
1145void pci_pme_wakeup_bus(struct pci_bus *bus);
1146void pci_d3cold_enable(struct pci_dev *dev);
1147void pci_d3cold_disable(struct pci_dev *dev);
1148bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1149
1150int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1151
1152
1153int pci_save_vc_state(struct pci_dev *dev);
1154void pci_restore_vc_state(struct pci_dev *dev);
1155void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1156
1157
1158void set_pcie_port_type(struct pci_dev *pdev);
1159void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1160
1161
1162int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1163unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1164unsigned int pci_rescan_bus(struct pci_bus *bus);
1165void pci_lock_rescan_remove(void);
1166void pci_unlock_rescan_remove(void);
1167
1168
1169ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1170ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1171int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1172
1173
1174resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1175void pci_bus_assign_resources(const struct pci_bus *bus);
1176void pci_bus_size_bridges(struct pci_bus *bus);
1177int pci_claim_resource(struct pci_dev *, int);
1178int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1179void pci_assign_unassigned_resources(void);
1180void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1181void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1182void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1183int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1184void pdev_enable_device(struct pci_dev *);
1185int pci_enable_resources(struct pci_dev *, int mask);
1186void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1187 int (*)(const struct pci_dev *, u8, u8));
1188#define HAVE_PCI_REQ_REGIONS 2
1189int __must_check pci_request_regions(struct pci_dev *, const char *);
1190int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1191void pci_release_regions(struct pci_dev *);
1192int __must_check pci_request_region(struct pci_dev *, int, const char *);
1193int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1194void pci_release_region(struct pci_dev *, int);
1195int pci_request_selected_regions(struct pci_dev *, int, const char *);
1196int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1197void pci_release_selected_regions(struct pci_dev *, int);
1198
1199
1200struct pci_bus *pci_bus_get(struct pci_bus *bus);
1201void pci_bus_put(struct pci_bus *bus);
1202void pci_add_resource(struct list_head *resources, struct resource *res);
1203void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1204 resource_size_t offset);
1205void pci_free_resource_list(struct list_head *resources);
1206void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1207struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1208void pci_bus_remove_resources(struct pci_bus *bus);
1209
1210#define pci_bus_for_each_resource(bus, res, i) \
1211 for (i = 0; \
1212 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1213 i++)
1214
1215int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1216 struct resource *res, resource_size_t size,
1217 resource_size_t align, resource_size_t min,
1218 unsigned long type_mask,
1219 resource_size_t (*alignf)(void *,
1220 const struct resource *,
1221 resource_size_t,
1222 resource_size_t),
1223 void *alignf_data);
1224
1225
1226int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1227
1228static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1229{
1230 struct pci_bus_region region;
1231
1232 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1233 return region.start;
1234}
1235
1236
1237int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1238 const char *mod_name);
1239
1240
1241
1242
1243#define pci_register_driver(driver) \
1244 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1245
1246void pci_unregister_driver(struct pci_driver *dev);
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256#define module_pci_driver(__pci_driver) \
1257 module_driver(__pci_driver, pci_register_driver, \
1258 pci_unregister_driver)
1259
1260struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1261int pci_add_dynid(struct pci_driver *drv,
1262 unsigned int vendor, unsigned int device,
1263 unsigned int subvendor, unsigned int subdevice,
1264 unsigned int class, unsigned int class_mask,
1265 unsigned long driver_data);
1266const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1267 struct pci_dev *dev);
1268
1269const struct pci_device_id *pci_hw_vendor_status(
1270 const struct pci_device_id *ids,
1271 struct pci_dev *dev);
1272int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1273 int pass);
1274
1275void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1276 void *userdata);
1277int pci_cfg_space_size(struct pci_dev *dev);
1278unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1279void pci_setup_bridge(struct pci_bus *bus);
1280resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1281 unsigned long type);
1282resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1283
1284#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1285#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1286
1287int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1288 unsigned int command_bits, u32 flags);
1289#define PCI_IRQ_LEGACY (1 << 0)
1290#define PCI_IRQ_MSI (1 << 1)
1291#define PCI_IRQ_MSIX (1 << 2)
1292#define PCI_IRQ_AFFINITY (1 << 3)
1293#define PCI_IRQ_ALL_TYPES \
1294 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1295
1296
1297
1298#include <linux/dmapool.h>
1299
1300#define pci_pool dma_pool
1301#define pci_pool_create(name, pdev, size, align, allocation) \
1302 dma_pool_create(name, &pdev->dev, size, align, allocation)
1303#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1304#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1305#define pci_pool_zalloc(pool, flags, handle) \
1306 dma_pool_zalloc(pool, flags, handle)
1307#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1308
1309struct msix_entry {
1310 u32 vector;
1311 u16 entry;
1312};
1313
1314#ifdef CONFIG_PCI_MSI
1315int pci_msi_vec_count(struct pci_dev *dev);
1316int pci_enable_msi_block(struct pci_dev *dev, int nvec);
1317void pci_msi_shutdown(struct pci_dev *dev);
1318void pci_disable_msi(struct pci_dev *dev);
1319int pci_msix_vec_count(struct pci_dev *dev);
1320int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1321void pci_msix_shutdown(struct pci_dev *dev);
1322void pci_disable_msix(struct pci_dev *dev);
1323void pci_restore_msi_state(struct pci_dev *dev);
1324int pci_msi_enabled(void);
1325int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1326static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1327{
1328 int rc = pci_enable_msi_range(dev, nvec, nvec);
1329 if (rc < 0)
1330 return rc;
1331 return 0;
1332}
1333int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1334 int minvec, int maxvec);
1335static inline int pci_enable_msix_exact(struct pci_dev *dev,
1336 struct msix_entry *entries, int nvec)
1337{
1338 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1339 if (rc < 0)
1340 return rc;
1341 return 0;
1342}
1343int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1344 unsigned int max_vecs, unsigned int flags,
1345 const struct irq_affinity *affd);
1346
1347void pci_free_irq_vectors(struct pci_dev *dev);
1348int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1349const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1350int pci_irq_get_node(struct pci_dev *pdev, int vec);
1351
1352#else
1353static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1354static inline int pci_enable_msi_block(struct pci_dev *dev, int nvec)
1355{ return -ENOSYS; }
1356static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1357static inline void pci_disable_msi(struct pci_dev *dev) { }
1358static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1359static inline int pci_enable_msix(struct pci_dev *dev,
1360 struct msix_entry *entries, int nvec)
1361{ return -ENOSYS; }
1362static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1363static inline void pci_disable_msix(struct pci_dev *dev) { }
1364static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1365static inline int pci_msi_enabled(void) { return 0; }
1366static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1367 int maxvec)
1368{ return -ENOSYS; }
1369static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1370{ return -ENOSYS; }
1371static inline int pci_enable_msix_range(struct pci_dev *dev,
1372 struct msix_entry *entries, int minvec, int maxvec)
1373{ return -ENOSYS; }
1374static inline int pci_enable_msix_exact(struct pci_dev *dev,
1375 struct msix_entry *entries, int nvec)
1376{ return -ENOSYS; }
1377
1378static inline int
1379pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1380 unsigned int max_vecs, unsigned int flags,
1381 const struct irq_affinity *aff_desc)
1382{
1383 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1384 return 1;
1385 return -ENOSPC;
1386}
1387
1388static inline void pci_free_irq_vectors(struct pci_dev *dev)
1389{
1390}
1391
1392static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1393{
1394 if (WARN_ON_ONCE(nr > 0))
1395 return -EINVAL;
1396 return dev->irq;
1397}
1398static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1399 int vec)
1400{
1401 return cpu_possible_mask;
1402}
1403
1404static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1405{
1406 return first_online_node;
1407}
1408#endif
1409
1410static inline int
1411pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1412 unsigned int max_vecs, unsigned int flags)
1413{
1414 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1415 NULL);
1416}
1417
1418#ifdef CONFIG_PCIEPORTBUS
1419extern bool pcie_ports_disabled;
1420extern bool pcie_ports_native;
1421#else
1422#define pcie_ports_disabled true
1423#define pcie_ports_native false
1424#endif
1425
1426#ifdef CONFIG_PCIEASPM
1427bool pcie_aspm_support_enabled(void);
1428#else
1429static inline bool pcie_aspm_support_enabled(void) { return false; }
1430#endif
1431
1432#ifdef CONFIG_PCIEAER
1433void pci_no_aer(void);
1434bool pci_aer_available(void);
1435#else
1436static inline void pci_no_aer(void) { }
1437static inline bool pci_aer_available(void) { return false; }
1438#endif
1439
1440#ifdef CONFIG_PCIE_ECRC
1441void pcie_set_ecrc_checking(struct pci_dev *dev);
1442void pcie_ecrc_get_policy(char *str);
1443#else
1444static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1445static inline void pcie_ecrc_get_policy(char *str) { }
1446#endif
1447
1448#define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1449
1450#ifdef CONFIG_HT_IRQ
1451
1452int ht_create_irq(struct pci_dev *dev, int idx);
1453void ht_destroy_irq(unsigned int irq);
1454#endif
1455
1456#ifdef CONFIG_PCI_ATS
1457
1458void pci_ats_init(struct pci_dev *dev);
1459int pci_enable_ats(struct pci_dev *dev, int ps);
1460void pci_disable_ats(struct pci_dev *dev);
1461int pci_ats_queue_depth(struct pci_dev *dev);
1462#else
1463static inline void pci_ats_init(struct pci_dev *d) { }
1464static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1465static inline void pci_disable_ats(struct pci_dev *d) { }
1466static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1467#endif
1468
1469void pci_cfg_access_lock(struct pci_dev *dev);
1470bool pci_cfg_access_trylock(struct pci_dev *dev);
1471void pci_cfg_access_unlock(struct pci_dev *dev);
1472
1473
1474
1475
1476
1477
1478#ifdef CONFIG_PCI_DOMAINS
1479extern int pci_domains_supported;
1480#else
1481enum { pci_domains_supported = 0 };
1482static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1483static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1484#endif
1485
1486
1487
1488
1489
1490
1491#ifdef CONFIG_PCI_DOMAINS_GENERIC
1492static inline int pci_domain_nr(struct pci_bus *bus)
1493{
1494 return bus->domain_nr;
1495}
1496void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1497#else
1498static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1499 struct device *parent)
1500{
1501}
1502#endif
1503
1504
1505typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1506 unsigned int command_bits, u32 flags);
1507void pci_register_set_vga_state(arch_set_vga_state_t func);
1508
1509static inline int
1510pci_request_io_regions(struct pci_dev *pdev, const char *name)
1511{
1512 return pci_request_selected_regions(pdev,
1513 pci_select_bars(pdev, IORESOURCE_IO), name);
1514}
1515
1516static inline void
1517pci_release_io_regions(struct pci_dev *pdev)
1518{
1519 return pci_release_selected_regions(pdev,
1520 pci_select_bars(pdev, IORESOURCE_IO));
1521}
1522
1523static inline int
1524pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1525{
1526 return pci_request_selected_regions(pdev,
1527 pci_select_bars(pdev, IORESOURCE_MEM), name);
1528}
1529
1530static inline void
1531pci_release_mem_regions(struct pci_dev *pdev)
1532{
1533 return pci_release_selected_regions(pdev,
1534 pci_select_bars(pdev, IORESOURCE_MEM));
1535}
1536
1537#else
1538
1539static inline void pci_set_flags(int flags) { }
1540static inline void pci_add_flags(int flags) { }
1541static inline void pci_clear_flags(int flags) { }
1542static inline int pci_has_flag(int flag) { return 0; }
1543
1544
1545
1546
1547
1548
1549#define _PCI_NOP(o, s, t) \
1550 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1551 int where, t val) \
1552 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1553
1554#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1555 _PCI_NOP(o, word, u16 x) \
1556 _PCI_NOP(o, dword, u32 x)
1557_PCI_NOP_ALL(read, *)
1558_PCI_NOP_ALL(write,)
1559
1560static inline struct pci_dev *pci_get_device(unsigned int vendor,
1561 unsigned int device,
1562 struct pci_dev *from)
1563{ return NULL; }
1564
1565static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1566 unsigned int device,
1567 unsigned int ss_vendor,
1568 unsigned int ss_device,
1569 struct pci_dev *from)
1570{ return NULL; }
1571
1572static inline struct pci_dev *pci_get_class(unsigned int class,
1573 struct pci_dev *from)
1574{ return NULL; }
1575
1576#define pci_dev_present(ids) (0)
1577#define no_pci_devices() (1)
1578#define pci_dev_put(dev) do { } while (0)
1579
1580static inline void pci_set_master(struct pci_dev *dev) { }
1581static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1582static inline void pci_disable_device(struct pci_dev *dev) { }
1583static inline int pci_assign_resource(struct pci_dev *dev, int i)
1584{ return -EBUSY; }
1585static inline int __pci_register_driver(struct pci_driver *drv,
1586 struct module *owner)
1587{ return 0; }
1588static inline int pci_register_driver(struct pci_driver *drv)
1589{ return 0; }
1590static inline void pci_unregister_driver(struct pci_driver *drv) { }
1591static inline int pci_find_capability(struct pci_dev *dev, int cap)
1592{ return 0; }
1593static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1594 int cap)
1595{ return 0; }
1596static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1597{ return 0; }
1598
1599
1600static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1601static inline void pci_restore_state(struct pci_dev *dev) { }
1602static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1603{ return 0; }
1604static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1605{ return 0; }
1606static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1607 pm_message_t state)
1608{ return PCI_D0; }
1609static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1610 int enable)
1611{ return 0; }
1612
1613static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1614{ return -EIO; }
1615static inline void pci_release_regions(struct pci_dev *dev) { }
1616
1617static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1618static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1619{ return 0; }
1620static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1621
1622static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1623{ return NULL; }
1624static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1625 unsigned int devfn)
1626{ return NULL; }
1627static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1628 unsigned int devfn)
1629{ return NULL; }
1630
1631static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1632static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1633
1634#define dev_is_pci(d) (false)
1635#define dev_is_pf(d) (false)
1636#define dev_num_vf(d) (0)
1637#endif
1638
1639
1640
1641#include <asm/pci.h>
1642
1643
1644
1645#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1646#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1647#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1648#define pci_resource_len(dev,bar) \
1649 ((pci_resource_start((dev), (bar)) == 0 && \
1650 pci_resource_end((dev), (bar)) == \
1651 pci_resource_start((dev), (bar))) ? 0 : \
1652 \
1653 (pci_resource_end((dev), (bar)) - \
1654 pci_resource_start((dev), (bar)) + 1))
1655
1656
1657
1658
1659
1660static inline void *pci_get_drvdata(struct pci_dev *pdev)
1661{
1662 return dev_get_drvdata(&pdev->dev);
1663}
1664
1665static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1666{
1667 dev_set_drvdata(&pdev->dev, data);
1668}
1669
1670
1671
1672
1673static inline const char *pci_name(const struct pci_dev *pdev)
1674{
1675 return dev_name(&pdev->dev);
1676}
1677
1678
1679
1680
1681
1682#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1683static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1684 const struct resource *rsrc, resource_size_t *start,
1685 resource_size_t *end)
1686{
1687 *start = rsrc->start;
1688 *end = rsrc->end;
1689}
1690#endif
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700struct pci_fixup {
1701 u16 vendor;
1702 u16 device;
1703 u32 class;
1704 unsigned int class_shift;
1705 void (*hook)(struct pci_dev *dev);
1706};
1707
1708enum pci_fixup_pass {
1709 pci_fixup_early,
1710 pci_fixup_header,
1711 pci_fixup_final,
1712 pci_fixup_enable,
1713 pci_fixup_resume,
1714 pci_fixup_suspend,
1715 pci_fixup_resume_early,
1716 pci_fixup_suspend_late,
1717};
1718
1719
1720#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1721 class_shift, hook) \
1722 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1723 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1724 = { vendor, device, class, class_shift, hook };
1725
1726#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1727 class_shift, hook) \
1728 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1729 hook, vendor, device, class, class_shift, hook)
1730#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1731 class_shift, hook) \
1732 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1733 hook, vendor, device, class, class_shift, hook)
1734#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1735 class_shift, hook) \
1736 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1737 hook, vendor, device, class, class_shift, hook)
1738#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1739 class_shift, hook) \
1740 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1741 hook, vendor, device, class, class_shift, hook)
1742#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1743 class_shift, hook) \
1744 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1745 resume##hook, vendor, device, class, \
1746 class_shift, hook)
1747#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1748 class_shift, hook) \
1749 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1750 resume_early##hook, vendor, device, \
1751 class, class_shift, hook)
1752#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1753 class_shift, hook) \
1754 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1755 suspend##hook, vendor, device, class, \
1756 class_shift, hook)
1757#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1758 class_shift, hook) \
1759 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1760 suspend_late##hook, vendor, device, \
1761 class, class_shift, hook)
1762
1763#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1765 hook, vendor, device, PCI_ANY_ID, 0, hook)
1766#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1767 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1768 hook, vendor, device, PCI_ANY_ID, 0, hook)
1769#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1770 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1771 hook, vendor, device, PCI_ANY_ID, 0, hook)
1772#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1773 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1774 hook, vendor, device, PCI_ANY_ID, 0, hook)
1775#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1776 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1777 resume##hook, vendor, device, \
1778 PCI_ANY_ID, 0, hook)
1779#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1780 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1781 resume_early##hook, vendor, device, \
1782 PCI_ANY_ID, 0, hook)
1783#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1784 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1785 suspend##hook, vendor, device, \
1786 PCI_ANY_ID, 0, hook)
1787#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1788 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1789 suspend_late##hook, vendor, device, \
1790 PCI_ANY_ID, 0, hook)
1791
1792#ifdef CONFIG_PCI_QUIRKS
1793void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1794int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1795int pci_dev_specific_enable_acs(struct pci_dev *dev);
1796#else
1797static inline void pci_fixup_device(enum pci_fixup_pass pass,
1798 struct pci_dev *dev) { }
1799static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1800 u16 acs_flags)
1801{
1802 return -ENOTTY;
1803}
1804static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1805{
1806 return -ENOTTY;
1807}
1808#endif
1809
1810void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1811void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1812void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1813int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1814int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1815 const char *name);
1816void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1817
1818extern int pci_pci_problems;
1819#define PCIPCI_FAIL 1
1820#define PCIPCI_TRITON 2
1821#define PCIPCI_NATOMA 4
1822#define PCIPCI_VIAETBF 8
1823#define PCIPCI_VSFX 16
1824#define PCIPCI_ALIMAGIK 32
1825#define PCIAGP_FAIL 64
1826
1827extern unsigned long pci_cardbus_io_size;
1828extern unsigned long pci_cardbus_mem_size;
1829extern u8 pci_dfl_cache_line_size;
1830extern u8 pci_cache_line_size;
1831
1832extern unsigned long pci_hotplug_io_size;
1833extern unsigned long pci_hotplug_mem_size;
1834extern unsigned long pci_hotplug_bus_size;
1835
1836
1837void pcibios_disable_device(struct pci_dev *dev);
1838void pcibios_set_master(struct pci_dev *dev);
1839int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1840 enum pcie_reset_state state);
1841int pcibios_add_device(struct pci_dev *dev);
1842void pcibios_release_device(struct pci_dev *dev);
1843void pcibios_penalize_isa_irq(int irq, int active);
1844int pcibios_alloc_irq(struct pci_dev *dev);
1845void pcibios_free_irq(struct pci_dev *dev);
1846
1847#ifdef CONFIG_HIBERNATE_CALLBACKS
1848extern struct dev_pm_ops pcibios_pm_ops;
1849#endif
1850
1851#ifdef CONFIG_PCI_MMCONFIG
1852void __init pci_mmcfg_early_init(void);
1853void __init pci_mmcfg_late_init(void);
1854#else
1855static inline void pci_mmcfg_early_init(void) { }
1856static inline void pci_mmcfg_late_init(void) { }
1857#endif
1858
1859int pci_ext_cfg_avail(void);
1860
1861void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1862
1863#ifdef CONFIG_PCI_IOV
1864int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1865int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1866
1867int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1868void pci_disable_sriov(struct pci_dev *dev);
1869int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1870void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1871int pci_num_vf(struct pci_dev *dev);
1872int pci_vfs_assigned(struct pci_dev *dev);
1873int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1874int pci_sriov_get_totalvfs(struct pci_dev *dev);
1875int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1876resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1877#else
1878static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1879{
1880 return -ENOSYS;
1881}
1882static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1883{
1884 return -ENOSYS;
1885}
1886static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1887{ return -ENODEV; }
1888static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1889{
1890 return -ENOSYS;
1891}
1892static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1893 int id, int reset) { }
1894static inline void pci_disable_sriov(struct pci_dev *dev) { }
1895static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1896static inline int pci_vfs_assigned(struct pci_dev *dev)
1897{ return 0; }
1898static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1899{ return 0; }
1900static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1901{ return 0; }
1902#define pci_sriov_configure_simple NULL
1903static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1904{ return 0; }
1905#endif
1906
1907#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1908void pci_hp_create_module_link(struct pci_slot *pci_slot);
1909void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1910#endif
1911
1912extern int pci_pcie_cap(struct pci_dev *dev);
1913extern bool pci_is_pcie(struct pci_dev *dev);
1914
1915
1916
1917
1918
1919static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1920{
1921 return dev->pcie_flags_reg;
1922}
1923
1924int pci_pcie_type(const struct pci_dev *dev);
1925static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1926{
1927 while (1) {
1928 if (!pci_is_pcie(dev))
1929 break;
1930 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1931 return dev;
1932 if (!dev->bus->self)
1933 break;
1934 dev = dev->bus->self;
1935 }
1936 return NULL;
1937}
1938
1939void pci_request_acs(void);
1940bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1941bool pci_acs_path_enabled(struct pci_dev *start,
1942 struct pci_dev *end, u16 acs_flags);
1943int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
1944
1945#define PCI_VPD_LRDT 0x80
1946#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1947
1948
1949#define PCI_VPD_LTIN_ID_STRING 0x02
1950#define PCI_VPD_LTIN_RO_DATA 0x10
1951#define PCI_VPD_LTIN_RW_DATA 0x11
1952
1953#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1954#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1955#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1956
1957
1958#define PCI_VPD_STIN_END 0x0f
1959
1960#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1961
1962#define PCI_VPD_SRDT_TIN_MASK 0x78
1963#define PCI_VPD_SRDT_LEN_MASK 0x07
1964#define PCI_VPD_LRDT_TIN_MASK 0x7f
1965
1966#define PCI_VPD_LRDT_TAG_SIZE 3
1967#define PCI_VPD_SRDT_TAG_SIZE 1
1968
1969#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1970
1971#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1972#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1973#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1974#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1975
1976
1977
1978
1979
1980
1981
1982static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1983{
1984 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1985}
1986
1987
1988
1989
1990
1991
1992
1993static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1994{
1995 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1996}
1997
1998
1999
2000
2001
2002
2003
2004static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2005{
2006 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2007}
2008
2009
2010
2011
2012
2013
2014
2015static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2016{
2017 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2018}
2019
2020
2021
2022
2023
2024
2025
2026static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2027{
2028 return info_field[2];
2029}
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2054 unsigned int len, const char *kw);
2055
2056
2057#ifdef CONFIG_OF
2058struct device_node;
2059void pci_set_of_node(struct pci_dev *dev);
2060void pci_release_of_node(struct pci_dev *dev);
2061void pci_set_bus_of_node(struct pci_bus *bus);
2062void pci_release_bus_of_node(struct pci_bus *bus);
2063
2064
2065struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2066
2067static inline struct device_node *
2068pci_device_to_OF_node(const struct pci_dev *pdev)
2069{
2070 return pdev ? pdev->dev.of_node : NULL;
2071}
2072
2073static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2074{
2075 return bus ? bus->dev.of_node : NULL;
2076}
2077
2078#else
2079static inline void pci_set_of_node(struct pci_dev *dev) { }
2080static inline void pci_release_of_node(struct pci_dev *dev) { }
2081static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2082static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2083static inline struct device_node *
2084pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2085#endif
2086
2087#ifdef CONFIG_EEH
2088static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2089{
2090 return pdev->dev.archdata.edev;
2091}
2092#endif
2093
2094void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2095bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2096int pci_for_each_dma_alias(struct pci_dev *pdev,
2097 int (*fn)(struct pci_dev *pdev,
2098 u16 alias, void *data), void *data);
2099
2100
2101static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2102{
2103 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2104}
2105static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2106{
2107 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2108}
2109static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2110{
2111 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2112}
2113
2114
2115
2116
2117
2118
2119
2120static inline bool pci_ari_enabled(struct pci_bus *bus)
2121{
2122 return bus->self && bus->self->ari_enabled;
2123}
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2134{
2135 struct pci_dev *parent = pdev;
2136
2137 if (pdev->is_thunderbolt)
2138 return true;
2139
2140 while ((parent = pci_upstream_bridge(parent)))
2141 if (parent->is_thunderbolt)
2142 return true;
2143
2144 return false;
2145}
2146
2147
2148#include <linux/pci-dma-compat.h>
2149
2150#define pci_printk(level, pdev, fmt, arg...) \
2151 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2152
2153#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2154#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2155#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2156#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2157#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2158#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2159#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2160#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2161
2162#endif
2163