LXR linux/arch/blackfin/include/asm/bfin

   1/*
   2 * bfin_crc.h - interface to Blackfin CRC controllers
   3 *
   4 * Copyright 2012 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef __BFIN_CRC_H__
  10#define __BFIN_CRC_H__
  11
  12/* Function driver which use hardware crc must initialize the structure */
  13struct crc_info {
  14        /* Input data address */
  15        unsigned char *in_addr;
  16        /* Output data address */
  17        unsigned char *out_addr;
  18        /* Input or output bytes */
  19        unsigned long datasize;
  20        union {
  21        /* CRC to compare with that of input buffer */
  22        unsigned long crc_compare;
  23        /* Value to compare with input data */
  24        unsigned long val_verify;
  25        /* Value to fill */
  26        unsigned long val_fill;
  27        };
  28        /* Value to program the 32b CRC Polynomial */
  29        unsigned long crc_poly;
  30        union {
  31        /* CRC calculated from the input data */
  32        unsigned long crc_result;
  33        /* First failed position to verify input data */
  34        unsigned long pos_verify;
  35        };
  36        /* CRC mirror flags */
  37        unsigned int bitmirr:1;
  38        unsigned int bytmirr:1;
  39        unsigned int w16swp:1;
  40        unsigned int fdsel:1;
  41        unsigned int rsltmirr:1;
  42        unsigned int polymirr:1;
  43        unsigned int cmpmirr:1;
  44};
  45
  46/* Userspace interface */
  47#define CRC_IOC_MAGIC           'C'
  48#define CRC_IOC_CALC_CRC        _IOWR('C', 0x01, unsigned int)
  49#define CRC_IOC_MEMCPY_CRC      _IOWR('C', 0x02, unsigned int)
  50#define CRC_IOC_VERIFY_VAL      _IOWR('C', 0x03, unsigned int)
  51#define CRC_IOC_FILL_VAL        _IOWR('C', 0x04, unsigned int)
  52
  53
  54#ifdef __KERNEL__
  55
  56#include <linux/types.h>
  57#include <linux/spinlock.h>
  58#include <linux/miscdevice.h>
  59
  60struct crc_register {
  61        u32 control;
  62        u32 datacnt;
  63        u32 datacntrld;
  64        u32 __pad_1[2];
  65        u32 compare;
  66        u32 fillval;
  67        u32 datafifo;
  68        u32 intren;
  69        u32 intrenset;
  70        u32 intrenclr;
  71        u32 poly;
  72        u32 __pad_2[4];
  73        u32 status;
  74        u32 datacntcap;
  75        u32 __pad_3;
  76        u32 result;
  77        u32 curresult;
  78        u32 __pad_4[3];
  79        u32 revid;
  80};
  81
  82/* CRC_STATUS Masks */
  83#define CMPERR                  0x00000002      /* Compare error */
  84#define DCNTEXP                 0x00000010      /* datacnt register expired */
  85#define IBR                     0x00010000      /* Input buffer ready */
  86#define OBR                     0x00020000      /* Output buffer ready */
  87#define IRR                     0x00040000      /* Immediate result readt */
  88#define LUTDONE                 0x00080000      /* Look-up table generation done */
  89#define FSTAT                   0x00700000      /* FIFO status */
  90#define MAX_FIFO                4               /* Max fifo size */
  91
  92/* CRC_CONTROL Masks */
  93#define BLKEN                   0x00000001      /* Block enable */
  94#define OPMODE                  0x000000F0      /* Operation mode */
  95#define OPMODE_OFFSET           4               /* Operation mode mask offset*/
  96#define MODE_DMACPY_CRC         1               /* MTM CRC compute and compare */
  97#define MODE_DATA_FILL          2               /* MTM data fill */
  98#define MODE_CALC_CRC           3               /* MSM CRC compute and compare */
  99#define MODE_DATA_VERIFY        4               /* MSM data verify */
 100#define AUTOCLRZ                0x00000100      /* Auto clear to zero */
 101#define AUTOCLRF                0x00000200      /* Auto clear to one */
 102#define OBRSTALL                0x00001000      /* Stall on output buffer ready */
 103#define IRRSTALL                0x00002000      /* Stall on immediate result ready */
 104#define BITMIRR                 0x00010000      /* Mirror bits within each byte of 32-bit input data */
 105#define BITMIRR_OFFSET          16              /* Mirror bits offset */
 106#define BYTMIRR                 0x00020000      /* Mirror bytes of 32-bit input data */
 107#define BYTMIRR_OFFSET          17              /* Mirror bytes offset */
 108#define W16SWP                  0x00040000      /* Mirror uppper and lower 16-bit word of 32-bit input data */
 109#define W16SWP_OFFSET           18              /* Mirror 16-bit word offset */
 110#define FDSEL                   0x00080000      /* FIFO is written after input data is mirrored */
 111#define FDSEL_OFFSET            19              /* Mirror FIFO offset */
 112#define RSLTMIRR                0x00100000      /* CRC result registers are mirrored. */
 113#define RSLTMIRR_OFFSET         20              /* Mirror CRC result offset. */
 114#define POLYMIRR                0x00200000      /* CRC poly register is mirrored. */
 115#define POLYMIRR_OFFSET         21              /* Mirror CRC poly offset. */
 116#define CMPMIRR                 0x00400000      /* CRC compare register is mirrored. */
 117#define CMPMIRR_OFFSET          22              /* Mirror CRC compare offset. */
 118
 119/* CRC_INTREN Masks */
 120#define CMPERRI                 0x02            /* CRC_ERROR_INTR */
 121#define DCNTEXPI                0x10            /* CRC_STATUS_INTR */
 122
 123#endif
 124
 125#endif
 126