1/* 2 * bfin_dma.h - Blackfin DMA defines/structures/etc... 3 * 4 * Copyright 2004-2010 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#ifndef __ASM_BFIN_DMA_H__ 10#define __ASM_BFIN_DMA_H__ 11 12#include <linux/types.h> 13 14/* DMA_CONFIG Masks */ 15#define DMAEN 0x0001 /* DMA Channel Enable */ 16#define WNR 0x0002 /* Channel Direction (W/R*) */ 17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 18#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ 19 20#ifdef CONFIG_BF60x 21 22#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ 23#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ 24#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ 25#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ 26#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ 27#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ 28#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ 29#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ 30#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ 31#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ 32#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ 33#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ 34#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ 35#define DI_EN DI_EN_X /* Data Interrupt Enable */ 36#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */ 37#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */ 38#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */ 39#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */ 40#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */ 41#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */ 42#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */ 43#define NDSIZE 0x00070000 /* Next Descriptor Size */ 44#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ 45#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ 46#define DMAFLOW_LARGE DMAFLOW_LIST 47#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ 48#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ 49#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ 50#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ 51#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ 52#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ 53#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ 54 55#else 56 57#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ 58#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ 59#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 60#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 61#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 62#define RESTART 0x0020 /* DMA Buffer Clear */ 63#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 64#define DI_EN 0x0080 /* Data Interrupt Enable */ 65#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ 66#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ 67#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 68#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 69#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 70#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 71#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 72#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 73#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 74#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 75#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 76#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 77#define NDSIZE 0x0f00 /* Next Descriptor Size */ 78#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ 79#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 80#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 81#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 82#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 83#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 84 85#endif 86#define DMAFLOW 0x7000 /* Flow Control */ 87#define DMAFLOW_STOP 0x0000 /* Stop Mode */ 88#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ 89 90/* DMA_IRQ_STATUS Masks */ 91#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 92#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 93#ifdef CONFIG_BF60x 94#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */ 95#else 96#define DMA_PIRQ 0 97#endif 98 99/* 100 * All Blackfin system MMRs are padded to 32bits even if the register 101 * itself is only 16bits. So use a helper macro to streamline this. 102 */ 103#define __BFP(m) u16 m; u16 __pad_##m 104 105/* 106 * bfin dma registers layout 107 */ 108struct bfin_dma_regs { 109 u32 next_desc_ptr; 110 u32 start_addr; 111#ifdef CONFIG_BF60x 112 u32 cfg; 113 u32 x_count; 114 u32 x_modify; 115 u32 y_count; 116 u32 y_modify; 117 u32 pad1; 118 u32 pad2; 119 u32 curr_desc_ptr; 120 u32 prev_desc_ptr; 121 u32 curr_addr; 122 u32 irq_status; 123 u32 curr_x_count; 124 u32 curr_y_count; 125 u32 pad3; 126 u32 bw_limit_count; 127 u32 curr_bw_limit_count; 128 u32 bw_monitor_count; 129 u32 curr_bw_monitor_count; 130#else 131 __BFP(config); 132 u32 __pad0; 133 __BFP(x_count); 134 __BFP(x_modify); 135 __BFP(y_count); 136 __BFP(y_modify); 137 u32 curr_desc_ptr; 138 u32 curr_addr; 139 __BFP(irq_status); 140 __BFP(peripheral_map); 141 __BFP(curr_x_count); 142 u32 __pad1; 143 __BFP(curr_y_count); 144 u32 __pad2; 145#endif 146}; 147 148#ifndef CONFIG_BF60x 149/* 150 * bfin handshake mdma registers layout 151 */ 152struct bfin_hmdma_regs { 153 __BFP(control); 154 __BFP(ecinit); 155 __BFP(bcinit); 156 __BFP(ecurgent); 157 __BFP(ecoverflow); 158 __BFP(ecount); 159 __BFP(bcount); 160}; 161#endif 162 163#undef __BFP 164 165#endif 166