1#ifndef __strmux_defs_h
2#define __strmux_defs_h
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17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
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87
88typedef struct {
89 unsigned int dma0 : 3;
90 unsigned int dma1 : 3;
91 unsigned int dma2 : 3;
92 unsigned int dma3 : 3;
93 unsigned int dma4 : 3;
94 unsigned int dma5 : 3;
95 unsigned int dma6 : 3;
96 unsigned int dma7 : 3;
97 unsigned int dma8 : 3;
98 unsigned int dma9 : 3;
99 unsigned int dummy1 : 2;
100} reg_strmux_rw_cfg;
101#define REG_RD_ADDR_strmux_rw_cfg 0
102#define REG_WR_ADDR_strmux_rw_cfg 0
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104
105
106enum {
107 regk_strmux_ata = 0x00000003,
108 regk_strmux_eth0 = 0x00000001,
109 regk_strmux_eth1 = 0x00000004,
110 regk_strmux_ext0 = 0x00000001,
111 regk_strmux_ext1 = 0x00000001,
112 regk_strmux_ext2 = 0x00000001,
113 regk_strmux_ext3 = 0x00000001,
114 regk_strmux_iop0 = 0x00000002,
115 regk_strmux_iop1 = 0x00000001,
116 regk_strmux_off = 0x00000000,
117 regk_strmux_p21 = 0x00000004,
118 regk_strmux_rw_cfg_default = 0x00000000,
119 regk_strmux_ser0 = 0x00000002,
120 regk_strmux_ser1 = 0x00000002,
121 regk_strmux_ser2 = 0x00000004,
122 regk_strmux_ser3 = 0x00000003,
123 regk_strmux_sser0 = 0x00000003,
124 regk_strmux_sser1 = 0x00000003,
125 regk_strmux_strcop = 0x00000002
126};
127#endif
128