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10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/slab.h>
21#include <linux/cpu.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/pci.h>
25#include <linux/kdebug.h>
26#include <linux/delay.h>
27#include <linux/crash_dump.h>
28#include <linux/memory.h>
29
30#include <asm/uv/uv_mmrs.h>
31#include <asm/uv/uv_hub.h>
32#include <asm/current.h>
33#include <asm/pgtable.h>
34#include <asm/uv/bios.h>
35#include <asm/uv/uv.h>
36#include <asm/apic.h>
37#include <asm/ipi.h>
38#include <asm/smp.h>
39#include <asm/x86_init.h>
40#include <asm/emergency-restart.h>
41#include <asm/nmi.h>
42
43DEFINE_PER_CPU(int, x2apic_extra_bits);
44
45#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
46
47static enum uv_system_type uv_system_type;
48static bool uv_hubless_system;
49static u64 gru_start_paddr, gru_end_paddr;
50static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
51static u64 gru_dist_lmask, gru_dist_umask;
52static union uvh_apicid uvh_apicid;
53
54
55static struct {
56 unsigned int apicid_shift;
57 unsigned int apicid_mask;
58 unsigned int socketid_shift;
59 unsigned int pnode_mask;
60 unsigned int gpa_shift;
61 unsigned int gnode_shift;
62} uv_cpuid;
63
64int uv_min_hub_revision_id;
65EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
66unsigned int uv_apicid_hibits;
67EXPORT_SYMBOL_GPL(uv_apicid_hibits);
68
69static struct apic apic_x2apic_uv_x;
70static struct uv_hub_info_s uv_hub_info_node0;
71
72
73static int disable_uv_undefined_panic = 1;
74unsigned long uv_undefined(char *str)
75{
76 if (likely(!disable_uv_undefined_panic))
77 panic("UV: error: undefined MMR: %s\n", str);
78 else
79 pr_crit("UV: error: undefined MMR: %s\n", str);
80 return ~0ul;
81}
82EXPORT_SYMBOL(uv_undefined);
83
84static unsigned long __init uv_early_read_mmr(unsigned long addr)
85{
86 unsigned long val, *mmr;
87
88 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
89 val = *mmr;
90 early_iounmap(mmr, sizeof(*mmr));
91 return val;
92}
93
94static inline bool is_GRU_range(u64 start, u64 end)
95{
96 if (gru_dist_base) {
97 u64 su = start & gru_dist_umask;
98 u64 sl = start & gru_dist_lmask;
99 u64 eu = end & gru_dist_umask;
100 u64 el = end & gru_dist_lmask;
101
102
103 return (sl == gru_dist_base && el == gru_dist_base &&
104 su >= gru_first_node_paddr &&
105 su <= gru_last_node_paddr &&
106 eu == su);
107 } else {
108 return start >= gru_start_paddr && end <= gru_end_paddr;
109 }
110}
111
112static bool uv_is_untracked_pat_range(u64 start, u64 end)
113{
114 return is_ISA_range(start, end) || is_GRU_range(start, end);
115}
116
117static int __init early_get_pnodeid(void)
118{
119 union uvh_node_id_u node_id;
120 union uvh_rh_gam_config_mmr_u m_n_config;
121 int pnode;
122
123
124 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
125 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
126 uv_min_hub_revision_id = node_id.s.revision;
127
128 switch (node_id.s.part_number) {
129 case UV2_HUB_PART_NUMBER:
130 case UV2_HUB_PART_NUMBER_X:
131 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
132 break;
133 case UV3_HUB_PART_NUMBER:
134 case UV3_HUB_PART_NUMBER_X:
135 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
136 break;
137
138
139 case UV4_HUB_PART_NUMBER:
140 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
141 uv_cpuid.gnode_shift = 2;
142 break;
143 }
144
145 uv_hub_info->hub_revision = uv_min_hub_revision_id;
146 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
147 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
148 uv_cpuid.gpa_shift = 46;
149
150 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
151 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
152 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
153 return pnode;
154}
155
156static void __init uv_tsc_check_sync(void)
157{
158 u64 mmr;
159 int sync_state;
160 int mmr_shift;
161 char *state;
162 bool valid;
163
164
165 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
166 mmr_shift =
167 is_uv1_hub() ? 0 :
168 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
169 if (mmr_shift)
170 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
171 else
172 sync_state = 0;
173
174 switch (sync_state) {
175 case UVH_TSC_SYNC_VALID:
176 state = "in sync";
177 valid = true;
178 break;
179
180 case UVH_TSC_SYNC_INVALID:
181 state = "unstable";
182 valid = false;
183 break;
184 default:
185 state = "unknown: assuming valid";
186 valid = true;
187 break;
188 }
189 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
190
191
192 if (valid)
193 mark_tsc_async_resets("UV BIOS");
194 else
195 mark_tsc_unstable("UV BIOS");
196}
197
198
199#define SMT_LEVEL 0
200#define INVALID_TYPE 0
201#define SMT_TYPE 1
202#define CORE_TYPE 2
203#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
204#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
205
206static void set_x2apic_bits(void)
207{
208 unsigned int eax, ebx, ecx, edx, sub_index;
209 unsigned int sid_shift;
210
211 cpuid(0, &eax, &ebx, &ecx, &edx);
212 if (eax < 0xb) {
213 pr_info("UV: CPU does not have CPUID.11\n");
214 return;
215 }
216 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
217 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
218 pr_info("UV: CPUID.11 not implemented\n");
219 return;
220 }
221 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
222 sub_index = 1;
223 do {
224 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
225 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
226 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
227 break;
228 }
229 sub_index++;
230 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
231 uv_cpuid.apicid_shift = 0;
232 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
233 uv_cpuid.socketid_shift = sid_shift;
234}
235
236static void __init early_get_apic_socketid_shift(void)
237{
238 if (is_uv2_hub() || is_uv3_hub())
239 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
240
241 set_x2apic_bits();
242
243 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
244 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
245 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
246 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
247}
248
249
250
251
252
253
254static void __init uv_set_apicid_hibit(void)
255{
256 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
257
258 if (is_uv1_hub()) {
259 apicid_mask.v =
260 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
261 uv_apicid_hibits =
262 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
263 }
264}
265
266static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
267{
268 int pnodeid;
269 int uv_apic;
270
271 if (strncmp(oem_id, "SGI", 3) != 0) {
272 if (strncmp(oem_id, "NSGI", 4) == 0) {
273 uv_hubless_system = true;
274 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
275 oem_id, oem_table_id);
276 }
277 return 0;
278 }
279
280 if (numa_off) {
281 pr_err("UV: NUMA is off, disabling UV support\n");
282 return 0;
283 }
284
285
286 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
287
288
289
290
291
292
293
294
295 uv_hub_info->hub_revision =
296 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
297 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
298 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
299 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
300
301 if (uv_hub_info->hub_revision == 0)
302 goto badbios;
303
304 pnodeid = early_get_pnodeid();
305 early_get_apic_socketid_shift();
306 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
307 x86_platform.nmi_init = uv_nmi_init;
308
309 if (!strcmp(oem_table_id, "UVX")) {
310 uv_system_type = UV_X2APIC;
311 uv_apic = 0;
312
313 } else if (!strcmp(oem_table_id, "UVH")) {
314 uv_system_type = UV_NON_UNIQUE_APIC;
315 __this_cpu_write(x2apic_extra_bits,
316 pnodeid << uvh_apicid.s.pnode_shift);
317 uv_set_apicid_hibit();
318 uv_apic = 1;
319
320 } else if (!strcmp(oem_table_id, "UVL")) {
321 uv_system_type = UV_LEGACY_APIC;
322 uv_apic = 0;
323
324 } else {
325 goto badbios;
326 }
327
328 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
329 oem_id, oem_table_id, uv_system_type,
330 uv_min_hub_revision_id, uv_apic);
331 uv_tsc_check_sync();
332
333 return uv_apic;
334
335badbios:
336 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
337 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
338 BUG();
339}
340
341enum uv_system_type get_uv_system_type(void)
342{
343 return uv_system_type;
344}
345
346int is_uv_system(void)
347{
348 return uv_system_type != UV_NONE;
349}
350EXPORT_SYMBOL_GPL(is_uv_system);
351
352int is_uv_hubless(void)
353{
354 return uv_hubless_system;
355}
356EXPORT_SYMBOL_GPL(is_uv_hubless);
357
358void **__uv_hub_info_list;
359EXPORT_SYMBOL_GPL(__uv_hub_info_list);
360
361DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
362EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
363
364short uv_possible_blades;
365EXPORT_SYMBOL_GPL(uv_possible_blades);
366
367unsigned long sn_rtc_cycles_per_second;
368EXPORT_SYMBOL(sn_rtc_cycles_per_second);
369
370
371static __initdata unsigned short *_node_to_pnode;
372static __initdata unsigned short _min_socket, _max_socket;
373static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
374static __initdata struct uv_gam_range_entry *uv_gre_table;
375static __initdata struct uv_gam_parameters *uv_gp_table;
376static __initdata unsigned short *_socket_to_node;
377static __initdata unsigned short *_socket_to_pnode;
378static __initdata unsigned short *_pnode_to_socket;
379static __initdata struct uv_gam_range_s *_gr_table;
380#define SOCK_EMPTY ((unsigned short)~0)
381
382extern int uv_hub_info_version(void)
383{
384 return UV_HUB_INFO_VERSION;
385}
386EXPORT_SYMBOL(uv_hub_info_version);
387
388
389static unsigned long mem_block_size = (2UL << 30);
390
391
392static int parse_mem_block_size(char *ptr)
393{
394 unsigned long size = memparse(ptr, NULL);
395
396
397 mem_block_size = size;
398 return 0;
399}
400early_param("uv_memblksize", parse_mem_block_size);
401
402static __init int adj_blksize(u32 lgre)
403{
404 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
405 unsigned long size;
406
407 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
408 if (IS_ALIGNED(base, size))
409 break;
410
411 if (size >= mem_block_size)
412 return 0;
413
414 mem_block_size = size;
415 return 1;
416}
417
418static __init void set_block_size(void)
419{
420 unsigned int order = ffs(mem_block_size);
421
422 if (order) {
423
424 set_memory_block_size_order(order - 1);
425 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
426 } else {
427
428 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
429 set_memory_block_size_order(31);
430 }
431}
432
433
434static __init void build_uv_gr_table(void)
435{
436 struct uv_gam_range_entry *gre = uv_gre_table;
437 struct uv_gam_range_s *grt;
438 unsigned long last_limit = 0, ram_limit = 0;
439 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
440
441 if (!gre)
442 return;
443
444 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
445 grt = kzalloc(bytes, GFP_KERNEL);
446 BUG_ON(!grt);
447 _gr_table = grt;
448
449 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
450 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
451 if (!ram_limit) {
452 ram_limit = last_limit;
453 last_limit = gre->limit;
454 lsid++;
455 continue;
456 }
457 last_limit = gre->limit;
458 pr_info("UV: extra hole in GAM RE table @%d\n",
459 (int)(gre - uv_gre_table));
460 continue;
461 }
462 if (_max_socket < gre->sockid) {
463 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
464 gre->sockid, _max_socket,
465 (int)(gre - uv_gre_table));
466 continue;
467 }
468 sid = gre->sockid - _min_socket;
469 if (lsid < sid) {
470 grt = &_gr_table[indx];
471 grt->base = lindx;
472 grt->nasid = gre->nasid;
473 grt->limit = last_limit = gre->limit;
474 lsid = sid;
475 lindx = indx++;
476 continue;
477 }
478 if (lsid == sid && !ram_limit) {
479 if (grt->limit == last_limit) {
480 grt->limit = last_limit = gre->limit;
481 continue;
482 }
483 }
484 if (!ram_limit) {
485 grt++;
486 grt->base = lindx;
487 grt->nasid = gre->nasid;
488 grt->limit = last_limit = gre->limit;
489 continue;
490 }
491 grt++;
492 grt->base = grt - _gr_table;
493 grt->nasid = gre->nasid;
494 grt->limit = last_limit = gre->limit;
495 lsid++;
496 }
497
498
499 grt++;
500 i = grt - _gr_table;
501 if (i < _gr_table_len) {
502 void *ret;
503
504 bytes = i * sizeof(struct uv_gam_range_s);
505 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
506 if (ret) {
507 _gr_table = ret;
508 _gr_table_len = i;
509 }
510 }
511
512
513 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
514 int gb = grt->base;
515 unsigned long start = gb < 0 ? 0 :
516 (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
517 unsigned long end =
518 (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
519
520 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
521 i, grt->nasid, start, end, gb);
522 }
523}
524
525static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
526{
527#ifdef CONFIG_SMP
528 unsigned long val;
529 int pnode;
530
531 pnode = uv_apicid_to_pnode(phys_apicid);
532 phys_apicid |= uv_apicid_hibits;
533 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
534 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
535 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
536 APIC_DM_INIT;
537 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
538
539 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
540 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
541 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
542 APIC_DM_STARTUP;
543 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
544
545 atomic_set(&init_deasserted, 1);
546#endif
547 return 0;
548}
549
550static void uv_send_IPI_one(int cpu, int vector)
551{
552 unsigned long apicid;
553 int pnode;
554
555 apicid = per_cpu(x86_cpu_to_apicid, cpu);
556 pnode = uv_apicid_to_pnode(apicid);
557 uv_hub_send_ipi(pnode, apicid, vector);
558}
559
560static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
561{
562 unsigned int cpu;
563
564 for_each_cpu(cpu, mask)
565 uv_send_IPI_one(cpu, vector);
566}
567
568static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
569{
570 unsigned int this_cpu = smp_processor_id();
571 unsigned int cpu;
572
573 for_each_cpu(cpu, mask) {
574 if (cpu != this_cpu)
575 uv_send_IPI_one(cpu, vector);
576 }
577}
578
579static void uv_send_IPI_allbutself(int vector)
580{
581 unsigned int this_cpu = smp_processor_id();
582 unsigned int cpu;
583
584 for_each_online_cpu(cpu) {
585 if (cpu != this_cpu)
586 uv_send_IPI_one(cpu, vector);
587 }
588}
589
590static void uv_send_IPI_all(int vector)
591{
592 uv_send_IPI_mask(cpu_online_mask, vector);
593}
594
595static int uv_apic_id_valid(int apicid)
596{
597 return 1;
598}
599
600static int uv_apic_id_registered(void)
601{
602 return 1;
603}
604
605static void uv_init_apic_ldr(void)
606{
607}
608
609static int
610uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
611 const struct cpumask *andmask,
612 unsigned int *apicid)
613{
614 int unsigned cpu;
615
616
617
618
619
620 for_each_cpu_and(cpu, cpumask, andmask) {
621 if (cpumask_test_cpu(cpu, cpu_online_mask))
622 break;
623 }
624
625 if (likely(cpu < nr_cpu_ids)) {
626 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
627 return 0;
628 }
629
630 return -EINVAL;
631}
632
633static unsigned int x2apic_get_apic_id(unsigned long x)
634{
635 unsigned int id;
636
637 WARN_ON(preemptible() && num_online_cpus() > 1);
638 id = x | __this_cpu_read(x2apic_extra_bits);
639
640 return id;
641}
642
643static unsigned long set_apic_id(unsigned int id)
644{
645 unsigned long x;
646
647
648 x = id;
649 return x;
650}
651
652static unsigned int uv_read_apic_id(void)
653{
654 return x2apic_get_apic_id(apic_read(APIC_ID));
655}
656
657static int uv_phys_pkg_id(int initial_apicid, int index_msb)
658{
659 return uv_read_apic_id() >> index_msb;
660}
661
662static void uv_send_IPI_self(int vector)
663{
664 apic_write(APIC_SELF_IPI, vector);
665}
666
667static int uv_probe(void)
668{
669 return apic == &apic_x2apic_uv_x;
670}
671
672static struct apic __refdata apic_x2apic_uv_x = {
673
674 .name = "UV large system",
675 .probe = uv_probe,
676 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
677 .apic_id_valid = uv_apic_id_valid,
678 .apic_id_registered = uv_apic_id_registered,
679
680 .irq_delivery_mode = dest_Fixed,
681 .irq_dest_mode = 0,
682
683 .target_cpus = online_target_cpus,
684 .disable_esr = 0,
685 .dest_logical = APIC_DEST_LOGICAL,
686 .check_apicid_used = NULL,
687 .check_apicid_present = NULL,
688
689 .vector_allocation_domain = default_vector_allocation_domain,
690 .init_apic_ldr = uv_init_apic_ldr,
691
692 .ioapic_phys_id_map = NULL,
693 .setup_apic_routing = NULL,
694 .multi_timer_check = NULL,
695 .cpu_present_to_apicid = default_cpu_present_to_apicid,
696 .apicid_to_cpu_present = NULL,
697 .setup_portio_remap = NULL,
698 .check_phys_apicid_present = default_check_phys_apicid_present,
699 .enable_apic_mode = NULL,
700 .phys_pkg_id = uv_phys_pkg_id,
701 .mps_oem_check = NULL,
702
703 .get_apic_id = x2apic_get_apic_id,
704 .set_apic_id = set_apic_id,
705 .apic_id_mask = 0xFFFFFFFFu,
706
707 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
708
709 .send_IPI_mask = uv_send_IPI_mask,
710 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
711 .send_IPI_allbutself = uv_send_IPI_allbutself,
712 .send_IPI_all = uv_send_IPI_all,
713 .send_IPI_self = uv_send_IPI_self,
714
715 .wakeup_secondary_cpu = uv_wakeup_secondary,
716 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
717 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
718 .wait_for_init_deassert = NULL,
719 .smp_callin_clear_local_apic = NULL,
720 .inquire_remote_apic = NULL,
721
722 .read = native_apic_msr_read,
723 .write = native_apic_msr_write,
724 .eoi_write = native_apic_msr_eoi_write,
725 .icr_read = native_x2apic_icr_read,
726 .icr_write = native_x2apic_icr_write,
727 .wait_icr_idle = native_x2apic_wait_icr_idle,
728 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
729};
730
731static void set_x2apic_extra_bits(int pnode)
732{
733 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
734}
735
736#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
737#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
738
739static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
740{
741 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
742 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
743 unsigned long m_redirect;
744 unsigned long m_overlay;
745 int i;
746
747 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
748 switch (i) {
749 case 0:
750 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
751 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
752 break;
753 case 1:
754 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
755 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
756 break;
757 case 2:
758 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
759 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
760 break;
761 }
762 alias.v = uv_read_local_mmr(m_overlay);
763 if (alias.s.enable && alias.s.base == 0) {
764 *size = (1UL << alias.s.m_alias);
765 redirect.v = uv_read_local_mmr(m_redirect);
766 *base = (unsigned long)redirect.s.dest_base
767 << DEST_SHIFT;
768 return;
769 }
770 }
771 *base = *size = 0;
772}
773
774enum map_type {map_wb, map_uc};
775
776static __init void map_high(char *id, unsigned long base, int pshift,
777 int bshift, int max_pnode, enum map_type map_type)
778{
779 unsigned long bytes, paddr;
780
781 paddr = base << pshift;
782 bytes = (1UL << bshift) * (max_pnode + 1);
783 if (!paddr) {
784 pr_info("UV: Map %s_HI base address NULL\n", id);
785 return;
786 }
787 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
788 if (map_type == map_uc)
789 init_extra_mapping_uc(paddr, bytes);
790 else
791 init_extra_mapping_wb(paddr, bytes);
792}
793
794static __init void map_gru_distributed(unsigned long c)
795{
796 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
797 u64 paddr;
798 unsigned long bytes;
799 int nid;
800
801 gru.v = c;
802
803 gru_dist_base = gru.v & 0x000007fff0000000UL;
804 if (!gru_dist_base) {
805 pr_info("UV: Map GRU_DIST base address NULL\n");
806 return;
807 }
808 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
809 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
810 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
811 gru_dist_base &= gru_dist_lmask;
812 for_each_online_node(nid) {
813 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
814 gru_dist_base;
815 init_extra_mapping_wb(paddr, bytes);
816 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
817 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
818 }
819
820 gru_first_node_paddr &= gru_dist_umask;
821 gru_last_node_paddr &= gru_dist_umask;
822 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
823 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
824}
825
826static __init void map_gru_high(int max_pnode)
827{
828 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
829 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
830 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
831 unsigned long base;
832
833 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
834 if (!gru.s.enable) {
835 pr_info("UV: GRU disabled\n");
836 return;
837 }
838
839
840 if (is_uv3_hub() && gru.s3.mode) {
841 map_gru_distributed(gru.v);
842 return;
843 }
844 base = (gru.v & mask) >> shift;
845 map_high("GRU", base, shift, shift, max_pnode, map_wb);
846 gru_start_paddr = ((u64)base << shift);
847 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
848}
849
850static __init void map_mmr_high(int max_pnode)
851{
852 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
853 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
854
855 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
856 if (mmr.s.enable)
857 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
858 else
859 pr_info("UV: MMR disabled\n");
860}
861
862
863static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
864{
865 unsigned long overlay;
866 unsigned long mmr;
867 unsigned long base;
868 unsigned long nasid_mask;
869 unsigned long m_overlay;
870 int i, n, shift, m_io, max_io;
871 int nasid, lnasid, fi, li;
872 char *id;
873
874 if (index == 0) {
875 id = "MMIOH0";
876 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
877 overlay = uv_read_local_mmr(m_overlay);
878 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
879 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
880 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
881 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
882 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
883 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
884 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
885 } else {
886 id = "MMIOH1";
887 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
888 overlay = uv_read_local_mmr(m_overlay);
889 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
890 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
891 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
892 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
893 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
894 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
895 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
896 }
897 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
898 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
899 pr_info("UV: %s disabled\n", id);
900 return;
901 }
902
903 min_pnode *= 2;
904 max_pnode *= 2;
905 max_io = lnasid = fi = li = -1;
906
907 for (i = 0; i < n; i++) {
908 unsigned long m_redirect = mmr + i * 8;
909 unsigned long redirect = uv_read_local_mmr(m_redirect);
910
911 nasid = redirect & nasid_mask;
912 if (i == 0)
913 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
914 id, redirect, m_redirect, nasid);
915
916 if (nasid < min_pnode || max_pnode < nasid)
917 nasid = -1;
918
919 if (nasid == lnasid) {
920 li = i;
921 if (i != n-1)
922 continue;
923 }
924
925
926 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
927 unsigned long addr1, addr2;
928 int f, l;
929
930 if (lnasid == -1) {
931 f = l = i;
932 lnasid = nasid;
933 } else {
934 f = fi;
935 l = li;
936 }
937 addr1 = (base << shift) +
938 f * (unsigned long)(1 << m_io);
939 addr2 = (base << shift) +
940 (l + 1) * (unsigned long)(1 << m_io);
941 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
942 id, fi, li, lnasid, addr1, addr2);
943 if (max_io < l)
944 max_io = l;
945 }
946 fi = li = i;
947 lnasid = nasid;
948 }
949
950 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
951 id, base, shift, m_io, max_io);
952
953 if (max_io >= 0)
954 map_high(id, base, shift, m_io, max_io, map_uc);
955}
956
957static __init void map_mmioh_high(int min_pnode, int max_pnode)
958{
959 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
960 unsigned long mmr, base;
961 int shift, enable, m_io, n_io;
962
963 if (is_uv3_hub() || is_uv4_hub()) {
964
965 map_mmioh_high_uv34(0, min_pnode, max_pnode);
966 map_mmioh_high_uv34(1, min_pnode, max_pnode);
967 return;
968 }
969
970 if (is_uv1_hub()) {
971 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
972 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
973 mmioh.v = uv_read_local_mmr(mmr);
974 enable = !!mmioh.s1.enable;
975 base = mmioh.s1.base;
976 m_io = mmioh.s1.m_io;
977 n_io = mmioh.s1.n_io;
978 } else if (is_uv2_hub()) {
979 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
980 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
981 mmioh.v = uv_read_local_mmr(mmr);
982 enable = !!mmioh.s2.enable;
983 base = mmioh.s2.base;
984 m_io = mmioh.s2.m_io;
985 n_io = mmioh.s2.n_io;
986 } else
987 return;
988
989 if (enable) {
990 max_pnode &= (1 << n_io) - 1;
991 pr_info(
992 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
993 base, shift, m_io, n_io, max_pnode);
994 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
995 } else {
996 pr_info("UV: MMIOH disabled\n");
997 }
998}
999
1000static __init void map_low_mmrs(void)
1001{
1002 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1003 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1004}
1005
1006static __init void uv_rtc_init(void)
1007{
1008 long status;
1009 u64 ticks_per_sec;
1010
1011 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
1012 &ticks_per_sec);
1013 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1014 printk(KERN_WARNING
1015 "unable to determine platform RTC clock frequency, "
1016 "guessing.\n");
1017
1018 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1019 } else
1020 sn_rtc_cycles_per_second = ticks_per_sec;
1021}
1022
1023
1024
1025
1026static void uv_heartbeat(unsigned long ignored)
1027{
1028 struct timer_list *timer = &uv_scir_info->timer;
1029 unsigned char bits = uv_scir_info->state;
1030
1031
1032 bits ^= SCIR_CPU_HEARTBEAT;
1033
1034
1035 if (idle_cpu(raw_smp_processor_id()))
1036 bits &= ~SCIR_CPU_ACTIVITY;
1037 else
1038 bits |= SCIR_CPU_ACTIVITY;
1039
1040
1041 uv_set_scir_bits(bits);
1042
1043
1044 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1045}
1046
1047static void uv_heartbeat_enable(int cpu)
1048{
1049 while (!uv_cpu_scir_info(cpu)->enabled) {
1050 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1051
1052 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1053 setup_timer(timer, uv_heartbeat, cpu);
1054 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1055 add_timer_on(timer, cpu);
1056 uv_cpu_scir_info(cpu)->enabled = 1;
1057
1058
1059 cpu = 0;
1060 }
1061}
1062
1063#ifdef CONFIG_HOTPLUG_CPU
1064static void uv_heartbeat_disable(int cpu)
1065{
1066 if (uv_cpu_scir_info(cpu)->enabled) {
1067 uv_cpu_scir_info(cpu)->enabled = 0;
1068 del_timer(&uv_cpu_scir_info(cpu)->timer);
1069 }
1070 uv_set_cpu_scir_bits(cpu, 0xff);
1071}
1072
1073
1074
1075
1076static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
1077 void *hcpu)
1078{
1079 long cpu = (long)hcpu;
1080
1081 switch (action) {
1082 case CPU_ONLINE:
1083 uv_heartbeat_enable(cpu);
1084 break;
1085 case CPU_DOWN_PREPARE:
1086 uv_heartbeat_disable(cpu);
1087 break;
1088 default:
1089 break;
1090 }
1091 return NOTIFY_OK;
1092}
1093
1094static __init void uv_scir_register_cpu_notifier(void)
1095{
1096 hotcpu_notifier(uv_scir_cpu_notify, 0);
1097}
1098
1099#else
1100
1101static __init void uv_scir_register_cpu_notifier(void)
1102{
1103}
1104
1105static __init int uv_init_heartbeat(void)
1106{
1107 int cpu;
1108
1109 if (is_uv_system())
1110 for_each_online_cpu(cpu)
1111 uv_heartbeat_enable(cpu);
1112 return 0;
1113}
1114
1115late_initcall(uv_init_heartbeat);
1116
1117#endif
1118
1119
1120int uv_set_vga_state(struct pci_dev *pdev, bool decode,
1121 unsigned int command_bits, u32 flags)
1122{
1123 int domain, bus, rc;
1124
1125 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
1126 pdev->devfn, decode, command_bits, flags);
1127
1128 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1129 return 0;
1130
1131 if ((command_bits & PCI_COMMAND_IO) == 0)
1132 return 0;
1133
1134 domain = pci_domain_nr(pdev->bus);
1135 bus = pdev->bus->number;
1136
1137 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1138 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
1139
1140 return rc;
1141}
1142
1143
1144
1145
1146
1147void uv_cpu_init(void)
1148{
1149
1150 if (smp_processor_id() == 0)
1151 return;
1152
1153 uv_hub_info->nr_online_cpus++;
1154
1155 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1156 set_x2apic_extra_bits(uv_hub_info->pnode);
1157}
1158
1159struct mn {
1160 unsigned char m_val;
1161 unsigned char n_val;
1162 unsigned char m_shift;
1163 unsigned char n_lshift;
1164};
1165
1166static void get_mn(struct mn *mnp)
1167{
1168 union uvh_rh_gam_config_mmr_u m_n_config;
1169 union uv3h_gr0_gam_gr_config_u m_gr_config;
1170
1171 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1172 mnp->n_val = m_n_config.s.n_skt;
1173 if (is_uv4_hub()) {
1174 mnp->m_val = 0;
1175 mnp->n_lshift = 0;
1176 } else if (is_uv3_hub()) {
1177 mnp->m_val = m_n_config.s3.m_skt;
1178 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1179 mnp->n_lshift = m_gr_config.s3.m_skt;
1180 } else if (is_uv2_hub()) {
1181 mnp->m_val = m_n_config.s2.m_skt;
1182 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1183 } else if (is_uv1_hub()) {
1184 mnp->m_val = m_n_config.s1.m_skt;
1185 mnp->n_lshift = mnp->m_val;
1186 }
1187 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1188}
1189
1190void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
1191{
1192 struct mn mn = {0};
1193 union uvh_node_id_u node_id;
1194
1195 get_mn(&mn);
1196 hub_info->m_val = mn.m_val;
1197 hub_info->n_val = mn.n_val;
1198 hub_info->m_shift = mn.m_shift;
1199 hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1200
1201 hub_info->hub_revision = uv_hub_info->hub_revision;
1202 hub_info->pnode_mask = uv_cpuid.pnode_mask;
1203 hub_info->min_pnode = _min_pnode;
1204 hub_info->min_socket = _min_socket;
1205 hub_info->pnode_to_socket = _pnode_to_socket;
1206 hub_info->socket_to_node = _socket_to_node;
1207 hub_info->socket_to_pnode = _socket_to_pnode;
1208 hub_info->gr_table_len = _gr_table_len;
1209 hub_info->gr_table = _gr_table;
1210 hub_info->gpa_mask = mn.m_val ?
1211 (1UL << (mn.m_val + mn.n_val)) - 1 :
1212 (1UL << uv_cpuid.gpa_shift) - 1;
1213
1214 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1215 uv_cpuid.gnode_shift = max_t(unsigned int,
1216 uv_cpuid.gnode_shift, mn.n_val);
1217 hub_info->gnode_extra =
1218 (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1219
1220 if (mn.m_val)
1221 hub_info->gnode_upper = (u64)hub_info->gnode_extra << mn.m_val;
1222
1223 if (uv_gp_table) {
1224 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1225 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1226 hub_info->global_gru_base = uv_gp_table->gru_base;
1227 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1228 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1229 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1230 } else {
1231 hub_info->global_mmr_base =
1232 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1233 ~UV_MMR_ENABLE;
1234 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1235 }
1236
1237 get_lowmem_redirect(
1238 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
1239
1240 hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
1241
1242
1243 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1244 hub_info->n_val, hub_info->m_val,
1245 hub_info->m_shift, hub_info->n_lshift);
1246
1247 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
1248 hub_info->gpa_mask, hub_info->gpa_shift,
1249 hub_info->pnode_mask, hub_info->apic_pnode_shift);
1250
1251 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
1252 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1253 hub_info->global_gru_base, hub_info->global_gru_shift);
1254
1255 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1256 hub_info->gnode_upper, hub_info->gnode_extra);
1257}
1258
1259static void __init decode_gam_params(unsigned long ptr)
1260{
1261 uv_gp_table = (struct uv_gam_parameters *)ptr;
1262
1263 pr_info("UV: GAM Params...\n");
1264 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1265 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1266 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1267 uv_gp_table->gpa_shift);
1268}
1269
1270static void __init decode_gam_rng_tbl(unsigned long ptr)
1271{
1272 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1273 unsigned long lgre = 0;
1274 int index = 0;
1275 int sock_min = 999999, pnode_min = 99999;
1276 int sock_max = -1, pnode_max = -1;
1277
1278 uv_gre_table = gre;
1279 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1280 unsigned long size = ((unsigned long)(gre->limit - lgre)
1281 << UV_GAM_RANGE_SHFT);
1282 int order = 0;
1283 char suffix[] = " KMGTPE";
1284 int flag = ' ';
1285
1286 while (size > 9999 && order < sizeof(suffix)) {
1287 size /= 1024;
1288 order++;
1289 }
1290
1291
1292 if (gre->type == 1 || gre->type == 2)
1293 if (adj_blksize(lgre))
1294 flag = '*';
1295
1296 if (!index) {
1297 pr_info("UV: GAM Range Table...\n");
1298 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1299 }
1300 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1301 index++,
1302 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1303 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1304 flag, size, suffix[order],
1305 gre->type, gre->nasid, gre->sockid, gre->pnode);
1306
1307
1308 lgre = gre->limit;
1309 if (sock_min > gre->sockid)
1310 sock_min = gre->sockid;
1311 if (sock_max < gre->sockid)
1312 sock_max = gre->sockid;
1313 if (pnode_min > gre->pnode)
1314 pnode_min = gre->pnode;
1315 if (pnode_max < gre->pnode)
1316 pnode_max = gre->pnode;
1317 }
1318 _min_socket = sock_min;
1319 _max_socket = sock_max;
1320 _min_pnode = pnode_min;
1321 _max_pnode = pnode_max;
1322 _gr_table_len = index;
1323 pr_info(
1324 "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1325 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1326}
1327
1328static int __init decode_uv_systab(void)
1329{
1330 struct uv_systab *st;
1331 int i;
1332
1333 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1334 return 0;
1335
1336 st = uv_systab;
1337 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1338 int rev = st ? st->revision : 0;
1339
1340 pr_err(
1341 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1342 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1343 pr_err(
1344 "UV: Cannot support UV operations, switching to generic PC\n");
1345 uv_system_type = UV_NONE;
1346 return -EINVAL;
1347 }
1348
1349 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1350 unsigned long ptr = st->entry[i].offset;
1351
1352 if (!ptr)
1353 continue;
1354
1355 ptr = ptr + (unsigned long)st;
1356
1357 switch (st->entry[i].type) {
1358 case UV_SYSTAB_TYPE_GAM_PARAMS:
1359 decode_gam_params(ptr);
1360 break;
1361
1362 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1363 decode_gam_rng_tbl(ptr);
1364 break;
1365 }
1366 }
1367 return 0;
1368}
1369
1370
1371
1372
1373
1374
1375static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1376{
1377 int i, uv_pb = 0;
1378
1379 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1380 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1381 unsigned long np;
1382
1383 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1384 if (np)
1385 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1386
1387 uv_pb += hweight64(np);
1388 }
1389 if (uv_possible_blades != uv_pb)
1390 uv_possible_blades = uv_pb;
1391}
1392
1393static void __init build_socket_tables(void)
1394{
1395 struct uv_gam_range_entry *gre = uv_gre_table;
1396 int num, nump;
1397 int cpu, i, lnid;
1398 int minsock = _min_socket;
1399 int maxsock = _max_socket;
1400 int minpnode = _min_pnode;
1401 int maxpnode = _max_pnode;
1402 size_t bytes;
1403
1404 if (!gre) {
1405 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1406 pr_info("UV: No UVsystab socket table, ignoring\n");
1407 return;
1408 }
1409 pr_crit(
1410 "UV: Error: UVsystab address translations not available!\n");
1411 BUG();
1412 }
1413
1414
1415 num = maxsock - minsock + 1;
1416 bytes = num * sizeof(_socket_to_node[0]);
1417 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1418 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1419
1420 nump = maxpnode - minpnode + 1;
1421 bytes = nump * sizeof(_pnode_to_socket[0]);
1422 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1423 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1424
1425 for (i = 0; i < num; i++)
1426 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1427
1428 for (i = 0; i < nump; i++)
1429 _pnode_to_socket[i] = SOCK_EMPTY;
1430
1431
1432 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1433 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1434 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1435 continue;
1436 i = gre->sockid - minsock;
1437 if (_socket_to_pnode[i] != SOCK_EMPTY)
1438 continue;
1439 _socket_to_pnode[i] = gre->pnode;
1440
1441 i = gre->pnode - minpnode;
1442 _pnode_to_socket[i] = gre->sockid;
1443
1444 pr_info(
1445 "UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1446 gre->sockid, gre->type, gre->nasid,
1447 _socket_to_pnode[gre->sockid - minsock],
1448 _pnode_to_socket[gre->pnode - minpnode]);
1449 }
1450
1451
1452 lnid = -1;
1453 for_each_present_cpu(cpu) {
1454 int nid = cpu_to_node(cpu);
1455 int apicid, sockid;
1456
1457 if (lnid == nid)
1458 continue;
1459 lnid = nid;
1460 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1461 sockid = apicid >> uv_cpuid.socketid_shift;
1462 _socket_to_node[sockid - minsock] = nid;
1463 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1464 sockid, apicid, nid);
1465 }
1466
1467
1468 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1469 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1470 BUG_ON(!_node_to_pnode);
1471
1472 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1473 unsigned short sockid;
1474
1475 for (sockid = minsock; sockid <= maxsock; sockid++) {
1476 if (lnid == _socket_to_node[sockid - minsock]) {
1477 _node_to_pnode[lnid] =
1478 _socket_to_pnode[sockid - minsock];
1479 break;
1480 }
1481 }
1482 if (sockid > maxsock) {
1483 pr_err("UV: socket for node %d not found!\n", lnid);
1484 BUG();
1485 }
1486 }
1487
1488
1489
1490
1491
1492 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1493 if (minsock == 0) {
1494 for (i = 0; i < num; i++)
1495 if (_socket_to_node[i] == SOCK_EMPTY ||
1496 i != _socket_to_node[i])
1497 break;
1498 if (i >= num) {
1499 kfree(_socket_to_node);
1500 _socket_to_node = NULL;
1501 pr_info("UV: 1:1 socket_to_node table removed\n");
1502 }
1503 }
1504 if (minsock == minpnode) {
1505 for (i = 0; i < num; i++)
1506 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1507 _socket_to_pnode[i] != i + minpnode)
1508 break;
1509 if (i >= num) {
1510 kfree(_socket_to_pnode);
1511 _socket_to_pnode = NULL;
1512 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1513 }
1514 }
1515}
1516
1517static void __init uv_system_init_hub(void)
1518{
1519 struct uv_hub_info_s hub_info = {0};
1520 int bytes, cpu, nodeid;
1521 unsigned short min_pnode = 9999, max_pnode = 0;
1522 char *hub = is_uv4_hub() ? "UV400" :
1523 is_uv3_hub() ? "UV300" :
1524 is_uv2_hub() ? "UV2000/3000" :
1525 is_uv1_hub() ? "UV100/1000" : NULL;
1526
1527 if (!hub) {
1528 pr_err("UV: Unknown/unsupported UV hub\n");
1529 return;
1530 }
1531 pr_info("UV: Found %s hub\n", hub);
1532
1533 map_low_mmrs();
1534
1535 uv_bios_init();
1536 if (decode_uv_systab() < 0)
1537 return;
1538 build_socket_tables();
1539 build_uv_gr_table();
1540 set_block_size();
1541 uv_init_hub_info(&hub_info);
1542 uv_possible_blades = num_possible_nodes();
1543 if (!_node_to_pnode)
1544 boot_init_possible_blades(&hub_info);
1545
1546
1547 pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1548 uv_num_possible_blades(),
1549 num_possible_nodes(),
1550 num_possible_cpus());
1551
1552 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1553 &sn_region_size, &system_serial_number);
1554 hub_info.coherency_domain_number = sn_coherency_id;
1555 uv_rtc_init();
1556
1557 bytes = sizeof(void *) * uv_num_possible_blades();
1558 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1559 BUG_ON(!__uv_hub_info_list);
1560
1561 bytes = sizeof(struct uv_hub_info_s);
1562 for_each_node(nodeid) {
1563 struct uv_hub_info_s *new_hub;
1564
1565 if (__uv_hub_info_list[nodeid]) {
1566 pr_err("UV: Node %d UV HUB already initialized!?\n",
1567 nodeid);
1568 BUG();
1569 }
1570
1571
1572 new_hub = (nodeid == 0) ?
1573 &uv_hub_info_node0 :
1574 kzalloc_node(bytes, GFP_KERNEL, nodeid);
1575 BUG_ON(!new_hub);
1576 __uv_hub_info_list[nodeid] = new_hub;
1577 new_hub = uv_hub_info_list(nodeid);
1578 BUG_ON(!new_hub);
1579 *new_hub = hub_info;
1580
1581
1582 if (_node_to_pnode)
1583 new_hub->pnode = _node_to_pnode[nodeid];
1584 else
1585 new_hub->pnode = 0xffff;
1586 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1587 new_hub->memory_nid = -1;
1588 new_hub->nr_possible_cpus = 0;
1589 new_hub->nr_online_cpus = 0;
1590 }
1591
1592
1593 for_each_possible_cpu(cpu) {
1594 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1595 int numa_node_id;
1596 unsigned short pnode;
1597
1598 nodeid = cpu_to_node(cpu);
1599 numa_node_id = numa_cpu_node(cpu);
1600 pnode = uv_apicid_to_pnode(apicid);
1601
1602 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1603 uv_cpu_info_per(cpu)->blade_cpu_id =
1604 uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1605 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1606 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1607 if (nodeid != numa_node_id &&
1608 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1609 uv_hub_info_list(numa_node_id)->pnode = pnode;
1610 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1611 uv_cpu_hub_info(cpu)->pnode = pnode;
1612 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1613 }
1614
1615 for_each_node(nodeid) {
1616 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1617
1618
1619 if (pnode == 0xffff) {
1620 unsigned long paddr;
1621
1622 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1623 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1624 uv_hub_info_list(nodeid)->pnode = pnode;
1625 }
1626 min_pnode = min(pnode, min_pnode);
1627 max_pnode = max(pnode, max_pnode);
1628 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1629 nodeid,
1630 uv_hub_info_list(nodeid)->pnode,
1631 uv_hub_info_list(nodeid)->nr_possible_cpus);
1632 }
1633
1634 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1635 map_gru_high(max_pnode);
1636 map_mmr_high(max_pnode);
1637 map_mmioh_high(min_pnode, max_pnode);
1638
1639 uv_nmi_setup();
1640 uv_cpu_init();
1641 uv_scir_register_cpu_notifier();
1642 proc_mkdir("sgi_uv", NULL);
1643
1644
1645 pci_register_set_vga_state(uv_set_vga_state);
1646
1647
1648
1649
1650
1651 if (is_kdump_kernel())
1652 reboot_type = BOOT_ACPI;
1653}
1654
1655
1656
1657
1658
1659void __init uv_system_init(void)
1660{
1661 if (likely(!is_uv_system() && !is_uv_hubless()))
1662 return;
1663
1664 if (is_uv_system())
1665 uv_system_init_hub();
1666 else
1667 uv_nmi_setup_hubless();
1668}
1669
1670apic_driver(apic_x2apic_uv_x);
1671
