LXR linux/drivers/ata/ahci.h

   1/*
   2 *  ahci.h - Common AHCI SATA definitions and declarations
   3 *
   4 *  Maintained by:  Tejun Heo <tj@kernel.org>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#ifndef _AHCI_H
  36#define _AHCI_H
  37
  38#include <linux/clk.h>
  39#include <linux/libata.h>
  40
  41/* Enclosure Management Control */
  42#define EM_CTRL_MSG_TYPE              0x000f0000
  43
  44/* Enclosure Management LED Message Type */
  45#define EM_MSG_LED_HBA_PORT           0x0000000f
  46#define EM_MSG_LED_PMP_SLOT           0x0000ff00
  47#define EM_MSG_LED_VALUE              0xffff0000
  48#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
  49#define EM_MSG_LED_VALUE_OFF          0xfff80000
  50#define EM_MSG_LED_VALUE_ON           0x00010000
  51
  52enum {
  53        AHCI_MAX_PORTS          = 32,
  54        AHCI_MAX_SG             = 168, /* hardware max is 64K */
  55        AHCI_DMA_BOUNDARY       = 0xffffffff,
  56        AHCI_MAX_CMDS           = 32,
  57        AHCI_CMD_SZ             = 32,
  58        AHCI_CMD_SLOT_SZ        = AHCI_MAX_CMDS * AHCI_CMD_SZ,
  59        AHCI_RX_FIS_SZ          = 256,
  60        AHCI_CMD_TBL_CDB        = 0x40,
  61        AHCI_CMD_TBL_HDR_SZ     = 0x80,
  62        AHCI_CMD_TBL_SZ         = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
  63        AHCI_CMD_TBL_AR_SZ      = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
  64        AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
  65                                  AHCI_RX_FIS_SZ,
  66        AHCI_PORT_PRIV_FBS_DMA_SZ       = AHCI_CMD_SLOT_SZ +
  67                                          AHCI_CMD_TBL_AR_SZ +
  68                                          (AHCI_RX_FIS_SZ * 16),
  69        AHCI_IRQ_ON_SG          = (1 << 31),
  70        AHCI_CMD_ATAPI          = (1 << 5),
  71        AHCI_CMD_WRITE          = (1 << 6),
  72        AHCI_CMD_PREFETCH       = (1 << 7),
  73        AHCI_CMD_RESET          = (1 << 8),
  74        AHCI_CMD_CLR_BUSY       = (1 << 10),
  75
  76        RX_FIS_PIO_SETUP        = 0x20, /* offset of PIO Setup FIS data */
  77        RX_FIS_D2H_REG          = 0x40, /* offset of D2H Register FIS data */
  78        RX_FIS_SDB              = 0x58, /* offset of SDB FIS data */
  79        RX_FIS_UNK              = 0x60, /* offset of Unknown FIS data */
  80
  81        /* global controller registers */
  82        HOST_CAP                = 0x00, /* host capabilities */
  83        HOST_CTL                = 0x04, /* global host control */
  84        HOST_IRQ_STAT           = 0x08, /* interrupt status */
  85        HOST_PORTS_IMPL         = 0x0c, /* bitmap of implemented ports */
  86        HOST_VERSION            = 0x10, /* AHCI spec. version compliancy */
  87        HOST_EM_LOC             = 0x1c, /* Enclosure Management location */
  88        HOST_EM_CTL             = 0x20, /* Enclosure Management Control */
  89        HOST_CAP2               = 0x24, /* host capabilities, extended */
  90
  91        /* HOST_CTL bits */
  92        HOST_RESET              = (1 << 0),  /* reset controller; self-clear */
  93        HOST_IRQ_EN             = (1 << 1),  /* global IRQ enable */
  94        HOST_MRSM               = (1 << 2),  /* MSI Revert to Single Message */
  95        HOST_AHCI_EN            = (1 << 31), /* AHCI enabled */
  96
  97        /* HOST_CAP bits */
  98        HOST_CAP_SXS            = (1 << 5),  /* Supports External SATA */
  99        HOST_CAP_EMS            = (1 << 6),  /* Enclosure Management support */
 100        HOST_CAP_CCC            = (1 << 7),  /* Command Completion Coalescing */
 101        HOST_CAP_PART           = (1 << 13), /* Partial state capable */
 102        HOST_CAP_SSC            = (1 << 14), /* Slumber state capable */
 103        HOST_CAP_PIO_MULTI      = (1 << 15), /* PIO multiple DRQ support */
 104        HOST_CAP_FBS            = (1 << 16), /* FIS-based switching support */
 105        HOST_CAP_PMP            = (1 << 17), /* Port Multiplier support */
 106        HOST_CAP_ONLY           = (1 << 18), /* Supports AHCI mode only */
 107        HOST_CAP_CLO            = (1 << 24), /* Command List Override support */
 108        HOST_CAP_LED            = (1 << 25), /* Supports activity LED */
 109        HOST_CAP_ALPM           = (1 << 26), /* Aggressive Link PM support */
 110        HOST_CAP_SSS            = (1 << 27), /* Staggered Spin-up */
 111        HOST_CAP_MPS            = (1 << 28), /* Mechanical presence switch */
 112        HOST_CAP_SNTF           = (1 << 29), /* SNotification register */
 113        HOST_CAP_NCQ            = (1 << 30), /* Native Command Queueing */
 114        HOST_CAP_64             = (1 << 31), /* PCI DAC (64-bit DMA) support */
 115
 116        /* HOST_CAP2 bits */
 117        HOST_CAP2_BOH           = (1 << 0),  /* BIOS/OS handoff supported */
 118        HOST_CAP2_NVMHCI        = (1 << 1),  /* NVMHCI supported */
 119        HOST_CAP2_APST          = (1 << 2),  /* Automatic partial to slumber */
 120        HOST_CAP2_SDS           = (1 << 3),  /* Support device sleep */
 121        HOST_CAP2_SADM          = (1 << 4),  /* Support aggressive DevSlp */
 122        HOST_CAP2_DESO          = (1 << 5),  /* DevSlp from slumber only */
 123
 124        /* registers for each SATA port */
 125        PORT_LST_ADDR           = 0x00, /* command list DMA addr */
 126        PORT_LST_ADDR_HI        = 0x04, /* command list DMA addr hi */
 127        PORT_FIS_ADDR           = 0x08, /* FIS rx buf addr */
 128        PORT_FIS_ADDR_HI        = 0x0c, /* FIS rx buf addr hi */
 129        PORT_IRQ_STAT           = 0x10, /* interrupt status */
 130        PORT_IRQ_MASK           = 0x14, /* interrupt enable/disable mask */
 131        PORT_CMD                = 0x18, /* port command */
 132        PORT_TFDATA             = 0x20, /* taskfile data */
 133        PORT_SIG                = 0x24, /* device TF signature */
 134        PORT_CMD_ISSUE          = 0x38, /* command issue */
 135        PORT_SCR_STAT           = 0x28, /* SATA phy register: SStatus */
 136        PORT_SCR_CTL            = 0x2c, /* SATA phy register: SControl */
 137        PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
 138        PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
 139        PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
 140        PORT_FBS                = 0x40, /* FIS-based Switching */
 141        PORT_DEVSLP             = 0x44, /* device sleep */
 142
 143        /* PORT_IRQ_{STAT,MASK} bits */
 144        PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
 145        PORT_IRQ_TF_ERR         = (1 << 30), /* task file error */
 146        PORT_IRQ_HBUS_ERR       = (1 << 29), /* host bus fatal error */
 147        PORT_IRQ_HBUS_DATA_ERR  = (1 << 28), /* host bus data error */
 148        PORT_IRQ_IF_ERR         = (1 << 27), /* interface fatal error */
 149        PORT_IRQ_IF_NONFATAL    = (1 << 26), /* interface non-fatal error */
 150        PORT_IRQ_OVERFLOW       = (1 << 24), /* xfer exhausted available S/G */
 151        PORT_IRQ_BAD_PMP        = (1 << 23), /* incorrect port multiplier */
 152
 153        PORT_IRQ_PHYRDY         = (1 << 22), /* PhyRdy changed */
 154        PORT_IRQ_DEV_ILCK       = (1 << 7), /* device interlock */
 155        PORT_IRQ_CONNECT        = (1 << 6), /* port connect change status */
 156        PORT_IRQ_SG_DONE        = (1 << 5), /* descriptor processed */
 157        PORT_IRQ_UNK_FIS        = (1 << 4), /* unknown FIS rx'd */
 158        PORT_IRQ_SDB_FIS        = (1 << 3), /* Set Device Bits FIS rx'd */
 159        PORT_IRQ_DMAS_FIS       = (1 << 2), /* DMA Setup FIS rx'd */
 160        PORT_IRQ_PIOS_FIS       = (1 << 1), /* PIO Setup FIS rx'd */
 161        PORT_IRQ_D2H_REG_FIS    = (1 << 0), /* D2H Register FIS rx'd */
 162
 163        PORT_IRQ_FREEZE         = PORT_IRQ_HBUS_ERR |
 164                                  PORT_IRQ_IF_ERR |
 165                                  PORT_IRQ_CONNECT |
 166                                  PORT_IRQ_PHYRDY |
 167                                  PORT_IRQ_UNK_FIS |
 168                                  PORT_IRQ_BAD_PMP,
 169        PORT_IRQ_ERROR          = PORT_IRQ_FREEZE |
 170                                  PORT_IRQ_TF_ERR |
 171                                  PORT_IRQ_HBUS_DATA_ERR,
 172        DEF_PORT_IRQ            = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
 173                                  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
 174                                  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
 175
 176        /* PORT_CMD bits */
 177        PORT_CMD_ASP            = (1 << 27), /* Aggressive Slumber/Partial */
 178        PORT_CMD_ALPE           = (1 << 26), /* Aggressive Link PM enable */
 179        PORT_CMD_ATAPI          = (1 << 24), /* Device is ATAPI */
 180        PORT_CMD_FBSCP          = (1 << 22), /* FBS Capable Port */
 181        PORT_CMD_ESP            = (1 << 21), /* External Sata Port */
 182        PORT_CMD_HPCP           = (1 << 18), /* HotPlug Capable Port */
 183        PORT_CMD_PMP            = (1 << 17), /* PMP attached */
 184        PORT_CMD_LIST_ON        = (1 << 15), /* cmd list DMA engine running */
 185        PORT_CMD_FIS_ON         = (1 << 14), /* FIS DMA engine running */
 186        PORT_CMD_FIS_RX         = (1 << 4), /* Enable FIS receive DMA engine */
 187        PORT_CMD_CLO            = (1 << 3), /* Command list override */
 188        PORT_CMD_POWER_ON       = (1 << 2), /* Power up device */
 189        PORT_CMD_SPIN_UP        = (1 << 1), /* Spin up device */
 190        PORT_CMD_START          = (1 << 0), /* Enable port DMA engine */
 191
 192        PORT_CMD_ICC_MASK       = (0xf << 28), /* i/f ICC state mask */
 193        PORT_CMD_ICC_ACTIVE     = (0x1 << 28), /* Put i/f in active state */
 194        PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
 195        PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
 196
 197        /* PORT_FBS bits */
 198        PORT_FBS_DWE_OFFSET     = 16, /* FBS device with error offset */
 199        PORT_FBS_ADO_OFFSET     = 12, /* FBS active dev optimization offset */
 200        PORT_FBS_DEV_OFFSET     = 8,  /* FBS device to issue offset */
 201        PORT_FBS_DEV_MASK       = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
 202        PORT_FBS_SDE            = (1 << 2), /* FBS single device error */
 203        PORT_FBS_DEC            = (1 << 1), /* FBS device error clear */
 204        PORT_FBS_EN             = (1 << 0), /* Enable FBS */
 205
 206        /* PORT_DEVSLP bits */
 207        PORT_DEVSLP_DM_OFFSET   = 25,             /* DITO multiplier offset */
 208        PORT_DEVSLP_DM_MASK     = (0xf << 25),    /* DITO multiplier mask */
 209        PORT_DEVSLP_DITO_OFFSET = 15,             /* DITO offset */
 210        PORT_DEVSLP_MDAT_OFFSET = 10,             /* Minimum assertion time */
 211        PORT_DEVSLP_DETO_OFFSET = 2,              /* DevSlp exit timeout */
 212        PORT_DEVSLP_DSP         = (1 << 1),       /* DevSlp present */
 213        PORT_DEVSLP_ADSE        = (1 << 0),       /* Aggressive DevSlp enable */
 214
 215        /* hpriv->flags bits */
 216
 217#define AHCI_HFLAGS(flags)              .private_data   = (void *)(flags)
 218
 219        AHCI_HFLAG_NO_NCQ               = (1 << 0),
 220        AHCI_HFLAG_IGN_IRQ_IF_ERR       = (1 << 1), /* ignore IRQ_IF_ERR */
 221        AHCI_HFLAG_IGN_SERR_INTERNAL    = (1 << 2), /* ignore SERR_INTERNAL */
 222        AHCI_HFLAG_32BIT_ONLY           = (1 << 3), /* force 32bit */
 223        AHCI_HFLAG_MV_PATA              = (1 << 4), /* PATA port */
 224        AHCI_HFLAG_NO_MSI               = (1 << 5), /* no PCI MSI */
 225        AHCI_HFLAG_NO_PMP               = (1 << 6), /* no PMP */
 226        AHCI_HFLAG_SECT255              = (1 << 8), /* max 255 sectors */
 227        AHCI_HFLAG_YES_NCQ              = (1 << 9), /* force NCQ cap on */
 228        AHCI_HFLAG_NO_SUSPEND           = (1 << 10), /* don't suspend */
 229        AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
 230                                                        link offline */
 231        AHCI_HFLAG_NO_SNTF              = (1 << 12), /* no sntf */
 232        AHCI_HFLAG_NO_FPDMA_AA          = (1 << 13), /* no FPDMA AA */
 233        AHCI_HFLAG_YES_FBS              = (1 << 14), /* force FBS cap on */
 234        AHCI_HFLAG_DELAY_ENGINE         = (1 << 15), /* do not start engine on
 235                                                        port start (wait until
 236                                                        error-handling stage) */
 237        AHCI_HFLAG_MULTI_MSI            = (1 << 16), /* multiple PCI MSIs */
 238        AHCI_HFLAG_NO_FBS               = (1 << 17), /* no FBS */
 239        AHCI_HFLAG_MULTI_MSIX           = (1 << 18), /* per-port MSI-X */
 240
 241        /* ap->flags bits */
 242
 243        AHCI_FLAG_COMMON                = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
 244                                          ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
 245
 246        ICH_MAP                         = 0x90, /* ICH MAP register */
 247
 248        /* em constants */
 249        EM_MAX_SLOTS                    = 8,
 250        EM_MAX_RETRY                    = 5,
 251
 252        /* em_ctl bits */
 253        EM_CTL_RST              = (1 << 9), /* Reset */
 254        EM_CTL_TM               = (1 << 8), /* Transmit Message */
 255        EM_CTL_MR               = (1 << 0), /* Message Received */
 256        EM_CTL_ALHD             = (1 << 26), /* Activity LED */
 257        EM_CTL_XMT              = (1 << 25), /* Transmit Only */
 258        EM_CTL_SMB              = (1 << 24), /* Single Message Buffer */
 259        EM_CTL_SGPIO            = (1 << 19), /* SGPIO messages supported */
 260        EM_CTL_SES              = (1 << 18), /* SES-2 messages supported */
 261        EM_CTL_SAFTE            = (1 << 17), /* SAF-TE messages supported */
 262        EM_CTL_LED              = (1 << 16), /* LED messages supported */
 263
 264        /* em message type */
 265        EM_MSG_TYPE_LED         = (1 << 0), /* LED */
 266        EM_MSG_TYPE_SAFTE       = (1 << 1), /* SAF-TE */
 267        EM_MSG_TYPE_SES2        = (1 << 2), /* SES-2 */
 268        EM_MSG_TYPE_SGPIO       = (1 << 3), /* SGPIO */
 269};
 270
 271struct ahci_cmd_hdr {
 272        __le32                  opts;
 273        __le32                  status;
 274        __le32                  tbl_addr;
 275        __le32                  tbl_addr_hi;
 276        __le32                  reserved[4];
 277};
 278
 279struct ahci_sg {
 280        __le32                  addr;
 281        __le32                  addr_hi;
 282        __le32                  reserved;
 283        __le32                  flags_size;
 284};
 285
 286struct ahci_em_priv {
 287        enum sw_activity blink_policy;
 288        struct timer_list timer;
 289        unsigned long saved_activity;
 290        unsigned long activity;
 291        unsigned long led_state;
 292};
 293
 294struct ahci_port_priv {
 295        struct ata_link         *active_link;
 296        struct ahci_cmd_hdr     *cmd_slot;
 297        dma_addr_t              cmd_slot_dma;
 298        void                    *cmd_tbl;
 299        dma_addr_t              cmd_tbl_dma;
 300        void                    *rx_fis;
 301        dma_addr_t              rx_fis_dma;
 302        /* for NCQ spurious interrupt analysis */
 303        unsigned int            ncq_saw_d2h:1;
 304        unsigned int            ncq_saw_dmas:1;
 305        unsigned int            ncq_saw_sdb:1;
 306        spinlock_t              lock;           /* protects parent ata_port */
 307        u32                     intr_mask;      /* interrupts to enable */
 308        bool                    fbs_supported;  /* set iff FBS is supported */
 309        bool                    fbs_enabled;    /* set iff FBS is enabled */
 310        int                     fbs_last_dev;   /* save FBS.DEV of last FIS */
 311        /* enclosure management info per PM slot */
 312        struct ahci_em_priv     em_priv[EM_MAX_SLOTS];
 313        char                    *irq_desc;      /* desc in /proc/interrupts */
 314};
 315
 316struct ahci_host_priv {
 317        void __iomem *          mmio;           /* bus-independent mem map */
 318        unsigned int            flags;          /* AHCI_HFLAG_* */
 319        u32                     cap;            /* cap to use */
 320        u32                     cap2;           /* cap2 to use */
 321        u32                     version;        /* cached version */
 322        u32                     port_map;       /* port map to use */
 323        u32                     saved_cap;      /* saved initial cap */
 324        u32                     saved_cap2;     /* saved initial cap2 */
 325        u32                     saved_port_map; /* saved initial port_map */
 326        u32                     em_loc; /* enclosure management location */
 327        u32                     em_buf_sz;      /* EM buffer size in byte */
 328        u32                     em_msg_type;    /* EM message type */
 329        struct clk              *clk;           /* Only for platforms supporting clk */
 330        struct msix_entry       *msix;          /* Optional MSI-X support */
 331        unsigned int            irq;            /* interrupt line */
 332};
 333
 334extern int ahci_ignore_sss;
 335
 336extern struct device_attribute *ahci_shost_attrs[];
 337extern struct device_attribute *ahci_sdev_attrs[];
 338
 339#define AHCI_SHT(drv_name)                                              \
 340        ATA_NCQ_SHT(drv_name),                                          \
 341        .can_queue              = AHCI_MAX_CMDS - 1,                    \
 342        .sg_tablesize           = AHCI_MAX_SG,                          \
 343        .dma_boundary           = AHCI_DMA_BOUNDARY,                    \
 344        .shost_attrs            = ahci_shost_attrs,                     \
 345        .sdev_attrs             = ahci_sdev_attrs
 346
 347extern struct ata_port_operations ahci_ops;
 348extern struct ata_port_operations ahci_pmp_retry_srst_ops;
 349
 350unsigned int ahci_dev_classify(struct ata_port *ap);
 351void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
 352                        u32 opts);
 353void ahci_save_initial_config(struct device *dev,
 354                              struct ahci_host_priv *hpriv,
 355                              unsigned int force_port_map,
 356                              unsigned int mask_port_map);
 357void ahci_init_controller(struct ata_host *host);
 358int ahci_reset_controller(struct ata_host *host);
 359
 360int ahci_do_softreset(struct ata_link *link, unsigned int *class,
 361                      int pmp, unsigned long deadline,
 362                      int (*check_ready)(struct ata_link *link));
 363
 364unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
 365int ahci_stop_engine(struct ata_port *ap);
 366void ahci_start_fis_rx(struct ata_port *ap);
 367void ahci_start_engine(struct ata_port *ap);
 368int ahci_check_ready(struct ata_link *link);
 369int ahci_kick_engine(struct ata_port *ap);
 370int ahci_port_resume(struct ata_port *ap);
 371void ahci_set_em_messages(struct ahci_host_priv *hpriv,
 372                          struct ata_port_info *pi);
 373int ahci_reset_em(struct ata_host *host);
 374void ahci_print_info(struct ata_host *host, const char *scc_s);
 375int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
 376
 377static inline void __iomem *__ahci_port_base(struct ata_host *host,
 378                                             unsigned int port_no)
 379{
 380        struct ahci_host_priv *hpriv = host->private_data;
 381        void __iomem *mmio = hpriv->mmio;
 382
 383        return mmio + 0x100 + (port_no * 0x80);
 384}
 385
 386static inline void __iomem *ahci_port_base(struct ata_port *ap)
 387{
 388        return __ahci_port_base(ap->host, ap->port_no);
 389}
 390
 391static inline int ahci_nr_ports(u32 cap)
 392{
 393        return (cap & 0x1f) + 1;
 394}
 395
 396#endif /* _AHCI_H */
 397