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20#include <linux/clk.h>
21#include <linux/clkdev.h>
22#include <linux/clk-provider.h>
23#include <linux/io.h>
24#include <linux/of.h>
25
26
27#define CLKMGR_CTRL 0x0
28#define CLKMGR_BYPASS 0x4
29
30
31#define MAINPLL_BYPASS (1<<0)
32#define SDRAMPLL_BYPASS (1<<1)
33#define SDRAMPLL_SRC_BYPASS (1<<2)
34#define PERPLL_BYPASS (1<<3)
35#define PERPLL_SRC_BYPASS (1<<4)
36
37#define SOCFPGA_PLL_BG_PWRDWN 0
38#define SOCFPGA_PLL_EXT_ENA 1
39#define SOCFPGA_PLL_PWR_DOWN 2
40#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
41#define SOCFPGA_PLL_DIVF_SHIFT 3
42#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
43#define SOCFPGA_PLL_DIVQ_SHIFT 16
44
45extern void __iomem *clk_mgr_base_addr;
46
47struct socfpga_clk {
48 struct clk_gate hw;
49 char *parent_name;
50 char *clk_name;
51 u32 fixed_div;
52};
53#define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
54
55static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
56 unsigned long parent_rate)
57{
58 struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
59 unsigned long divf, divq, vco_freq, reg;
60 unsigned long bypass;
61
62 reg = readl(socfpgaclk->hw.reg);
63 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
64 if (bypass & MAINPLL_BYPASS)
65 return parent_rate;
66
67 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
68 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
69 vco_freq = parent_rate * (divf + 1);
70 return vco_freq / (1 + divq);
71}
72
73
74static struct clk_ops clk_pll_ops = {
75 .recalc_rate = clk_pll_recalc_rate,
76};
77
78static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
79 unsigned long parent_rate)
80{
81 struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
82 u32 div;
83
84 if (socfpgaclk->fixed_div)
85 div = socfpgaclk->fixed_div;
86 else
87 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
88
89 return parent_rate / div;
90}
91
92static const struct clk_ops periclk_ops = {
93 .recalc_rate = clk_periclk_recalc_rate,
94};
95
96static __init struct clk *socfpga_clk_init(struct device_node *node,
97 const struct clk_ops *ops)
98{
99 u32 reg;
100 struct clk *clk;
101 struct socfpga_clk *socfpga_clk;
102 const char *clk_name = node->name;
103 const char *parent_name;
104 struct clk_init_data init;
105 int rc;
106 u32 fixed_div;
107
108 rc = of_property_read_u32(node, "reg", ®);
109 if (WARN_ON(rc))
110 return NULL;
111
112 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
113 if (WARN_ON(!socfpga_clk))
114 return NULL;
115
116 socfpga_clk->hw.reg = clk_mgr_base_addr + reg;
117
118 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
119 if (rc)
120 socfpga_clk->fixed_div = 0;
121 else
122 socfpga_clk->fixed_div = fixed_div;
123
124 of_property_read_string(node, "clock-output-names", &clk_name);
125
126 init.name = clk_name;
127 init.ops = ops;
128 init.flags = 0;
129 parent_name = of_clk_get_parent_name(node, 0);
130 init.parent_names = &parent_name;
131 init.num_parents = 1;
132
133 socfpga_clk->hw.hw.init = &init;
134
135 if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
136 strcmp(clk_name, "sdram_pll")) {
137 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
138 clk_pll_ops.enable = clk_gate_ops.enable;
139 clk_pll_ops.disable = clk_gate_ops.disable;
140 }
141
142 clk = clk_register(NULL, &socfpga_clk->hw.hw);
143 if (WARN_ON(IS_ERR(clk))) {
144 kfree(socfpga_clk);
145 return NULL;
146 }
147 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
148 return clk;
149}
150
151static void __init socfpga_pll_init(struct device_node *node)
152{
153 socfpga_clk_init(node, &clk_pll_ops);
154}
155CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
156
157static void __init socfpga_periph_init(struct device_node *node)
158{
159 socfpga_clk_init(node, &periclk_ops);
160}
161CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
162
163void __init socfpga_init_clocks(void)
164{
165 struct clk *clk;
166 int ret;
167
168 clk = clk_register_fixed_factor(NULL, "smp_twd", "mpuclk", 0, 1, 4);
169 ret = clk_register_clkdev(clk, NULL, "smp_twd");
170 if (ret)
171 pr_err("smp_twd alias not registered\n");
172}
173
