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12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/clk.h>
15#include <linux/cpufreq.h>
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/opp.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <linux/slab.h>
23
24static unsigned int transition_latency;
25static unsigned int voltage_tolerance;
26
27static struct device *cpu_dev;
28static struct clk *cpu_clk;
29static struct regulator *cpu_reg;
30static struct cpufreq_frequency_table *freq_table;
31
32static int cpu0_verify_speed(struct cpufreq_policy *policy)
33{
34 return cpufreq_frequency_table_verify(policy, freq_table);
35}
36
37static unsigned int cpu0_get_speed(unsigned int cpu)
38{
39 return clk_get_rate(cpu_clk) / 1000;
40}
41
42static int cpu0_set_target(struct cpufreq_policy *policy,
43 unsigned int target_freq, unsigned int relation)
44{
45 struct cpufreq_freqs freqs;
46 struct opp *opp;
47 unsigned long volt = 0, volt_old = 0, tol = 0;
48 long freq_Hz, freq_exact;
49 unsigned int index;
50 int ret;
51
52 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
53 relation, &index);
54 if (ret) {
55 pr_err("failed to match target freqency %d: %d\n",
56 target_freq, ret);
57 return ret;
58 }
59
60 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
61 if (freq_Hz < 0)
62 freq_Hz = freq_table[index].frequency * 1000;
63 freq_exact = freq_Hz;
64 freqs.new = freq_Hz / 1000;
65 freqs.old = clk_get_rate(cpu_clk) / 1000;
66
67 if (freqs.old == freqs.new)
68 return 0;
69
70 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
71
72 if (cpu_reg) {
73 rcu_read_lock();
74 opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
75 if (IS_ERR(opp)) {
76 rcu_read_unlock();
77 pr_err("failed to find OPP for %ld\n", freq_Hz);
78 freqs.new = freqs.old;
79 ret = PTR_ERR(opp);
80 goto post_notify;
81 }
82 volt = opp_get_voltage(opp);
83 rcu_read_unlock();
84 tol = volt * voltage_tolerance / 100;
85 volt_old = regulator_get_voltage(cpu_reg);
86 }
87
88 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
89 freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
90 freqs.new / 1000, volt ? volt / 1000 : -1);
91
92
93 if (cpu_reg && freqs.new > freqs.old) {
94 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95 if (ret) {
96 pr_err("failed to scale voltage up: %d\n", ret);
97 freqs.new = freqs.old;
98 goto post_notify;
99 }
100 }
101
102 ret = clk_set_rate(cpu_clk, freq_exact);
103 if (ret) {
104 pr_err("failed to set clock rate: %d\n", ret);
105 if (cpu_reg)
106 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
107 freqs.new = freqs.old;
108 goto post_notify;
109 }
110
111
112 if (cpu_reg && freqs.new < freqs.old) {
113 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
114 if (ret) {
115 pr_err("failed to scale voltage down: %d\n", ret);
116 clk_set_rate(cpu_clk, freqs.old * 1000);
117 freqs.new = freqs.old;
118 }
119 }
120
121post_notify:
122 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
123
124 return ret;
125}
126
127static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
128{
129 int ret;
130
131 ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
132 if (ret) {
133 pr_err("invalid frequency table: %d\n", ret);
134 return ret;
135 }
136
137 policy->cpuinfo.transition_latency = transition_latency;
138 policy->cur = clk_get_rate(cpu_clk) / 1000;
139
140
141
142
143
144
145 cpumask_setall(policy->cpus);
146
147 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
148
149 return 0;
150}
151
152static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
153{
154 cpufreq_frequency_table_put_attr(policy->cpu);
155
156 return 0;
157}
158
159static struct freq_attr *cpu0_cpufreq_attr[] = {
160 &cpufreq_freq_attr_scaling_available_freqs,
161 NULL,
162};
163
164static struct cpufreq_driver cpu0_cpufreq_driver = {
165 .flags = CPUFREQ_STICKY,
166 .verify = cpu0_verify_speed,
167 .target = cpu0_set_target,
168 .get = cpu0_get_speed,
169 .init = cpu0_cpufreq_init,
170 .exit = cpu0_cpufreq_exit,
171 .name = "generic_cpu0",
172 .attr = cpu0_cpufreq_attr,
173};
174
175static int cpu0_cpufreq_probe(struct platform_device *pdev)
176{
177 struct device_node *np, *parent;
178 int ret;
179
180 parent = of_find_node_by_path("/cpus");
181 if (!parent) {
182 pr_err("failed to find OF /cpus\n");
183 return -ENOENT;
184 }
185
186 for_each_child_of_node(parent, np) {
187 if (of_get_property(np, "operating-points", NULL))
188 break;
189 }
190
191 if (!np) {
192 pr_err("failed to find cpu0 node\n");
193 ret = -ENOENT;
194 goto out_put_parent;
195 }
196
197 cpu_dev = &pdev->dev;
198 cpu_dev->of_node = np;
199
200 cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
201 if (IS_ERR(cpu_reg)) {
202
203
204
205
206 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
207 dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
208 ret = -EPROBE_DEFER;
209 goto out_put_node;
210 }
211 pr_warn("failed to get cpu0 regulator: %ld\n",
212 PTR_ERR(cpu_reg));
213 cpu_reg = NULL;
214 }
215
216 cpu_clk = devm_clk_get(cpu_dev, NULL);
217 if (IS_ERR(cpu_clk)) {
218 ret = PTR_ERR(cpu_clk);
219 pr_err("failed to get cpu0 clock: %d\n", ret);
220 goto out_put_node;
221 }
222
223 ret = of_init_opp_table(cpu_dev);
224 if (ret) {
225 pr_err("failed to init OPP table: %d\n", ret);
226 goto out_put_node;
227 }
228
229 ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
230 if (ret) {
231 pr_err("failed to init cpufreq table: %d\n", ret);
232 goto out_put_node;
233 }
234
235 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
236
237 if (of_property_read_u32(np, "clock-latency", &transition_latency))
238 transition_latency = CPUFREQ_ETERNAL;
239
240 if (cpu_reg) {
241 struct opp *opp;
242 unsigned long min_uV, max_uV;
243 int i;
244
245
246
247
248
249
250 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
251 ;
252 rcu_read_lock();
253 opp = opp_find_freq_exact(cpu_dev,
254 freq_table[0].frequency * 1000, true);
255 min_uV = opp_get_voltage(opp);
256 opp = opp_find_freq_exact(cpu_dev,
257 freq_table[i-1].frequency * 1000, true);
258 max_uV = opp_get_voltage(opp);
259 rcu_read_unlock();
260 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
261 if (ret > 0)
262 transition_latency += ret * 1000;
263 }
264
265 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
266 if (ret) {
267 pr_err("failed register driver: %d\n", ret);
268 goto out_free_table;
269 }
270
271 of_node_put(np);
272 of_node_put(parent);
273 return 0;
274
275out_free_table:
276 opp_free_cpufreq_table(cpu_dev, &freq_table);
277out_put_node:
278 of_node_put(np);
279out_put_parent:
280 of_node_put(parent);
281 return ret;
282}
283
284static int cpu0_cpufreq_remove(struct platform_device *pdev)
285{
286 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
287 opp_free_cpufreq_table(cpu_dev, &freq_table);
288
289 return 0;
290}
291
292static struct platform_driver cpu0_cpufreq_platdrv = {
293 .driver = {
294 .name = "cpufreq-cpu0",
295 .owner = THIS_MODULE,
296 },
297 .probe = cpu0_cpufreq_probe,
298 .remove = cpu0_cpufreq_remove,
299};
300module_platform_driver(cpu0_cpufreq_platdrv);
301
302MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
303MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
304MODULE_LICENSE("GPL");
305
