LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <drm/drmP.h>
  25#include "amdgpu.h"
  26#include "amdgpu_ih.h"
  27
  28/**
  29 * amdgpu_ih_ring_init - initialize the IH state
  30 *
  31 * @adev: amdgpu_device pointer
  32 * @ih: ih ring to initialize
  33 * @ring_size: ring size to allocate
  34 * @use_bus_addr: true when we can use dma_alloc_coherent
  35 *
  36 * Initializes the IH state and allocates a buffer
  37 * for the IH ring buffer.
  38 * Returns 0 for success, errors for failure.
  39 */
  40int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
  41                        unsigned ring_size, bool use_bus_addr)
  42{
  43        u32 rb_bufsz;
  44        int r;
  45
  46        /* Align ring size */
  47        rb_bufsz = order_base_2(ring_size / 4);
  48        ring_size = (1 << rb_bufsz) * 4;
  49        ih->ring_size = ring_size;
  50        ih->ptr_mask = ih->ring_size - 1;
  51        ih->rptr = 0;
  52        ih->use_bus_addr = use_bus_addr;
  53
  54        if (use_bus_addr) {
  55                if (ih->ring)
  56                        return 0;
  57
  58                /* add 8 bytes for the rptr/wptr shadows and
  59                 * add them to the end of the ring allocation.
  60                 */
  61                ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
  62                                              &ih->rb_dma_addr, GFP_KERNEL);
  63                if (ih->ring == NULL)
  64                        return -ENOMEM;
  65
  66                memset((void *)ih->ring, 0, ih->ring_size + 8);
  67                ih->wptr_offs = (ih->ring_size / 4) + 0;
  68                ih->rptr_offs = (ih->ring_size / 4) + 1;
  69        } else {
  70                r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
  71                if (r)
  72                        return r;
  73
  74                r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
  75                if (r) {
  76                        amdgpu_device_wb_free(adev, ih->wptr_offs);
  77                        return r;
  78                }
  79
  80                r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
  81                                            AMDGPU_GEM_DOMAIN_GTT,
  82                                            &ih->ring_obj, &ih->gpu_addr,
  83                                            (void **)&ih->ring);
  84                if (r) {
  85                        amdgpu_device_wb_free(adev, ih->rptr_offs);
  86                        amdgpu_device_wb_free(adev, ih->wptr_offs);
  87                        return r;
  88                }
  89        }
  90        return 0;
  91}
  92
  93/**
  94 * amdgpu_ih_ring_fini - tear down the IH state
  95 *
  96 * @adev: amdgpu_device pointer
  97 * @ih: ih ring to tear down
  98 *
  99 * Tears down the IH state and frees buffer
 100 * used for the IH ring buffer.
 101 */
 102void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 103{
 104        if (ih->use_bus_addr) {
 105                if (!ih->ring)
 106                        return;
 107
 108                /* add 8 bytes for the rptr/wptr shadows and
 109                 * add them to the end of the ring allocation.
 110                 */
 111                dma_free_coherent(adev->dev, ih->ring_size + 8,
 112                                  (void *)ih->ring, ih->rb_dma_addr);
 113                ih->ring = NULL;
 114        } else {
 115                amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
 116                                      (void **)&ih->ring);
 117                amdgpu_device_wb_free(adev, ih->wptr_offs);
 118                amdgpu_device_wb_free(adev, ih->rptr_offs);
 119        }
 120}
 121
 122/**
 123 * amdgpu_ih_process - interrupt handler
 124 *
 125 * @adev: amdgpu_device pointer
 126 * @ih: ih ring to process
 127 *
 128 * Interrupt hander (VI), walk the IH ring.
 129 * Returns irq process return code.
 130 */
 131int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
 132                      void (*callback)(struct amdgpu_device *adev,
 133                                       struct amdgpu_ih_ring *ih))
 134{
 135        u32 wptr;
 136
 137        if (!ih->enabled || adev->shutdown)
 138                return IRQ_NONE;
 139
 140        wptr = amdgpu_ih_get_wptr(adev);
 141
 142restart_ih:
 143        /* is somebody else already processing irqs? */
 144        if (atomic_xchg(&ih->lock, 1))
 145                return IRQ_NONE;
 146
 147        DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
 148
 149        /* Order reading of wptr vs. reading of IH ring data */
 150        rmb();
 151
 152        while (ih->rptr != wptr) {
 153                callback(adev, ih);
 154                ih->rptr &= ih->ptr_mask;
 155        }
 156
 157        amdgpu_ih_set_rptr(adev);
 158        atomic_set(&ih->lock, 0);
 159
 160        /* make sure wptr hasn't changed while processing */
 161        wptr = amdgpu_ih_get_wptr(adev);
 162        if (wptr != ih->rptr)
 163                goto restart_ih;
 164
 165        return IRQ_HANDLED;
 166}
 167
 168