LXR linux/drivers/gpu/drm/amd/include/kgd_kfd

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23/*
  24 * This file defines the private interface between the
  25 * AMD kernel graphics drivers and the AMD KFD.
  26 */
  27
  28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
  29#define KGD_KFD_INTERFACE_H_INCLUDED
  30
  31#include <linux/types.h>
  32#include <linux/bitmap.h>
  33#include <linux/dma-fence.h>
  34
  35struct pci_dev;
  36
  37#define KFD_INTERFACE_VERSION 2
  38#define KGD_MAX_QUEUES 128
  39
  40struct kfd_dev;
  41struct kgd_dev;
  42
  43struct kgd_mem;
  44
  45enum kfd_preempt_type {
  46        KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
  47        KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  48};
  49
  50struct kfd_vm_fault_info {
  51        uint64_t        page_addr;
  52        uint32_t        vmid;
  53        uint32_t        mc_id;
  54        uint32_t        status;
  55        bool            prot_valid;
  56        bool            prot_read;
  57        bool            prot_write;
  58        bool            prot_exec;
  59};
  60
  61struct kfd_cu_info {
  62        uint32_t num_shader_engines;
  63        uint32_t num_shader_arrays_per_engine;
  64        uint32_t num_cu_per_sh;
  65        uint32_t cu_active_number;
  66        uint32_t cu_ao_mask;
  67        uint32_t simd_per_cu;
  68        uint32_t max_waves_per_simd;
  69        uint32_t wave_front_size;
  70        uint32_t max_scratch_slots_per_cu;
  71        uint32_t lds_size;
  72        uint32_t cu_bitmap[4][4];
  73};
  74
  75/* For getting GPU local memory information from KGD */
  76struct kfd_local_mem_info {
  77        uint64_t local_mem_size_private;
  78        uint64_t local_mem_size_public;
  79        uint32_t vram_width;
  80        uint32_t mem_clk_max;
  81};
  82
  83enum kgd_memory_pool {
  84        KGD_POOL_SYSTEM_CACHEABLE = 1,
  85        KGD_POOL_SYSTEM_WRITECOMBINE = 2,
  86        KGD_POOL_FRAMEBUFFER = 3,
  87};
  88
  89enum kgd_engine_type {
  90        KGD_ENGINE_PFP = 1,
  91        KGD_ENGINE_ME,
  92        KGD_ENGINE_CE,
  93        KGD_ENGINE_MEC1,
  94        KGD_ENGINE_MEC2,
  95        KGD_ENGINE_RLC,
  96        KGD_ENGINE_SDMA1,
  97        KGD_ENGINE_SDMA2,
  98        KGD_ENGINE_MAX
  99};
 100
 101/**
 102 * enum kfd_sched_policy
 103 *
 104 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
 105 * scheduling. In this scheduling mode we're using the firmware code to
 106 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
 107 * the HIQ queue is used as a special queue that dispatches the configuration
 108 * to the cp and the user mode queues list that are currently running.
 109 * the DIQ queue is a debugging queue that dispatches debugging commands to the
 110 * firmware.
 111 * in this scheduling mode user mode queues over subscription feature is
 112 * enabled.
 113 *
 114 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
 115 * subscription feature disabled.
 116 *
 117 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
 118 * set the command processor registers and sets the queues "manually". This
 119 * mode is used *ONLY* for debugging proposes.
 120 *
 121 */
 122enum kfd_sched_policy {
 123        KFD_SCHED_POLICY_HWS = 0,
 124        KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
 125        KFD_SCHED_POLICY_NO_HWS
 126};
 127
 128struct kgd2kfd_shared_resources {
 129        /* Bit n == 1 means VMID n is available for KFD. */
 130        unsigned int compute_vmid_bitmap;
 131
 132        /* number of pipes per mec */
 133        uint32_t num_pipe_per_mec;
 134
 135        /* number of queues per pipe */
 136        uint32_t num_queue_per_pipe;
 137
 138        /* Bit n == 1 means Queue n is available for KFD */
 139        DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
 140
 141        /* Doorbell assignments (SOC15 and later chips only). Only
 142         * specific doorbells are routed to each SDMA engine. Others
 143         * are routed to IH and VCN. They are not usable by the CP.
 144         *
 145         * Any doorbell number D that satisfies the following condition
 146         * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
 147         *
 148         * KFD currently uses 1024 (= 0x3ff) doorbells per process. If
 149         * doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
 150         * mask would be set to 0x1e0 and val set to 0x0e0.
 151         */
 152        unsigned int sdma_doorbell[2][8];
 153        unsigned int reserved_doorbell_mask;
 154        unsigned int reserved_doorbell_val;
 155
 156        /* Base address of doorbell aperture. */
 157        phys_addr_t doorbell_physical_address;
 158
 159        /* Size in bytes of doorbell aperture. */
 160        size_t doorbell_aperture_size;
 161
 162        /* Number of bytes at start of aperture reserved for KGD. */
 163        size_t doorbell_start_offset;
 164
 165        /* GPUVM address space size in bytes */
 166        uint64_t gpuvm_size;
 167
 168        /* Minor device number of the render node */
 169        int drm_render_minor;
 170};
 171
 172struct tile_config {
 173        uint32_t *tile_config_ptr;
 174        uint32_t *macro_tile_config_ptr;
 175        uint32_t num_tile_configs;
 176        uint32_t num_macro_tile_configs;
 177
 178        uint32_t gb_addr_config;
 179        uint32_t num_banks;
 180        uint32_t num_ranks;
 181};
 182
 183#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
 184
 185/*
 186 * Allocation flag domains
 187 * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
 188 */
 189#define ALLOC_MEM_FLAGS_VRAM            (1 << 0)
 190#define ALLOC_MEM_FLAGS_GTT             (1 << 1)
 191#define ALLOC_MEM_FLAGS_USERPTR         (1 << 2)
 192#define ALLOC_MEM_FLAGS_DOORBELL        (1 << 3)
 193
 194/*
 195 * Allocation flags attributes/access options.
 196 * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
 197 */
 198#define ALLOC_MEM_FLAGS_WRITABLE        (1 << 31)
 199#define ALLOC_MEM_FLAGS_EXECUTABLE      (1 << 30)
 200#define ALLOC_MEM_FLAGS_PUBLIC          (1 << 29)
 201#define ALLOC_MEM_FLAGS_NO_SUBSTITUTE   (1 << 28) /* TODO */
 202#define ALLOC_MEM_FLAGS_AQL_QUEUE_MEM   (1 << 27)
 203#define ALLOC_MEM_FLAGS_COHERENT        (1 << 26) /* For GFXv9 or later */
 204
 205/**
 206 * struct kfd2kgd_calls
 207 *
 208 * @program_sh_mem_settings: A function that should initiate the memory
 209 * properties such as main aperture memory type (cache / non cached) and
 210 * secondary aperture base address, size and memory type.
 211 * This function is used only for no cp scheduling mode.
 212 *
 213 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
 214 * scheduling mode. Only used for no cp scheduling mode.
 215 *
 216 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
 217 * sceduling mode.
 218 *
 219 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
 220 * used only for no HWS mode.
 221 *
 222 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
 223 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
 224 *
 225 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
 226 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
 227 *
 228 * @hqd_is_occupies: Checks if a hqd slot is occupied.
 229 *
 230 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
 231 *
 232 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
 233 *
 234 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
 235 * SDMA hqd slot.
 236 *
 237 * @get_fw_version: Returns FW versions from the header
 238 *
 239 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
 240 * Only used for no cp scheduling mode
 241 *
 242 * @get_tile_config: Returns GPU-specific tiling mode information
 243 *
 244 * @set_vm_context_page_table_base: Program page table base for a VMID
 245 *
 246 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
 247 *
 248 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
 249 *
 250 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
 251 * IH ring entry. This function allows the KFD ISR to get the VMID
 252 * from the fault status register as early as possible.
 253 *
 254 * @get_hive_id: Returns hive id of current  device,  0 if xgmi is not enabled
 255 *
 256 * This structure contains function pointers to services that the kgd driver
 257 * provides to amdkfd driver.
 258 *
 259 */
 260struct kfd2kgd_calls {
 261        /* Register access functions */
 262        void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
 263                        uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
 264                        uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
 265
 266        int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
 267                                        unsigned int vmid);
 268
 269        int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
 270
 271        int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 272                        uint32_t queue_id, uint32_t __user *wptr,
 273                        uint32_t wptr_shift, uint32_t wptr_mask,
 274                        struct mm_struct *mm);
 275
 276        int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
 277                             uint32_t __user *wptr, struct mm_struct *mm);
 278
 279        int (*hqd_dump)(struct kgd_dev *kgd,
 280                        uint32_t pipe_id, uint32_t queue_id,
 281                        uint32_t (**dump)[2], uint32_t *n_regs);
 282
 283        int (*hqd_sdma_dump)(struct kgd_dev *kgd,
 284                             uint32_t engine_id, uint32_t queue_id,
 285                             uint32_t (**dump)[2], uint32_t *n_regs);
 286
 287        bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
 288                                uint32_t pipe_id, uint32_t queue_id);
 289
 290        int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
 291                                unsigned int timeout, uint32_t pipe_id,
 292                                uint32_t queue_id);
 293
 294        bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
 295
 296        int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
 297                                unsigned int timeout);
 298
 299        int (*address_watch_disable)(struct kgd_dev *kgd);
 300        int (*address_watch_execute)(struct kgd_dev *kgd,
 301                                        unsigned int watch_point_id,
 302                                        uint32_t cntl_val,
 303                                        uint32_t addr_hi,
 304                                        uint32_t addr_lo);
 305        int (*wave_control_execute)(struct kgd_dev *kgd,
 306                                        uint32_t gfx_index_val,
 307                                        uint32_t sq_cmd);
 308        uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
 309                                        unsigned int watch_point_id,
 310                                        unsigned int reg_offset);
 311        bool (*get_atc_vmid_pasid_mapping_valid)(
 312                                        struct kgd_dev *kgd,
 313                                        uint8_t vmid);
 314        uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
 315                                        struct kgd_dev *kgd,
 316                                        uint8_t vmid);
 317
 318        uint16_t (*get_fw_version)(struct kgd_dev *kgd,
 319                                enum kgd_engine_type type);
 320        void (*set_scratch_backing_va)(struct kgd_dev *kgd,
 321                                uint64_t va, uint32_t vmid);
 322        int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
 323
 324        void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
 325                        uint32_t vmid, uint64_t page_table_base);
 326        int (*invalidate_tlbs)(struct kgd_dev *kgd, uint16_t pasid);
 327        int (*invalidate_tlbs_vmid)(struct kgd_dev *kgd, uint16_t vmid);
 328        uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
 329        uint64_t (*get_hive_id)(struct kgd_dev *kgd);
 330
 331};
 332
 333/**
 334 * struct kgd2kfd_calls
 335 *
 336 * @exit: Notifies amdkfd that kgd module is unloaded
 337 *
 338 * @probe: Notifies amdkfd about a probe done on a device in the kgd driver.
 339 *
 340 * @device_init: Initialize the newly probed device (if it is a device that
 341 * amdkfd supports)
 342 *
 343 * @device_exit: Notifies amdkfd about a removal of a kgd device
 344 *
 345 * @suspend: Notifies amdkfd about a suspend action done to a kgd device
 346 *
 347 * @resume: Notifies amdkfd about a resume action done to a kgd device
 348 *
 349 * @quiesce_mm: Quiesce all user queue access to specified MM address space
 350 *
 351 * @resume_mm: Resume user queue access to specified MM address space
 352 *
 353 * @schedule_evict_and_restore_process: Schedules work queue that will prepare
 354 * for safe eviction of KFD BOs that belong to the specified process.
 355 *
 356 * @pre_reset: Notifies amdkfd that amdgpu about to reset the gpu
 357 *
 358 * @post_reset: Notify amdkfd that amgpu successfully reseted the gpu
 359 *
 360 * This structure contains function callback pointers so the kgd driver
 361 * will notify to the amdkfd about certain status changes.
 362 *
 363 */
 364struct kgd2kfd_calls {
 365        void (*exit)(void);
 366        struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev,
 367                const struct kfd2kgd_calls *f2g);
 368        bool (*device_init)(struct kfd_dev *kfd,
 369                        const struct kgd2kfd_shared_resources *gpu_resources);
 370        void (*device_exit)(struct kfd_dev *kfd);
 371        void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry);
 372        void (*suspend)(struct kfd_dev *kfd);
 373        int (*resume)(struct kfd_dev *kfd);
 374        int (*quiesce_mm)(struct mm_struct *mm);
 375        int (*resume_mm)(struct mm_struct *mm);
 376        int (*schedule_evict_and_restore_process)(struct mm_struct *mm,
 377                        struct dma_fence *fence);
 378        int  (*pre_reset)(struct kfd_dev *kfd);
 379        int  (*post_reset)(struct kfd_dev *kfd);
 380};
 381
 382int kgd2kfd_init(unsigned interface_version,
 383                const struct kgd2kfd_calls **g2f);
 384
 385#endif  /* KGD_KFD_INTERFACE_H_INCLUDED */
 386