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25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/slab.h>
28#include <linux/types.h>
29
30#include "dvb_frontend.h"
31#include "it913x-fe.h"
32#include "it913x-fe-priv.h"
33
34static int it913x_debug;
35
36module_param_named(debug, it913x_debug, int, 0644);
37MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
38
39#define dprintk(level, args...) do { \
40 if (level & it913x_debug) \
41 printk(KERN_DEBUG "it913x-fe: " args); \
42} while (0)
43
44#define deb_info(args...) dprintk(0x01, args)
45#define debug_data_snipet(level, name, p) \
46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \
48 *(p+5), *(p+6), *(p+7));
49#define info(format, arg...) \
50 printk(KERN_INFO "it913x-fe: " format "\n" , ## arg)
51
52struct it913x_fe_state {
53 struct dvb_frontend frontend;
54 struct i2c_adapter *i2c_adap;
55 struct ite_config *config;
56 u8 i2c_addr;
57 u32 frequency;
58 fe_modulation_t constellation;
59 fe_transmit_mode_t transmission_mode;
60 u8 priority;
61 u32 crystalFrequency;
62 u32 adcFrequency;
63 u8 tuner_type;
64 struct adctable *table;
65 fe_status_t it913x_status;
66 u16 tun_xtal;
67 u8 tun_fdiv;
68 u8 tun_clk_mode;
69 u32 tun_fn_min;
70 u32 ucblocks;
71};
72
73static int it913x_read_reg(struct it913x_fe_state *state,
74 u32 reg, u8 *data, u8 count)
75{
76 int ret;
77 u8 pro = PRO_DMOD;
78 u8 b[4];
79 struct i2c_msg msg[2] = {
80 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
81 .buf = b, .len = sizeof(b) },
82 { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD,
83 .buf = data, .len = count }
84 };
85 b[0] = (u8) reg >> 24;
86 b[1] = (u8)(reg >> 16) & 0xff;
87 b[2] = (u8)(reg >> 8) & 0xff;
88 b[3] = (u8) reg & 0xff;
89
90 ret = i2c_transfer(state->i2c_adap, msg, 2);
91
92 return ret;
93}
94
95static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg)
96{
97 int ret;
98 u8 b[1];
99 ret = it913x_read_reg(state, reg, &b[0], sizeof(b));
100 return (ret < 0) ? -ENODEV : b[0];
101}
102
103static int it913x_write(struct it913x_fe_state *state,
104 u8 pro, u32 reg, u8 buf[], u8 count)
105{
106 u8 b[256];
107 struct i2c_msg msg[1] = {
108 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
109 .buf = b, .len = count + 4 }
110 };
111 int ret;
112
113 b[0] = (u8) reg >> 24;
114 b[1] = (u8)(reg >> 16) & 0xff;
115 b[2] = (u8)(reg >> 8) & 0xff;
116 b[3] = (u8) reg & 0xff;
117 memcpy(&b[4], buf, count);
118
119 ret = i2c_transfer(state->i2c_adap, msg, 1);
120
121 if (ret < 0)
122 return -EIO;
123
124 return 0;
125}
126
127static int it913x_write_reg(struct it913x_fe_state *state,
128 u8 pro, u32 reg, u32 data)
129{
130 int ret;
131 u8 b[4];
132 u8 s;
133
134 b[0] = data >> 24;
135 b[1] = (data >> 16) & 0xff;
136 b[2] = (data >> 8) & 0xff;
137 b[3] = data & 0xff;
138
139 if (data < 0x100)
140 s = 3;
141 else if (data < 0x1000)
142 s = 2;
143 else if (data < 0x100000)
144 s = 1;
145 else
146 s = 0;
147
148 ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s);
149
150 return ret;
151}
152
153static int it913x_fe_script_loader(struct it913x_fe_state *state,
154 struct it913xset *loadscript)
155{
156 int ret, i;
157 if (loadscript == NULL)
158 return -EINVAL;
159
160 for (i = 0; i < 1000; ++i) {
161 if (loadscript[i].pro == 0xff)
162 break;
163 ret = it913x_write(state, loadscript[i].pro,
164 loadscript[i].address,
165 loadscript[i].reg, loadscript[i].count);
166 if (ret < 0)
167 return -ENODEV;
168 }
169 return 0;
170}
171
172static int it913x_init_tuner(struct it913x_fe_state *state)
173{
174 int ret, i, reg;
175 u8 val, nv_val;
176 u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
177 u8 b[2];
178
179 reg = it913x_read_reg_u8(state, 0xec86);
180 switch (reg) {
181 case 0:
182 state->tun_clk_mode = reg;
183 state->tun_xtal = 2000;
184 state->tun_fdiv = 3;
185 val = 16;
186 break;
187 case -ENODEV:
188 return -ENODEV;
189 case 1:
190 default:
191 state->tun_clk_mode = reg;
192 state->tun_xtal = 640;
193 state->tun_fdiv = 1;
194 val = 6;
195 break;
196 }
197
198 reg = it913x_read_reg_u8(state, 0xed03);
199
200 if (reg < 0)
201 return -ENODEV;
202 else if (reg < ARRAY_SIZE(nv))
203 nv_val = nv[reg];
204 else
205 nv_val = 2;
206
207 for (i = 0; i < 50; i++) {
208 ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b));
209 reg = (b[1] << 8) + b[0];
210 if (reg > 0)
211 break;
212 if (ret < 0)
213 return -ENODEV;
214 udelay(2000);
215 }
216 state->tun_fn_min = state->tun_xtal * reg;
217 state->tun_fn_min /= (state->tun_fdiv * nv_val);
218 deb_info("Tuner fn_min %d", state->tun_fn_min);
219
220 if (state->config->chip_ver > 1)
221 msleep(50);
222 else {
223 for (i = 0; i < 50; i++) {
224 reg = it913x_read_reg_u8(state, 0xec82);
225 if (reg > 0)
226 break;
227 if (reg < 0)
228 return -ENODEV;
229 udelay(2000);
230 }
231 }
232
233 return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
234}
235
236static int it9137_set_tuner(struct it913x_fe_state *state,
237 u32 bandwidth, u32 frequency_m)
238{
239 struct it913xset *set_tuner = set_it9137_template;
240 int ret, reg;
241 u32 frequency = frequency_m / 1000;
242 u32 freq, temp_f, tmp;
243 u16 iqik_m_cal;
244 u16 n_div;
245 u8 n;
246 u8 l_band;
247 u8 lna_band;
248 u8 bw;
249
250 if (state->config->firmware_ver == 1)
251 set_tuner = set_it9135_template;
252 else
253 set_tuner = set_it9137_template;
254
255 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
256
257 if (frequency >= 51000 && frequency <= 440000) {
258 l_band = 0;
259 lna_band = 0;
260 } else if (frequency > 440000 && frequency <= 484000) {
261 l_band = 1;
262 lna_band = 1;
263 } else if (frequency > 484000 && frequency <= 533000) {
264 l_band = 1;
265 lna_band = 2;
266 } else if (frequency > 533000 && frequency <= 587000) {
267 l_band = 1;
268 lna_band = 3;
269 } else if (frequency > 587000 && frequency <= 645000) {
270 l_band = 1;
271 lna_band = 4;
272 } else if (frequency > 645000 && frequency <= 710000) {
273 l_band = 1;
274 lna_band = 5;
275 } else if (frequency > 710000 && frequency <= 782000) {
276 l_band = 1;
277 lna_band = 6;
278 } else if (frequency > 782000 && frequency <= 860000) {
279 l_band = 1;
280 lna_band = 7;
281 } else if (frequency > 1450000 && frequency <= 1492000) {
282 l_band = 1;
283 lna_band = 0;
284 } else if (frequency > 1660000 && frequency <= 1685000) {
285 l_band = 1;
286 lna_band = 1;
287 } else
288 return -EINVAL;
289 set_tuner[0].reg[0] = lna_band;
290
291 switch (bandwidth) {
292 case 5000000:
293 bw = 0;
294 break;
295 case 6000000:
296 bw = 2;
297 break;
298 case 7000000:
299 bw = 4;
300 break;
301 default:
302 case 8000000:
303 bw = 6;
304 break;
305 }
306
307 set_tuner[1].reg[0] = bw;
308 set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
309
310 if (frequency > 53000 && frequency <= 74000) {
311 n_div = 48;
312 n = 0;
313 } else if (frequency > 74000 && frequency <= 111000) {
314 n_div = 32;
315 n = 1;
316 } else if (frequency > 111000 && frequency <= 148000) {
317 n_div = 24;
318 n = 2;
319 } else if (frequency > 148000 && frequency <= 222000) {
320 n_div = 16;
321 n = 3;
322 } else if (frequency > 222000 && frequency <= 296000) {
323 n_div = 12;
324 n = 4;
325 } else if (frequency > 296000 && frequency <= 445000) {
326 n_div = 8;
327 n = 5;
328 } else if (frequency > 445000 && frequency <= state->tun_fn_min) {
329 n_div = 6;
330 n = 6;
331 } else if (frequency > state->tun_fn_min && frequency <= 950000) {
332 n_div = 4;
333 n = 7;
334 } else if (frequency > 1450000 && frequency <= 1680000) {
335 n_div = 2;
336 n = 0;
337 } else
338 return -EINVAL;
339
340 reg = it913x_read_reg_u8(state, 0xed81);
341 iqik_m_cal = (u16)reg * n_div;
342
343 if (reg < 0x20) {
344 if (state->tun_clk_mode == 0)
345 iqik_m_cal = (iqik_m_cal * 9) >> 5;
346 else
347 iqik_m_cal >>= 1;
348 } else {
349 iqik_m_cal = 0x40 - iqik_m_cal;
350 if (state->tun_clk_mode == 0)
351 iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
352 else
353 iqik_m_cal = ~(iqik_m_cal >> 1);
354 }
355
356 temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv;
357 freq = temp_f / state->tun_xtal;
358 tmp = freq * state->tun_xtal;
359
360 if ((temp_f - tmp) >= (state->tun_xtal >> 1))
361 freq++;
362
363 freq += (u32) n << 13;
364
365 temp_f = freq + (u32)iqik_m_cal;
366
367 set_tuner[3].reg[0] = temp_f & 0xff;
368 set_tuner[4].reg[0] = (temp_f >> 8) & 0xff;
369
370 deb_info("High Frequency = %04x", temp_f);
371
372
373 set_tuner[5].reg[0] = freq & 0xff;
374 set_tuner[6].reg[0] = (freq >> 8) & 0xff;
375
376 deb_info("low Frequency = %04x", freq);
377
378 ret = it913x_fe_script_loader(state, set_tuner);
379
380 return (ret < 0) ? -ENODEV : 0;
381}
382
383static int it913x_fe_select_bw(struct it913x_fe_state *state,
384 u32 bandwidth, u32 adcFrequency)
385{
386 int ret, i;
387 u8 buffer[256];
388 u32 coeff[8];
389 u16 bfsfcw_fftinx_ratio;
390 u16 fftinx_bfsfcw_ratio;
391 u8 count;
392 u8 bw;
393 u8 adcmultiplier;
394
395 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
396
397 switch (bandwidth) {
398 case 5000000:
399 bw = 3;
400 break;
401 case 6000000:
402 bw = 0;
403 break;
404 case 7000000:
405 bw = 1;
406 break;
407 default:
408 case 8000000:
409 bw = 2;
410 break;
411 }
412 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
413
414 if (state->table == NULL)
415 return -EINVAL;
416
417
418 coeff[0] = state->table[bw].coeff_1_2048;
419 coeff[1] = state->table[bw].coeff_2_2k;
420 coeff[2] = state->table[bw].coeff_1_8191;
421 coeff[3] = state->table[bw].coeff_1_8192;
422 coeff[4] = state->table[bw].coeff_1_8193;
423 coeff[5] = state->table[bw].coeff_2_8k;
424 coeff[6] = state->table[bw].coeff_1_4096;
425 coeff[7] = state->table[bw].coeff_2_4k;
426 bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio;
427 fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio;
428
429
430 ret = it913x_read_reg_u8(state, ADC_X_2);
431 if (ret < 0)
432 return -EINVAL;
433
434 adcmultiplier = ret;
435
436 count = 0;
437
438
439 for (i = 0; i < 8; i++) {
440 if (adcmultiplier == 1)
441 coeff[i] /= 2;
442 buffer[count++] = (coeff[i] >> 24) & 0x3;
443 buffer[count++] = (coeff[i] >> 16) & 0xff;
444 buffer[count++] = (coeff[i] >> 8) & 0xff;
445 buffer[count++] = coeff[i] & 0xff;
446 }
447
448
449 buffer[count++] = bfsfcw_fftinx_ratio & 0xff;
450 buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff;
451
452 buffer[count++] = fftinx_bfsfcw_ratio & 0xff;
453 buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff;
454
455 ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count);
456
457 for (i = 0; i < 42; i += 8)
458 debug_data_snipet(0x1, "Buffer", &buffer[i]);
459
460 return ret;
461}
462
463
464
465static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status)
466{
467 struct it913x_fe_state *state = fe->demodulator_priv;
468 int ret, i;
469 fe_status_t old_status = state->it913x_status;
470 *status = 0;
471
472 if (state->it913x_status == 0) {
473 ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
474 if (ret == 0x1) {
475 *status |= FE_HAS_SIGNAL;
476 for (i = 0; i < 40; i++) {
477 ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK);
478 if (ret == 0x1)
479 break;
480 msleep(25);
481 }
482 if (ret == 0x1)
483 *status |= FE_HAS_CARRIER
484 | FE_HAS_VITERBI
485 | FE_HAS_SYNC;
486 state->it913x_status = *status;
487 }
488 }
489
490 if (state->it913x_status & FE_HAS_SYNC) {
491 ret = it913x_read_reg_u8(state, TPSD_LOCK);
492 if (ret == 0x1)
493 *status |= FE_HAS_LOCK
494 | state->it913x_status;
495 else
496 state->it913x_status = 0;
497 if (old_status != state->it913x_status)
498 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret);
499 }
500
501 return 0;
502}
503
504
505int it913x_qpsk_pval[] = {0, -93, -91, -90, 0, -89, -88};
506int it913x_16qam_pval[] = {0, -87, -85, -84, 0, -83, -82};
507int it913x_64qam_pval[] = {0, -82, -80, -78, 0, -77, -76};
508
509static int it913x_get_signal_strength(struct dvb_frontend *fe)
510{
511 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
512 struct it913x_fe_state *state = fe->demodulator_priv;
513 u8 code_rate;
514 int ret, temp;
515 u8 lna_gain_os;
516
517 ret = it913x_read_reg_u8(state, VAR_P_INBAND);
518 if (ret < 0)
519 return ret;
520
521
522 if (state->frequency < 300000000)
523 lna_gain_os = 7;
524 else
525 lna_gain_os = 14;
526
527 temp = (ret - 100) - lna_gain_os;
528
529 if (state->priority == PRIORITY_HIGH)
530 code_rate = p->code_rate_HP;
531 else
532 code_rate = p->code_rate_LP;
533
534 if (code_rate >= ARRAY_SIZE(it913x_qpsk_pval))
535 return -EINVAL;
536
537 deb_info("Reg VAR_P_INBAND:%d Calc Offset Value:%d", ret, temp);
538
539
540 switch (p->modulation) {
541 case QPSK:
542 temp -= it913x_qpsk_pval[code_rate];
543 break;
544 case QAM_16:
545 temp -= it913x_16qam_pval[code_rate];
546 break;
547 case QAM_64:
548 temp -= it913x_64qam_pval[code_rate];
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 if (temp < -15)
555 ret = 0;
556 else if ((-15 <= temp) && (temp < 0))
557 ret = (2 * (temp + 15)) / 3;
558 else if ((0 <= temp) && (temp < 20))
559 ret = 4 * temp + 10;
560 else if ((20 <= temp) && (temp < 35))
561 ret = (2 * (temp - 20)) / 3 + 90;
562 else if (temp >= 35)
563 ret = 100;
564
565 deb_info("Signal Strength :%d", ret);
566
567 return ret;
568}
569
570static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
571 u16 *strength)
572{
573 struct it913x_fe_state *state = fe->demodulator_priv;
574 int ret = 0;
575 if (state->config->read_slevel) {
576 if (state->it913x_status & FE_HAS_SIGNAL)
577 ret = it913x_read_reg_u8(state, SIGNAL_LEVEL);
578 } else
579 ret = it913x_get_signal_strength(fe);
580
581 if (ret >= 0)
582 *strength = (u16)((u32)ret * 0xffff / 0x64);
583
584 return (ret < 0) ? -ENODEV : 0;
585}
586
587static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
588{
589 struct it913x_fe_state *state = fe->demodulator_priv;
590 int ret;
591 u8 reg[3];
592 u32 snr_val, snr_min, snr_max;
593 u32 temp;
594
595 ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg));
596
597 snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0];
598
599 ret |= it913x_read_reg(state, 0xf78b, reg, 1);
600 if (reg[0])
601 snr_val /= reg[0];
602
603 if (state->transmission_mode == TRANSMISSION_MODE_2K)
604 snr_val *= 4;
605 else if (state->transmission_mode == TRANSMISSION_MODE_4K)
606 snr_val *= 2;
607
608 if (state->constellation == QPSK) {
609 snr_min = 0xb4711;
610 snr_max = 0x191451;
611 } else if (state->constellation == QAM_16) {
612 snr_min = 0x4f0d5;
613 snr_max = 0xc7925;
614 } else if (state->constellation == QAM_64) {
615 snr_min = 0x256d0;
616 snr_max = 0x626be;
617 } else
618 return -EINVAL;
619
620 if (snr_val < snr_min)
621 *snr = 0;
622 else if (snr_val < snr_max) {
623 temp = (snr_val - snr_min) >> 5;
624 temp *= 0xffff;
625 temp /= (snr_max - snr_min) >> 5;
626 *snr = (u16)temp;
627 } else
628 *snr = 0xffff;
629
630 return (ret < 0) ? -ENODEV : 0;
631}
632
633static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
634{
635 struct it913x_fe_state *state = fe->demodulator_priv;
636 u8 reg[5];
637
638 it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
639 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
640 *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2];
641 return 0;
642}
643
644static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
645{
646 struct it913x_fe_state *state = fe->demodulator_priv;
647 int ret;
648 u8 reg[2];
649
650 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
651 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
652 *ucblocks = state->ucblocks;
653 return ret;
654}
655
656static int it913x_fe_get_frontend(struct dvb_frontend *fe)
657{
658 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
659 struct it913x_fe_state *state = fe->demodulator_priv;
660 u8 reg[8];
661
662 it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
663
664 if (reg[3] < 3)
665 p->modulation = fe_con[reg[3]];
666
667 if (reg[0] < 3)
668 p->transmission_mode = fe_mode[reg[0]];
669
670 if (reg[1] < 4)
671 p->guard_interval = fe_gi[reg[1]];
672
673 if (reg[2] < 4)
674 p->hierarchy = fe_hi[reg[2]];
675
676 state->priority = reg[5];
677
678 p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
679 p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
680
681
682 state->constellation = p->modulation;
683 state->transmission_mode = p->transmission_mode;
684
685 return 0;
686}
687
688static int it913x_fe_set_frontend(struct dvb_frontend *fe)
689{
690 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
691 struct it913x_fe_state *state = fe->demodulator_priv;
692 int i;
693 u8 empty_ch, last_ch;
694
695 state->it913x_status = 0;
696
697
698 it913x_fe_select_bw(state, p->bandwidth_hz,
699 state->adcFrequency);
700
701
702 it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0);
703
704
705 it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0);
706
707
708 it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0);
709
710 it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
711
712 if ((p->frequency >= 51000000) && (p->frequency <= 230000000))
713 i = 0;
714 else if ((p->frequency >= 350000000) && (p->frequency <= 900000000))
715 i = 1;
716 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
717 i = 2;
718 else
719 return -EOPNOTSUPP;
720
721 it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
722
723 deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
724 switch (state->tuner_type) {
725 case IT9135_38:
726 case IT9135_51:
727 case IT9135_52:
728 case IT9135_60:
729 case IT9135_61:
730 case IT9135_62:
731 it9137_set_tuner(state,
732 p->bandwidth_hz, p->frequency);
733 break;
734 default:
735 if (fe->ops.tuner_ops.set_params) {
736 fe->ops.tuner_ops.set_params(fe);
737 if (fe->ops.i2c_gate_ctrl)
738 fe->ops.i2c_gate_ctrl(fe, 0);
739 }
740 break;
741 }
742
743 it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
744
745 it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
746 last_ch = 2;
747 for (i = 0; i < 40; ++i) {
748 empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
749 if (last_ch == 1 && empty_ch == 1)
750 break;
751 if (last_ch == 2 && empty_ch == 2)
752 return 0;
753 last_ch = empty_ch;
754 msleep(25);
755 }
756 for (i = 0; i < 40; ++i) {
757 if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1)
758 break;
759 msleep(25);
760 }
761
762 state->frequency = p->frequency;
763 return 0;
764}
765
766static int it913x_fe_suspend(struct it913x_fe_state *state)
767{
768 int ret, i;
769 u8 b;
770
771 ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1);
772
773 ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
774
775 for (i = 0; i < 128; i++) {
776 ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1);
777 if (ret < 0)
778 return -ENODEV;
779 if (b == 0)
780 break;
781
782 }
783
784 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8);
785
786 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
787
788 ret |= it913x_fe_script_loader(state, it9137_tuner_off);
789
790 return (ret < 0) ? -ENODEV : 0;
791}
792
793
794
795
796
797static int it913x_fe_sleep(struct dvb_frontend *fe)
798{
799 struct it913x_fe_state *state = fe->demodulator_priv;
800 return it913x_fe_suspend(state);
801}
802
803static u32 compute_div(u32 a, u32 b, u32 x)
804{
805 u32 res = 0;
806 u32 c = 0;
807 u32 i = 0;
808
809 if (a > b) {
810 c = a / b;
811 a = a - c * b;
812 }
813
814 for (i = 0; i < x; i++) {
815 if (a >= b) {
816 res += 1;
817 a -= b;
818 }
819 a <<= 1;
820 res <<= 1;
821 }
822
823 res = (c << x) + res;
824
825 return res;
826}
827
828static int it913x_fe_start(struct it913x_fe_state *state)
829{
830 struct it913xset *set_lna;
831 struct it913xset *set_mode;
832 int ret;
833 u8 adf = (state->config->adf & 0xf);
834 u32 adc, xtal;
835 u8 b[4];
836
837 if (state->config->chip_ver == 1)
838 ret = it913x_init_tuner(state);
839
840 info("ADF table value :%02x", adf);
841
842 if (adf < 10) {
843 state->crystalFrequency = fe_clockTable[adf].xtal ;
844 state->table = fe_clockTable[adf].table;
845 state->adcFrequency = state->table->adcFrequency;
846
847 adc = compute_div(state->adcFrequency, 1000000ul, 19ul);
848 xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul);
849
850 } else
851 return -EINVAL;
852
853
854 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
855 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
856 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
857
858 ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type);
859 ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01);
860 ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01);
861
862 b[0] = xtal & 0xff;
863 b[1] = (xtal >> 8) & 0xff;
864 b[2] = (xtal >> 16) & 0xff;
865 b[3] = (xtal >> 24);
866 ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4);
867
868 b[0] = adc & 0xff;
869 b[1] = (adc >> 8) & 0xff;
870 b[2] = (adc >> 16) & 0xff;
871 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
872
873 if (state->config->adc_x2)
874 ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01);
875 b[0] = 0;
876 b[1] = 0;
877 b[2] = 0;
878 ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3);
879
880 info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x",
881 state->crystalFrequency, state->adcFrequency,
882 state->config->adc_x2);
883 deb_info("Xtal value :%04x Adc value :%04x", xtal, adc);
884
885 if (ret < 0)
886 return -ENODEV;
887
888
889 if (state->config->chip_ver > 1)
890 ret = it913x_fe_script_loader(state, it9135_v2);
891 else
892 ret = it913x_fe_script_loader(state, it9135_v1);
893 if (ret < 0)
894 return ret;
895
896
897 switch (state->tuner_type) {
898 case IT9135_51:
899 set_lna = it9135_51;
900 break;
901 case IT9135_52:
902 set_lna = it9135_52;
903 break;
904 case IT9135_60:
905 set_lna = it9135_60;
906 break;
907 case IT9135_61:
908 set_lna = it9135_61;
909 break;
910 case IT9135_62:
911 set_lna = it9135_62;
912 break;
913 case IT9135_38:
914 default:
915 set_lna = it9135_38;
916 }
917 info("Tuner LNA type :%02x", state->tuner_type);
918
919 ret = it913x_fe_script_loader(state, set_lna);
920 if (ret < 0)
921 return ret;
922
923 if (state->config->chip_ver == 2) {
924 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
925 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
926 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
927 ret |= it913x_init_tuner(state);
928 }
929 if (ret < 0)
930 return -ENODEV;
931
932
933 set_mode = set_solo_fe;
934 ret |= it913x_fe_script_loader(state, set_mode);
935
936 ret |= it913x_fe_suspend(state);
937 return (ret < 0) ? -ENODEV : 0;
938}
939
940static int it913x_fe_init(struct dvb_frontend *fe)
941{
942 struct it913x_fe_state *state = fe->demodulator_priv;
943 int ret = 0;
944
945 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
946
947 ret |= it913x_fe_script_loader(state, init_1);
948
949 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
950
951 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
952
953 return (ret < 0) ? -ENODEV : 0;
954}
955
956static void it913x_fe_release(struct dvb_frontend *fe)
957{
958 struct it913x_fe_state *state = fe->demodulator_priv;
959 kfree(state);
960}
961
962static struct dvb_frontend_ops it913x_fe_ofdm_ops;
963
964struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
965 u8 i2c_addr, struct ite_config *config)
966{
967 struct it913x_fe_state *state = NULL;
968 int ret;
969
970
971 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
972 if (state == NULL)
973 return NULL;
974 if (config == NULL)
975 goto error;
976
977 state->i2c_adap = i2c_adap;
978 state->i2c_addr = i2c_addr;
979 state->config = config;
980
981 switch (state->config->tuner_id_0) {
982 case IT9135_51:
983 case IT9135_52:
984 case IT9135_60:
985 case IT9135_61:
986 case IT9135_62:
987 state->tuner_type = state->config->tuner_id_0;
988 break;
989 default:
990 case IT9135_38:
991 state->tuner_type = IT9135_38;
992 }
993
994 ret = it913x_fe_start(state);
995 if (ret < 0)
996 goto error;
997
998
999
1000 memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops,
1001 sizeof(struct dvb_frontend_ops));
1002 state->frontend.demodulator_priv = state;
1003
1004 return &state->frontend;
1005error:
1006 kfree(state);
1007 return NULL;
1008}
1009EXPORT_SYMBOL(it913x_fe_attach);
1010
1011static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
1012 .delsys = { SYS_DVBT },
1013 .info = {
1014 .name = "it913x-fe DVB-T",
1015 .frequency_min = 51000000,
1016 .frequency_max = 1680000000,
1017 .frequency_stepsize = 62500,
1018 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1019 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1020 FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
1021 FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1022 FE_CAN_TRANSMISSION_MODE_AUTO |
1023 FE_CAN_GUARD_INTERVAL_AUTO |
1024 FE_CAN_HIERARCHY_AUTO,
1025 },
1026
1027 .release = it913x_fe_release,
1028
1029 .init = it913x_fe_init,
1030 .sleep = it913x_fe_sleep,
1031
1032 .set_frontend = it913x_fe_set_frontend,
1033 .get_frontend = it913x_fe_get_frontend,
1034
1035 .read_status = it913x_fe_read_status,
1036 .read_signal_strength = it913x_fe_read_signal_strength,
1037 .read_snr = it913x_fe_read_snr,
1038 .read_ber = it913x_fe_read_ber,
1039 .read_ucblocks = it913x_fe_read_ucblocks,
1040};
1041
1042MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
1043MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
1044MODULE_VERSION("1.15");
1045MODULE_LICENSE("GPL");
1046
