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25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/jiffies.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33
34#include "dvb_frontend.h"
35#include "m88rs2000.h"
36
37struct m88rs2000_state {
38 struct i2c_adapter *i2c;
39 const struct m88rs2000_config *config;
40 struct dvb_frontend frontend;
41 u8 no_lock_count;
42 u32 tuner_frequency;
43 u32 symbol_rate;
44 fe_code_rate_t fec_inner;
45 u8 tuner_level;
46 int errmode;
47};
48
49static int m88rs2000_debug;
50
51module_param_named(debug, m88rs2000_debug, int, 0644);
52MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
53
54#define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
57} while (0)
58
59#define deb_info(args...) dprintk(0x01, args)
60#define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
62
63static int m88rs2000_writereg(struct m88rs2000_state *state,
64 u8 reg, u8 data)
65{
66 int ret;
67 u8 buf[] = { reg, data };
68 struct i2c_msg msg = {
69 .addr = state->config->demod_addr,
70 .flags = 0,
71 .buf = buf,
72 .len = 2
73 };
74
75 ret = i2c_transfer(state->i2c, &msg, 1);
76
77 if (ret != 1)
78 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
79 "ret == %i)\n", __func__, reg, data, ret);
80
81 return (ret != 1) ? -EREMOTEIO : 0;
82}
83
84static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
85{
86 int ret;
87 u8 b0[] = { reg };
88 u8 b1[] = { 0 };
89
90 struct i2c_msg msg[] = {
91 {
92 .addr = state->config->demod_addr,
93 .flags = 0,
94 .buf = b0,
95 .len = 1
96 }, {
97 .addr = state->config->demod_addr,
98 .flags = I2C_M_RD,
99 .buf = b1,
100 .len = 1
101 }
102 };
103
104 ret = i2c_transfer(state->i2c, msg, 2);
105
106 if (ret != 2)
107 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
108 __func__, reg, ret);
109
110 return b1[0];
111}
112
113static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
114{
115 struct m88rs2000_state *state = fe->demodulator_priv;
116 int ret;
117 u32 temp;
118 u8 b[3];
119
120 if ((srate < 1000000) || (srate > 45000000))
121 return -EINVAL;
122
123 temp = srate / 1000;
124 temp *= 11831;
125 temp /= 68;
126 temp -= 3;
127
128 b[0] = (u8) (temp >> 16) & 0xff;
129 b[1] = (u8) (temp >> 8) & 0xff;
130 b[2] = (u8) temp & 0xff;
131 ret = m88rs2000_writereg(state, 0x93, b[2]);
132 ret |= m88rs2000_writereg(state, 0x94, b[1]);
133 ret |= m88rs2000_writereg(state, 0x95, b[0]);
134
135 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
136 return ret;
137}
138
139static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
140 struct dvb_diseqc_master_cmd *m)
141{
142 struct m88rs2000_state *state = fe->demodulator_priv;
143
144 int i;
145 u8 reg;
146 deb_info("%s\n", __func__);
147 m88rs2000_writereg(state, 0x9a, 0x30);
148 reg = m88rs2000_readreg(state, 0xb2);
149 reg &= 0x3f;
150 m88rs2000_writereg(state, 0xb2, reg);
151 for (i = 0; i < m->msg_len; i++)
152 m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
153
154 reg = m88rs2000_readreg(state, 0xb1);
155 reg &= 0x87;
156 reg |= ((m->msg_len - 1) << 3) | 0x07;
157 reg &= 0x7f;
158 m88rs2000_writereg(state, 0xb1, reg);
159
160 for (i = 0; i < 15; i++) {
161 if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
162 break;
163 msleep(20);
164 }
165
166 reg = m88rs2000_readreg(state, 0xb1);
167 if ((reg & 0x40) > 0x0) {
168 reg &= 0x7f;
169 reg |= 0x40;
170 m88rs2000_writereg(state, 0xb1, reg);
171 }
172
173 reg = m88rs2000_readreg(state, 0xb2);
174 reg &= 0x3f;
175 reg |= 0x80;
176 m88rs2000_writereg(state, 0xb2, reg);
177 m88rs2000_writereg(state, 0x9a, 0xb0);
178
179
180 return 0;
181}
182
183static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
184 fe_sec_mini_cmd_t burst)
185{
186 struct m88rs2000_state *state = fe->demodulator_priv;
187 u8 reg0, reg1;
188 deb_info("%s\n", __func__);
189 m88rs2000_writereg(state, 0x9a, 0x30);
190 msleep(50);
191 reg0 = m88rs2000_readreg(state, 0xb1);
192 reg1 = m88rs2000_readreg(state, 0xb2);
193
194 m88rs2000_writereg(state, 0xb2, reg1);
195 m88rs2000_writereg(state, 0xb1, reg0);
196 m88rs2000_writereg(state, 0x9a, 0xb0);
197
198 return 0;
199}
200
201static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
202{
203 struct m88rs2000_state *state = fe->demodulator_priv;
204 u8 reg0, reg1;
205 m88rs2000_writereg(state, 0x9a, 0x30);
206 reg0 = m88rs2000_readreg(state, 0xb1);
207 reg1 = m88rs2000_readreg(state, 0xb2);
208
209 reg1 &= 0x3f;
210
211 switch (tone) {
212 case SEC_TONE_ON:
213 reg0 |= 0x4;
214 reg0 &= 0xbc;
215 break;
216 case SEC_TONE_OFF:
217 reg1 |= 0x80;
218 break;
219 default:
220 break;
221 }
222 m88rs2000_writereg(state, 0xb2, reg1);
223 m88rs2000_writereg(state, 0xb1, reg0);
224 m88rs2000_writereg(state, 0x9a, 0xb0);
225 return 0;
226}
227
228struct inittab {
229 u8 cmd;
230 u8 reg;
231 u8 val;
232};
233
234struct inittab m88rs2000_setup[] = {
235 {DEMOD_WRITE, 0x9a, 0x30},
236 {DEMOD_WRITE, 0x00, 0x01},
237 {WRITE_DELAY, 0x19, 0x00},
238 {DEMOD_WRITE, 0x00, 0x00},
239 {DEMOD_WRITE, 0x9a, 0xb0},
240 {DEMOD_WRITE, 0x81, 0xc1},
241 {DEMOD_WRITE, 0x81, 0x81},
242 {DEMOD_WRITE, 0x86, 0xc6},
243 {DEMOD_WRITE, 0x9a, 0x30},
244 {DEMOD_WRITE, 0xf0, 0x22},
245 {DEMOD_WRITE, 0xf1, 0xbf},
246 {DEMOD_WRITE, 0xb0, 0x45},
247 {DEMOD_WRITE, 0xb2, 0x01},
248 {DEMOD_WRITE, 0x9a, 0xb0},
249 {0xff, 0xaa, 0xff}
250};
251
252struct inittab m88rs2000_shutdown[] = {
253 {DEMOD_WRITE, 0x9a, 0x30},
254 {DEMOD_WRITE, 0xb0, 0x00},
255 {DEMOD_WRITE, 0xf1, 0x89},
256 {DEMOD_WRITE, 0x00, 0x01},
257 {DEMOD_WRITE, 0x9a, 0xb0},
258 {DEMOD_WRITE, 0x81, 0x81},
259 {0xff, 0xaa, 0xff}
260};
261
262struct inittab fe_reset[] = {
263 {DEMOD_WRITE, 0x00, 0x01},
264 {DEMOD_WRITE, 0xf1, 0xbf},
265 {DEMOD_WRITE, 0x00, 0x01},
266 {DEMOD_WRITE, 0x20, 0x81},
267 {DEMOD_WRITE, 0x21, 0x80},
268 {DEMOD_WRITE, 0x10, 0x33},
269 {DEMOD_WRITE, 0x11, 0x44},
270 {DEMOD_WRITE, 0x12, 0x07},
271 {DEMOD_WRITE, 0x18, 0x20},
272 {DEMOD_WRITE, 0x28, 0x04},
273 {DEMOD_WRITE, 0x29, 0x8e},
274 {DEMOD_WRITE, 0x3b, 0xff},
275 {DEMOD_WRITE, 0x32, 0x10},
276 {DEMOD_WRITE, 0x33, 0x02},
277 {DEMOD_WRITE, 0x34, 0x30},
278 {DEMOD_WRITE, 0x35, 0xff},
279 {DEMOD_WRITE, 0x38, 0x50},
280 {DEMOD_WRITE, 0x39, 0x68},
281 {DEMOD_WRITE, 0x3c, 0x7f},
282 {DEMOD_WRITE, 0x3d, 0x0f},
283 {DEMOD_WRITE, 0x45, 0x20},
284 {DEMOD_WRITE, 0x46, 0x24},
285 {DEMOD_WRITE, 0x47, 0x7c},
286 {DEMOD_WRITE, 0x48, 0x16},
287 {DEMOD_WRITE, 0x49, 0x04},
288 {DEMOD_WRITE, 0x4a, 0x01},
289 {DEMOD_WRITE, 0x4b, 0x78},
290 {DEMOD_WRITE, 0X4d, 0xd2},
291 {DEMOD_WRITE, 0x4e, 0x6d},
292 {DEMOD_WRITE, 0x50, 0x30},
293 {DEMOD_WRITE, 0x51, 0x30},
294 {DEMOD_WRITE, 0x54, 0x7b},
295 {DEMOD_WRITE, 0x56, 0x09},
296 {DEMOD_WRITE, 0x58, 0x59},
297 {DEMOD_WRITE, 0x59, 0x37},
298 {DEMOD_WRITE, 0x63, 0xfa},
299 {0xff, 0xaa, 0xff}
300};
301
302struct inittab fe_trigger[] = {
303 {DEMOD_WRITE, 0x97, 0x04},
304 {DEMOD_WRITE, 0x99, 0x77},
305 {DEMOD_WRITE, 0x9b, 0x64},
306 {DEMOD_WRITE, 0x9e, 0x00},
307 {DEMOD_WRITE, 0x9f, 0xf8},
308 {DEMOD_WRITE, 0xa0, 0x20},
309 {DEMOD_WRITE, 0xa1, 0xe0},
310 {DEMOD_WRITE, 0xa3, 0x38},
311 {DEMOD_WRITE, 0x98, 0xff},
312 {DEMOD_WRITE, 0xc0, 0x0f},
313 {DEMOD_WRITE, 0x89, 0x01},
314 {DEMOD_WRITE, 0x00, 0x00},
315 {WRITE_DELAY, 0x0a, 0x00},
316 {DEMOD_WRITE, 0x00, 0x01},
317 {DEMOD_WRITE, 0x00, 0x00},
318 {DEMOD_WRITE, 0x9a, 0xb0},
319 {0xff, 0xaa, 0xff}
320};
321
322static int m88rs2000_tab_set(struct m88rs2000_state *state,
323 struct inittab *tab)
324{
325 int ret = 0;
326 u8 i;
327 if (tab == NULL)
328 return -EINVAL;
329
330 for (i = 0; i < 255; i++) {
331 switch (tab[i].cmd) {
332 case 0x01:
333 ret = m88rs2000_writereg(state, tab[i].reg,
334 tab[i].val);
335 break;
336 case 0x10:
337 if (tab[i].reg > 0)
338 mdelay(tab[i].reg);
339 break;
340 case 0xff:
341 if (tab[i].reg == 0xaa && tab[i].val == 0xff)
342 return 0;
343 case 0x00:
344 break;
345 default:
346 return -EINVAL;
347 }
348 if (ret < 0)
349 return -ENODEV;
350 }
351 return 0;
352}
353
354static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
355{
356 struct m88rs2000_state *state = fe->demodulator_priv;
357 u8 data;
358
359 data = m88rs2000_readreg(state, 0xb2);
360 data |= 0x03;
361
362 switch (volt) {
363 case SEC_VOLTAGE_18:
364 data &= ~0x03;
365 break;
366 case SEC_VOLTAGE_13:
367 data &= ~0x03;
368 data |= 0x01;
369 break;
370 case SEC_VOLTAGE_OFF:
371 break;
372 }
373
374 m88rs2000_writereg(state, 0xb2, data);
375
376 return 0;
377}
378
379static int m88rs2000_init(struct dvb_frontend *fe)
380{
381 struct m88rs2000_state *state = fe->demodulator_priv;
382 int ret;
383
384 deb_info("m88rs2000: init chip\n");
385
386 if (state->config->inittab)
387 ret = m88rs2000_tab_set(state,
388 (struct inittab *)state->config->inittab);
389 else
390 ret = m88rs2000_tab_set(state, m88rs2000_setup);
391
392 return ret;
393}
394
395static int m88rs2000_sleep(struct dvb_frontend *fe)
396{
397 struct m88rs2000_state *state = fe->demodulator_priv;
398 int ret;
399
400 ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
401 return ret;
402}
403
404static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
405{
406 struct m88rs2000_state *state = fe->demodulator_priv;
407 u8 reg = m88rs2000_readreg(state, 0x8c);
408
409 *status = 0;
410
411 if ((reg & 0x7) == 0x7) {
412 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
413 | FE_HAS_SYNC | FE_HAS_LOCK;
414 if (state->config->set_ts_params)
415 state->config->set_ts_params(fe, CALL_IS_READ);
416 }
417 return 0;
418}
419
420static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
421{
422 struct m88rs2000_state *state = fe->demodulator_priv;
423 u8 tmp0, tmp1;
424
425 m88rs2000_writereg(state, 0x9a, 0x30);
426 tmp0 = m88rs2000_readreg(state, 0xd8);
427 if ((tmp0 & 0x10) != 0) {
428 m88rs2000_writereg(state, 0x9a, 0xb0);
429 *ber = 0xffffffff;
430 return 0;
431 }
432
433 *ber = (m88rs2000_readreg(state, 0xd7) << 8) |
434 m88rs2000_readreg(state, 0xd6);
435
436 tmp1 = m88rs2000_readreg(state, 0xd9);
437 m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
438
439 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
440 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
441 m88rs2000_writereg(state, 0x9a, 0xb0);
442
443 return 0;
444}
445
446static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
447 u16 *strength)
448{
449 if (fe->ops.tuner_ops.get_rf_strength)
450 fe->ops.tuner_ops.get_rf_strength(fe, strength);
451
452 return 0;
453}
454
455static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
456{
457 struct m88rs2000_state *state = fe->demodulator_priv;
458
459 *snr = 512 * m88rs2000_readreg(state, 0x65);
460
461 return 0;
462}
463
464static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
465{
466 struct m88rs2000_state *state = fe->demodulator_priv;
467 u8 tmp;
468
469 *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
470 m88rs2000_readreg(state, 0xd4);
471 tmp = m88rs2000_readreg(state, 0xd8);
472 m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
473
474 m88rs2000_writereg(state, 0xd8, tmp | 0x20);
475 m88rs2000_writereg(state, 0xd8, tmp | 0x20);
476
477 return 0;
478}
479
480static int m88rs2000_set_fec(struct m88rs2000_state *state,
481 fe_code_rate_t fec)
482{
483 u16 fec_set;
484 switch (fec) {
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501 case FEC_AUTO:
502 default:
503 fec_set = 0x08;
504 }
505 m88rs2000_writereg(state, 0x76, fec_set);
506
507 return 0;
508}
509
510
511static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
512{
513 u8 reg;
514 m88rs2000_writereg(state, 0x9a, 0x30);
515 reg = m88rs2000_readreg(state, 0x76);
516 m88rs2000_writereg(state, 0x9a, 0xb0);
517
518 switch (reg) {
519 case 0x88:
520 return FEC_1_2;
521 case 0x68:
522 return FEC_2_3;
523 case 0x48:
524 return FEC_3_4;
525 case 0x28:
526 return FEC_5_6;
527 case 0x18:
528 return FEC_7_8;
529 case 0x08:
530 default:
531 break;
532 }
533
534 return FEC_AUTO;
535}
536
537static int m88rs2000_set_frontend(struct dvb_frontend *fe)
538{
539 struct m88rs2000_state *state = fe->demodulator_priv;
540 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
541 fe_status_t status;
542 int i, ret = 0;
543 s32 tmp;
544 u32 tuner_freq;
545 u16 offset = 0;
546 u8 reg;
547
548 state->no_lock_count = 0;
549
550 if (c->delivery_system != SYS_DVBS) {
551 deb_info("%s: unsupported delivery "
552 "system selected (%d)\n",
553 __func__, c->delivery_system);
554 return -EOPNOTSUPP;
555 }
556
557
558 if (fe->ops.tuner_ops.set_params)
559 ret = fe->ops.tuner_ops.set_params(fe);
560
561 if (ret < 0)
562 return -ENODEV;
563
564 if (fe->ops.tuner_ops.get_frequency)
565 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
566
567 if (ret < 0)
568 return -ENODEV;
569
570 offset = tuner_freq - c->frequency;
571
572
573 tmp = offset;
574 tmp *= 65536;
575
576 tmp = (2 * tmp + 96000) / (2 * 96000);
577 if (tmp < 0)
578 tmp += 65536;
579
580 offset = tmp & 0xffff;
581
582 ret = m88rs2000_writereg(state, 0x9a, 0x30);
583
584 reg = m88rs2000_readreg(state, 0x86);
585 ret |= m88rs2000_writereg(state, 0x86, reg);
586
587 ret |= m88rs2000_writereg(state, 0x9c, (offset >> 8));
588 ret |= m88rs2000_writereg(state, 0x9d, offset & 0xf0);
589
590
591
592 ret = m88rs2000_tab_set(state, fe_reset);
593 if (ret < 0)
594 return -ENODEV;
595
596
597 reg = m88rs2000_readreg(state, 0x70);
598 ret = m88rs2000_writereg(state, 0x70, reg);
599
600
601 ret |= m88rs2000_set_fec(state, c->fec_inner);
602 ret |= m88rs2000_writereg(state, 0x85, 0x1);
603 ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
604 ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
605 ret |= m88rs2000_writereg(state, 0x90, 0xf1);
606 ret |= m88rs2000_writereg(state, 0x91, 0x08);
607
608 if (ret < 0)
609 return -ENODEV;
610
611
612 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
613 if (ret < 0)
614 return -ENODEV;
615
616
617 ret = m88rs2000_tab_set(state, fe_trigger);
618 if (ret < 0)
619 return -ENODEV;
620
621 for (i = 0; i < 25; i++) {
622 reg = m88rs2000_readreg(state, 0x8c);
623 if ((reg & 0x7) == 0x7) {
624 status = FE_HAS_LOCK;
625 break;
626 }
627 state->no_lock_count++;
628 if (state->no_lock_count == 15) {
629 reg = m88rs2000_readreg(state, 0x70);
630 reg ^= 0x4;
631 m88rs2000_writereg(state, 0x70, reg);
632 state->no_lock_count = 0;
633 }
634 msleep(20);
635 }
636
637 if (status & FE_HAS_LOCK) {
638 state->fec_inner = m88rs2000_get_fec(state);
639
640 reg = m88rs2000_readreg(state, 0x65);
641 }
642
643 state->tuner_frequency = c->frequency;
644 state->symbol_rate = c->symbol_rate;
645 return 0;
646}
647
648static int m88rs2000_get_frontend(struct dvb_frontend *fe)
649{
650 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
651 struct m88rs2000_state *state = fe->demodulator_priv;
652 c->fec_inner = state->fec_inner;
653 c->frequency = state->tuner_frequency;
654 c->symbol_rate = state->symbol_rate;
655 return 0;
656}
657
658static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
659{
660 struct m88rs2000_state *state = fe->demodulator_priv;
661
662 if (enable)
663 m88rs2000_writereg(state, 0x81, 0x84);
664 else
665 m88rs2000_writereg(state, 0x81, 0x81);
666 udelay(10);
667 return 0;
668}
669
670static void m88rs2000_release(struct dvb_frontend *fe)
671{
672 struct m88rs2000_state *state = fe->demodulator_priv;
673 kfree(state);
674}
675
676static struct dvb_frontend_ops m88rs2000_ops = {
677 .delsys = { SYS_DVBS },
678 .info = {
679 .name = "M88RS2000 DVB-S",
680 .frequency_min = 950000,
681 .frequency_max = 2150000,
682 .frequency_stepsize = 1000,
683 .frequency_tolerance = 5000,
684 .symbol_rate_min = 1000000,
685 .symbol_rate_max = 45000000,
686 .symbol_rate_tolerance = 500,
687 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
688 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
689 FE_CAN_QPSK |
690 FE_CAN_FEC_AUTO
691 },
692
693 .release = m88rs2000_release,
694 .init = m88rs2000_init,
695 .sleep = m88rs2000_sleep,
696 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
697 .read_status = m88rs2000_read_status,
698 .read_ber = m88rs2000_read_ber,
699 .read_signal_strength = m88rs2000_read_signal_strength,
700 .read_snr = m88rs2000_read_snr,
701 .read_ucblocks = m88rs2000_read_ucblocks,
702 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
703 .diseqc_send_burst = m88rs2000_send_diseqc_burst,
704 .set_tone = m88rs2000_set_tone,
705 .set_voltage = m88rs2000_set_voltage,
706
707 .set_frontend = m88rs2000_set_frontend,
708 .get_frontend = m88rs2000_get_frontend,
709};
710
711struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
712 struct i2c_adapter *i2c)
713{
714 struct m88rs2000_state *state = NULL;
715
716
717 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
718 if (state == NULL)
719 goto error;
720
721
722 state->config = config;
723 state->i2c = i2c;
724 state->tuner_frequency = 0;
725 state->symbol_rate = 0;
726 state->fec_inner = 0;
727
728
729 memcpy(&state->frontend.ops, &m88rs2000_ops,
730 sizeof(struct dvb_frontend_ops));
731 state->frontend.demodulator_priv = state;
732 return &state->frontend;
733
734error:
735 kfree(state);
736
737 return NULL;
738}
739EXPORT_SYMBOL(m88rs2000_attach);
740
741MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
742MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
743MODULE_LICENSE("GPL");
744MODULE_VERSION("1.13");
745
746
