1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/led.h>
27#include <linux/can/platform/flexcan.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/if_arp.h>
31#include <linux/if_ether.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/kernel.h>
35#include <linux/list.h>
36#include <linux/module.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/platform_device.h>
40#include <linux/pinctrl/consumer.h>
41
42#define DRV_NAME "flexcan"
43
44
45#define FLEXCAN_NAPI_WEIGHT (8 + 2)
46
47
48#define FLEXCAN_MCR_MDIS BIT(31)
49#define FLEXCAN_MCR_FRZ BIT(30)
50#define FLEXCAN_MCR_FEN BIT(29)
51#define FLEXCAN_MCR_HALT BIT(28)
52#define FLEXCAN_MCR_NOT_RDY BIT(27)
53#define FLEXCAN_MCR_WAK_MSK BIT(26)
54#define FLEXCAN_MCR_SOFTRST BIT(25)
55#define FLEXCAN_MCR_FRZ_ACK BIT(24)
56#define FLEXCAN_MCR_SUPV BIT(23)
57#define FLEXCAN_MCR_SLF_WAK BIT(22)
58#define FLEXCAN_MCR_WRN_EN BIT(21)
59#define FLEXCAN_MCR_LPM_ACK BIT(20)
60#define FLEXCAN_MCR_WAK_SRC BIT(19)
61#define FLEXCAN_MCR_DOZE BIT(18)
62#define FLEXCAN_MCR_SRX_DIS BIT(17)
63#define FLEXCAN_MCR_BCC BIT(16)
64#define FLEXCAN_MCR_LPRIO_EN BIT(13)
65#define FLEXCAN_MCR_AEN BIT(12)
66#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
67#define FLEXCAN_MCR_IDAM_A (0 << 8)
68#define FLEXCAN_MCR_IDAM_B (1 << 8)
69#define FLEXCAN_MCR_IDAM_C (2 << 8)
70#define FLEXCAN_MCR_IDAM_D (3 << 8)
71
72
73#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
74#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
75#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
76#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
77#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
78#define FLEXCAN_CTRL_ERR_MSK BIT(14)
79#define FLEXCAN_CTRL_CLK_SRC BIT(13)
80#define FLEXCAN_CTRL_LPB BIT(12)
81#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
82#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
83#define FLEXCAN_CTRL_SMP BIT(7)
84#define FLEXCAN_CTRL_BOFF_REC BIT(6)
85#define FLEXCAN_CTRL_TSYN BIT(5)
86#define FLEXCAN_CTRL_LBUF BIT(4)
87#define FLEXCAN_CTRL_LOM BIT(3)
88#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
89#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
90#define FLEXCAN_CTRL_ERR_STATE \
91 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
92 FLEXCAN_CTRL_BOFF_MSK)
93#define FLEXCAN_CTRL_ERR_ALL \
94 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95
96
97#define FLEXCAN_ESR_TWRN_INT BIT(17)
98#define FLEXCAN_ESR_RWRN_INT BIT(16)
99#define FLEXCAN_ESR_BIT1_ERR BIT(15)
100#define FLEXCAN_ESR_BIT0_ERR BIT(14)
101#define FLEXCAN_ESR_ACK_ERR BIT(13)
102#define FLEXCAN_ESR_CRC_ERR BIT(12)
103#define FLEXCAN_ESR_FRM_ERR BIT(11)
104#define FLEXCAN_ESR_STF_ERR BIT(10)
105#define FLEXCAN_ESR_TX_WRN BIT(9)
106#define FLEXCAN_ESR_RX_WRN BIT(8)
107#define FLEXCAN_ESR_IDLE BIT(7)
108#define FLEXCAN_ESR_TXRX BIT(6)
109#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
110#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
113#define FLEXCAN_ESR_BOFF_INT BIT(2)
114#define FLEXCAN_ESR_ERR_INT BIT(1)
115#define FLEXCAN_ESR_WAK_INT BIT(0)
116#define FLEXCAN_ESR_ERR_BUS \
117 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
118 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
119 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
120#define FLEXCAN_ESR_ERR_STATE \
121 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
122#define FLEXCAN_ESR_ERR_ALL \
123 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
124#define FLEXCAN_ESR_ALL_INT \
125 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
126 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
127
128
129#define FLEXCAN_TX_BUF_ID 8
130#define FLEXCAN_IFLAG_BUF(x) BIT(x)
131#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
132#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
133#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
134#define FLEXCAN_IFLAG_DEFAULT \
135 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
136 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
137
138
139#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
140#define FLEXCAN_MB_CNT_SRR BIT(22)
141#define FLEXCAN_MB_CNT_IDE BIT(21)
142#define FLEXCAN_MB_CNT_RTR BIT(20)
143#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
144#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
145
146#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162#define FLEXCAN_HAS_V10_FEATURES BIT(1)
163#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2)
164
165
166struct flexcan_mb {
167 u32 can_ctrl;
168 u32 can_id;
169 u32 data[2];
170};
171
172
173struct flexcan_regs {
174 u32 mcr;
175 u32 ctrl;
176 u32 timer;
177 u32 _reserved1;
178 u32 rxgmask;
179 u32 rx14mask;
180 u32 rx15mask;
181 u32 ecr;
182 u32 esr;
183 u32 imask2;
184 u32 imask1;
185 u32 iflag2;
186 u32 iflag1;
187 u32 crl2;
188 u32 esr2;
189 u32 imeur;
190 u32 lrfr;
191 u32 crcr;
192 u32 rxfgmask;
193 u32 rxfir;
194 u32 _reserved3[12];
195 struct flexcan_mb cantxfg[64];
196};
197
198struct flexcan_devtype_data {
199 u32 features;
200};
201
202struct flexcan_priv {
203 struct can_priv can;
204 struct net_device *dev;
205 struct napi_struct napi;
206
207 void __iomem *base;
208 u32 reg_esr;
209 u32 reg_ctrl_default;
210
211 struct clk *clk_ipg;
212 struct clk *clk_per;
213 struct flexcan_platform_data *pdata;
214 const struct flexcan_devtype_data *devtype_data;
215};
216
217static struct flexcan_devtype_data fsl_p1010_devtype_data = {
218 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
219};
220static struct flexcan_devtype_data fsl_imx28_devtype_data;
221static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
222 .features = FLEXCAN_HAS_V10_FEATURES,
223};
224
225static const struct can_bittiming_const flexcan_bittiming_const = {
226 .name = DRV_NAME,
227 .tseg1_min = 4,
228 .tseg1_max = 16,
229 .tseg2_min = 2,
230 .tseg2_max = 8,
231 .sjw_max = 4,
232 .brp_min = 1,
233 .brp_max = 256,
234 .brp_inc = 1,
235};
236
237
238
239
240#if defined(__BIG_ENDIAN)
241static inline u32 flexcan_read(void __iomem *addr)
242{
243 return in_be32(addr);
244}
245
246static inline void flexcan_write(u32 val, void __iomem *addr)
247{
248 out_be32(addr, val);
249}
250#else
251static inline u32 flexcan_read(void __iomem *addr)
252{
253 return readl(addr);
254}
255
256static inline void flexcan_write(u32 val, void __iomem *addr)
257{
258 writel(val, addr);
259}
260#endif
261
262
263
264
265static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
266{
267 if (priv->pdata && priv->pdata->transceiver_switch)
268 priv->pdata->transceiver_switch(on);
269}
270
271static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
272 u32 reg_esr)
273{
274 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
275 (reg_esr & FLEXCAN_ESR_ERR_BUS);
276}
277
278static inline void flexcan_chip_enable(struct flexcan_priv *priv)
279{
280 struct flexcan_regs __iomem *regs = priv->base;
281 u32 reg;
282
283 reg = flexcan_read(®s->mcr);
284 reg &= ~FLEXCAN_MCR_MDIS;
285 flexcan_write(reg, ®s->mcr);
286
287 udelay(10);
288}
289
290static inline void flexcan_chip_disable(struct flexcan_priv *priv)
291{
292 struct flexcan_regs __iomem *regs = priv->base;
293 u32 reg;
294
295 reg = flexcan_read(®s->mcr);
296 reg |= FLEXCAN_MCR_MDIS;
297 flexcan_write(reg, ®s->mcr);
298}
299
300static int flexcan_get_berr_counter(const struct net_device *dev,
301 struct can_berr_counter *bec)
302{
303 const struct flexcan_priv *priv = netdev_priv(dev);
304 struct flexcan_regs __iomem *regs = priv->base;
305 u32 reg = flexcan_read(®s->ecr);
306
307 bec->txerr = (reg >> 0) & 0xff;
308 bec->rxerr = (reg >> 8) & 0xff;
309
310 return 0;
311}
312
313static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
314{
315 const struct flexcan_priv *priv = netdev_priv(dev);
316 struct flexcan_regs __iomem *regs = priv->base;
317 struct can_frame *cf = (struct can_frame *)skb->data;
318 u32 can_id;
319 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
320
321 if (can_dropped_invalid_skb(dev, skb))
322 return NETDEV_TX_OK;
323
324 netif_stop_queue(dev);
325
326 if (cf->can_id & CAN_EFF_FLAG) {
327 can_id = cf->can_id & CAN_EFF_MASK;
328 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
329 } else {
330 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
331 }
332
333 if (cf->can_id & CAN_RTR_FLAG)
334 ctrl |= FLEXCAN_MB_CNT_RTR;
335
336 if (cf->can_dlc > 0) {
337 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
338 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
339 }
340 if (cf->can_dlc > 3) {
341 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
342 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
343 }
344
345 can_put_echo_skb(skb, dev, 0);
346
347 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
348 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
349
350 return NETDEV_TX_OK;
351}
352
353static void do_bus_err(struct net_device *dev,
354 struct can_frame *cf, u32 reg_esr)
355{
356 struct flexcan_priv *priv = netdev_priv(dev);
357 int rx_errors = 0, tx_errors = 0;
358
359 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
360
361 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
362 netdev_dbg(dev, "BIT1_ERR irq\n");
363 cf->data[2] |= CAN_ERR_PROT_BIT1;
364 tx_errors = 1;
365 }
366 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
367 netdev_dbg(dev, "BIT0_ERR irq\n");
368 cf->data[2] |= CAN_ERR_PROT_BIT0;
369 tx_errors = 1;
370 }
371 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
372 netdev_dbg(dev, "ACK_ERR irq\n");
373 cf->can_id |= CAN_ERR_ACK;
374 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
375 tx_errors = 1;
376 }
377 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
378 netdev_dbg(dev, "CRC_ERR irq\n");
379 cf->data[2] |= CAN_ERR_PROT_BIT;
380 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
381 rx_errors = 1;
382 }
383 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
384 netdev_dbg(dev, "FRM_ERR irq\n");
385 cf->data[2] |= CAN_ERR_PROT_FORM;
386 rx_errors = 1;
387 }
388 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
389 netdev_dbg(dev, "STF_ERR irq\n");
390 cf->data[2] |= CAN_ERR_PROT_STUFF;
391 rx_errors = 1;
392 }
393
394 priv->can.can_stats.bus_error++;
395 if (rx_errors)
396 dev->stats.rx_errors++;
397 if (tx_errors)
398 dev->stats.tx_errors++;
399}
400
401static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
402{
403 struct sk_buff *skb;
404 struct can_frame *cf;
405
406 skb = alloc_can_err_skb(dev, &cf);
407 if (unlikely(!skb))
408 return 0;
409
410 do_bus_err(dev, cf, reg_esr);
411 netif_receive_skb(skb);
412
413 dev->stats.rx_packets++;
414 dev->stats.rx_bytes += cf->can_dlc;
415
416 return 1;
417}
418
419static void do_state(struct net_device *dev,
420 struct can_frame *cf, enum can_state new_state)
421{
422 struct flexcan_priv *priv = netdev_priv(dev);
423 struct can_berr_counter bec;
424
425 flexcan_get_berr_counter(dev, &bec);
426
427 switch (priv->can.state) {
428 case CAN_STATE_ERROR_ACTIVE:
429
430
431
432
433
434 if (new_state >= CAN_STATE_ERROR_WARNING &&
435 new_state <= CAN_STATE_BUS_OFF) {
436 netdev_dbg(dev, "Error Warning IRQ\n");
437 priv->can.can_stats.error_warning++;
438
439 cf->can_id |= CAN_ERR_CRTL;
440 cf->data[1] = (bec.txerr > bec.rxerr) ?
441 CAN_ERR_CRTL_TX_WARNING :
442 CAN_ERR_CRTL_RX_WARNING;
443 }
444 case CAN_STATE_ERROR_WARNING:
445
446
447
448
449
450 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
451 new_state <= CAN_STATE_BUS_OFF) {
452 netdev_dbg(dev, "Error Passive IRQ\n");
453 priv->can.can_stats.error_passive++;
454
455 cf->can_id |= CAN_ERR_CRTL;
456 cf->data[1] = (bec.txerr > bec.rxerr) ?
457 CAN_ERR_CRTL_TX_PASSIVE :
458 CAN_ERR_CRTL_RX_PASSIVE;
459 }
460 break;
461 case CAN_STATE_BUS_OFF:
462 netdev_err(dev, "BUG! "
463 "hardware recovered automatically from BUS_OFF\n");
464 break;
465 default:
466 break;
467 }
468
469
470 switch (new_state) {
471 case CAN_STATE_ERROR_ACTIVE:
472 netdev_dbg(dev, "Error Active\n");
473 cf->can_id |= CAN_ERR_PROT;
474 cf->data[2] = CAN_ERR_PROT_ACTIVE;
475 break;
476 case CAN_STATE_BUS_OFF:
477 cf->can_id |= CAN_ERR_BUSOFF;
478 can_bus_off(dev);
479 break;
480 default:
481 break;
482 }
483}
484
485static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
486{
487 struct flexcan_priv *priv = netdev_priv(dev);
488 struct sk_buff *skb;
489 struct can_frame *cf;
490 enum can_state new_state;
491 int flt;
492
493 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
494 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
495 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
496 FLEXCAN_ESR_RX_WRN))))
497 new_state = CAN_STATE_ERROR_ACTIVE;
498 else
499 new_state = CAN_STATE_ERROR_WARNING;
500 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
501 new_state = CAN_STATE_ERROR_PASSIVE;
502 else
503 new_state = CAN_STATE_BUS_OFF;
504
505
506 if (likely(new_state == priv->can.state))
507 return 0;
508
509 skb = alloc_can_err_skb(dev, &cf);
510 if (unlikely(!skb))
511 return 0;
512
513 do_state(dev, cf, new_state);
514 priv->can.state = new_state;
515 netif_receive_skb(skb);
516
517 dev->stats.rx_packets++;
518 dev->stats.rx_bytes += cf->can_dlc;
519
520 return 1;
521}
522
523static void flexcan_read_fifo(const struct net_device *dev,
524 struct can_frame *cf)
525{
526 const struct flexcan_priv *priv = netdev_priv(dev);
527 struct flexcan_regs __iomem *regs = priv->base;
528 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
529 u32 reg_ctrl, reg_id;
530
531 reg_ctrl = flexcan_read(&mb->can_ctrl);
532 reg_id = flexcan_read(&mb->can_id);
533 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
534 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
535 else
536 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
537
538 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
539 cf->can_id |= CAN_RTR_FLAG;
540 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
541
542 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
543 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
544
545
546 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
547 flexcan_read(®s->timer);
548}
549
550static int flexcan_read_frame(struct net_device *dev)
551{
552 struct net_device_stats *stats = &dev->stats;
553 struct can_frame *cf;
554 struct sk_buff *skb;
555
556 skb = alloc_can_skb(dev, &cf);
557 if (unlikely(!skb)) {
558 stats->rx_dropped++;
559 return 0;
560 }
561
562 flexcan_read_fifo(dev, cf);
563 netif_receive_skb(skb);
564
565 stats->rx_packets++;
566 stats->rx_bytes += cf->can_dlc;
567
568 can_led_event(dev, CAN_LED_EVENT_RX);
569
570 return 1;
571}
572
573static int flexcan_poll(struct napi_struct *napi, int quota)
574{
575 struct net_device *dev = napi->dev;
576 const struct flexcan_priv *priv = netdev_priv(dev);
577 struct flexcan_regs __iomem *regs = priv->base;
578 u32 reg_iflag1, reg_esr;
579 int work_done = 0;
580
581
582
583
584
585 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
586
587
588 work_done += flexcan_poll_state(dev, reg_esr);
589
590
591 reg_iflag1 = flexcan_read(®s->iflag1);
592 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
593 work_done < quota) {
594 work_done += flexcan_read_frame(dev);
595 reg_iflag1 = flexcan_read(®s->iflag1);
596 }
597
598
599 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
600 work_done += flexcan_poll_bus_err(dev, reg_esr);
601
602 if (work_done < quota) {
603 napi_complete(napi);
604
605 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
606 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
607 }
608
609 return work_done;
610}
611
612static irqreturn_t flexcan_irq(int irq, void *dev_id)
613{
614 struct net_device *dev = dev_id;
615 struct net_device_stats *stats = &dev->stats;
616 struct flexcan_priv *priv = netdev_priv(dev);
617 struct flexcan_regs __iomem *regs = priv->base;
618 u32 reg_iflag1, reg_esr;
619
620 reg_iflag1 = flexcan_read(®s->iflag1);
621 reg_esr = flexcan_read(®s->esr);
622
623 if (reg_esr & FLEXCAN_ESR_ALL_INT)
624 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
625
626
627
628
629
630
631
632 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
633 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
634 flexcan_has_and_handle_berr(priv, reg_esr)) {
635
636
637
638
639 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
640 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
641 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
642 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
643 ®s->ctrl);
644 napi_schedule(&priv->napi);
645 }
646
647
648 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
649 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
650 dev->stats.rx_over_errors++;
651 dev->stats.rx_errors++;
652 }
653
654
655 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
656 stats->tx_bytes += can_get_echo_skb(dev, 0);
657 stats->tx_packets++;
658 can_led_event(dev, CAN_LED_EVENT_TX);
659 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
660 netif_wake_queue(dev);
661 }
662
663 return IRQ_HANDLED;
664}
665
666static void flexcan_set_bittiming(struct net_device *dev)
667{
668 const struct flexcan_priv *priv = netdev_priv(dev);
669 const struct can_bittiming *bt = &priv->can.bittiming;
670 struct flexcan_regs __iomem *regs = priv->base;
671 u32 reg;
672
673 reg = flexcan_read(®s->ctrl);
674 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
675 FLEXCAN_CTRL_RJW(0x3) |
676 FLEXCAN_CTRL_PSEG1(0x7) |
677 FLEXCAN_CTRL_PSEG2(0x7) |
678 FLEXCAN_CTRL_PROPSEG(0x7) |
679 FLEXCAN_CTRL_LPB |
680 FLEXCAN_CTRL_SMP |
681 FLEXCAN_CTRL_LOM);
682
683 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
684 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
685 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
686 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
687 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
688
689 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
690 reg |= FLEXCAN_CTRL_LPB;
691 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
692 reg |= FLEXCAN_CTRL_LOM;
693 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
694 reg |= FLEXCAN_CTRL_SMP;
695
696 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
697 flexcan_write(reg, ®s->ctrl);
698
699
700 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
701 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
702}
703
704
705
706
707
708
709
710static int flexcan_chip_start(struct net_device *dev)
711{
712 struct flexcan_priv *priv = netdev_priv(dev);
713 struct flexcan_regs __iomem *regs = priv->base;
714 int err;
715 u32 reg_mcr, reg_ctrl;
716
717
718 flexcan_chip_enable(priv);
719
720
721 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
722 udelay(10);
723
724 reg_mcr = flexcan_read(®s->mcr);
725 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
726 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
727 reg_mcr);
728 err = -ENODEV;
729 goto out;
730 }
731
732 flexcan_set_bittiming(dev);
733
734
735
736
737
738
739
740
741
742
743
744
745
746 reg_mcr = flexcan_read(®s->mcr);
747 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
748 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
749 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
750 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
751 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
752 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
753 flexcan_write(reg_mcr, ®s->mcr);
754
755
756
757
758
759
760
761
762
763
764
765
766
767 reg_ctrl = flexcan_read(®s->ctrl);
768 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
769 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
770 FLEXCAN_CTRL_ERR_STATE;
771
772
773
774
775
776 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
777 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
778 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
779
780
781 priv->reg_ctrl_default = reg_ctrl;
782 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
783 flexcan_write(reg_ctrl, ®s->ctrl);
784
785
786 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
787 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
788
789
790 flexcan_write(0x0, ®s->rxgmask);
791 flexcan_write(0x0, ®s->rx14mask);
792 flexcan_write(0x0, ®s->rx15mask);
793
794 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
795 flexcan_write(0x0, ®s->rxfgmask);
796
797 flexcan_transceiver_switch(priv, 1);
798
799
800 reg_mcr = flexcan_read(®s->mcr);
801 reg_mcr &= ~FLEXCAN_MCR_HALT;
802 flexcan_write(reg_mcr, ®s->mcr);
803
804 priv->can.state = CAN_STATE_ERROR_ACTIVE;
805
806
807 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
808
809
810 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
811 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
812
813 return 0;
814
815 out:
816 flexcan_chip_disable(priv);
817 return err;
818}
819
820
821
822
823
824
825
826static void flexcan_chip_stop(struct net_device *dev)
827{
828 struct flexcan_priv *priv = netdev_priv(dev);
829 struct flexcan_regs __iomem *regs = priv->base;
830 u32 reg;
831
832
833 flexcan_write(0, ®s->imask1);
834
835
836 reg = flexcan_read(®s->mcr);
837 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
838 flexcan_write(reg, ®s->mcr);
839
840 flexcan_transceiver_switch(priv, 0);
841 priv->can.state = CAN_STATE_STOPPED;
842
843 return;
844}
845
846static int flexcan_open(struct net_device *dev)
847{
848 struct flexcan_priv *priv = netdev_priv(dev);
849 int err;
850
851 clk_prepare_enable(priv->clk_ipg);
852 clk_prepare_enable(priv->clk_per);
853
854 err = open_candev(dev);
855 if (err)
856 goto out;
857
858 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
859 if (err)
860 goto out_close;
861
862
863 err = flexcan_chip_start(dev);
864 if (err)
865 goto out_close;
866
867 can_led_event(dev, CAN_LED_EVENT_OPEN);
868
869 napi_enable(&priv->napi);
870 netif_start_queue(dev);
871
872 return 0;
873
874 out_close:
875 close_candev(dev);
876 out:
877 clk_disable_unprepare(priv->clk_per);
878 clk_disable_unprepare(priv->clk_ipg);
879
880 return err;
881}
882
883static int flexcan_close(struct net_device *dev)
884{
885 struct flexcan_priv *priv = netdev_priv(dev);
886
887 netif_stop_queue(dev);
888 napi_disable(&priv->napi);
889 flexcan_chip_stop(dev);
890
891 free_irq(dev->irq, dev);
892 clk_disable_unprepare(priv->clk_per);
893 clk_disable_unprepare(priv->clk_ipg);
894
895 close_candev(dev);
896
897 can_led_event(dev, CAN_LED_EVENT_STOP);
898
899 return 0;
900}
901
902static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
903{
904 int err;
905
906 switch (mode) {
907 case CAN_MODE_START:
908 err = flexcan_chip_start(dev);
909 if (err)
910 return err;
911
912 netif_wake_queue(dev);
913 break;
914
915 default:
916 return -EOPNOTSUPP;
917 }
918
919 return 0;
920}
921
922static const struct net_device_ops flexcan_netdev_ops = {
923 .ndo_open = flexcan_open,
924 .ndo_stop = flexcan_close,
925 .ndo_start_xmit = flexcan_start_xmit,
926};
927
928static int register_flexcandev(struct net_device *dev)
929{
930 struct flexcan_priv *priv = netdev_priv(dev);
931 struct flexcan_regs __iomem *regs = priv->base;
932 u32 reg, err;
933
934 clk_prepare_enable(priv->clk_ipg);
935 clk_prepare_enable(priv->clk_per);
936
937
938 flexcan_chip_disable(priv);
939 reg = flexcan_read(®s->ctrl);
940 reg |= FLEXCAN_CTRL_CLK_SRC;
941 flexcan_write(reg, ®s->ctrl);
942
943 flexcan_chip_enable(priv);
944
945
946 reg = flexcan_read(®s->mcr);
947 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
948 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
949 flexcan_write(reg, ®s->mcr);
950
951
952
953
954
955
956 reg = flexcan_read(®s->mcr);
957 if (!(reg & FLEXCAN_MCR_FEN)) {
958 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
959 err = -ENODEV;
960 goto out;
961 }
962
963 err = register_candev(dev);
964
965 out:
966
967 flexcan_chip_disable(priv);
968 clk_disable_unprepare(priv->clk_per);
969 clk_disable_unprepare(priv->clk_ipg);
970
971 return err;
972}
973
974static void unregister_flexcandev(struct net_device *dev)
975{
976 unregister_candev(dev);
977}
978
979static const struct of_device_id flexcan_of_match[] = {
980 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
981 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
982 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
983 { },
984};
985MODULE_DEVICE_TABLE(of, flexcan_of_match);
986
987static const struct platform_device_id flexcan_id_table[] = {
988 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
989 { },
990};
991MODULE_DEVICE_TABLE(platform, flexcan_id_table);
992
993static int flexcan_probe(struct platform_device *pdev)
994{
995 const struct of_device_id *of_id;
996 const struct flexcan_devtype_data *devtype_data;
997 struct net_device *dev;
998 struct flexcan_priv *priv;
999 struct resource *mem;
1000 struct clk *clk_ipg = NULL, *clk_per = NULL;
1001 struct pinctrl *pinctrl;
1002 void __iomem *base;
1003 resource_size_t mem_size;
1004 int err, irq;
1005 u32 clock_freq = 0;
1006
1007 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1008 if (IS_ERR(pinctrl))
1009 return PTR_ERR(pinctrl);
1010
1011 if (pdev->dev.of_node)
1012 of_property_read_u32(pdev->dev.of_node,
1013 "clock-frequency", &clock_freq);
1014
1015 if (!clock_freq) {
1016 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1017 if (IS_ERR(clk_ipg)) {
1018 dev_err(&pdev->dev, "no ipg clock defined\n");
1019 err = PTR_ERR(clk_ipg);
1020 goto failed_clock;
1021 }
1022 clock_freq = clk_get_rate(clk_ipg);
1023
1024 clk_per = devm_clk_get(&pdev->dev, "per");
1025 if (IS_ERR(clk_per)) {
1026 dev_err(&pdev->dev, "no per clock defined\n");
1027 err = PTR_ERR(clk_per);
1028 goto failed_clock;
1029 }
1030 }
1031
1032 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1033 irq = platform_get_irq(pdev, 0);
1034 if (!mem || irq <= 0) {
1035 err = -ENODEV;
1036 goto failed_get;
1037 }
1038
1039 mem_size = resource_size(mem);
1040 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
1041 err = -EBUSY;
1042 goto failed_get;
1043 }
1044
1045 base = ioremap(mem->start, mem_size);
1046 if (!base) {
1047 err = -ENOMEM;
1048 goto failed_map;
1049 }
1050
1051 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1052 if (!dev) {
1053 err = -ENOMEM;
1054 goto failed_alloc;
1055 }
1056
1057 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1058 if (of_id) {
1059 devtype_data = of_id->data;
1060 } else if (pdev->id_entry->driver_data) {
1061 devtype_data = (struct flexcan_devtype_data *)
1062 pdev->id_entry->driver_data;
1063 } else {
1064 err = -ENODEV;
1065 goto failed_devtype;
1066 }
1067
1068 dev->netdev_ops = &flexcan_netdev_ops;
1069 dev->irq = irq;
1070 dev->flags |= IFF_ECHO;
1071
1072 priv = netdev_priv(dev);
1073 priv->can.clock.freq = clock_freq;
1074 priv->can.bittiming_const = &flexcan_bittiming_const;
1075 priv->can.do_set_mode = flexcan_set_mode;
1076 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1077 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1078 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1079 CAN_CTRLMODE_BERR_REPORTING;
1080 priv->base = base;
1081 priv->dev = dev;
1082 priv->clk_ipg = clk_ipg;
1083 priv->clk_per = clk_per;
1084 priv->pdata = pdev->dev.platform_data;
1085 priv->devtype_data = devtype_data;
1086
1087 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1088
1089 dev_set_drvdata(&pdev->dev, dev);
1090 SET_NETDEV_DEV(dev, &pdev->dev);
1091
1092 err = register_flexcandev(dev);
1093 if (err) {
1094 dev_err(&pdev->dev, "registering netdev failed\n");
1095 goto failed_register;
1096 }
1097
1098 devm_can_led_init(dev);
1099
1100 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1101 priv->base, dev->irq);
1102
1103 return 0;
1104
1105 failed_register:
1106 failed_devtype:
1107 free_candev(dev);
1108 failed_alloc:
1109 iounmap(base);
1110 failed_map:
1111 release_mem_region(mem->start, mem_size);
1112 failed_get:
1113 failed_clock:
1114 return err;
1115}
1116
1117static int flexcan_remove(struct platform_device *pdev)
1118{
1119 struct net_device *dev = platform_get_drvdata(pdev);
1120 struct flexcan_priv *priv = netdev_priv(dev);
1121 struct resource *mem;
1122
1123 unregister_flexcandev(dev);
1124 platform_set_drvdata(pdev, NULL);
1125 iounmap(priv->base);
1126
1127 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1128 release_mem_region(mem->start, resource_size(mem));
1129
1130 free_candev(dev);
1131
1132 return 0;
1133}
1134
1135#ifdef CONFIG_PM
1136static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
1137{
1138 struct net_device *dev = platform_get_drvdata(pdev);
1139 struct flexcan_priv *priv = netdev_priv(dev);
1140
1141 flexcan_chip_disable(priv);
1142
1143 if (netif_running(dev)) {
1144 netif_stop_queue(dev);
1145 netif_device_detach(dev);
1146 }
1147 priv->can.state = CAN_STATE_SLEEPING;
1148
1149 return 0;
1150}
1151
1152static int flexcan_resume(struct platform_device *pdev)
1153{
1154 struct net_device *dev = platform_get_drvdata(pdev);
1155 struct flexcan_priv *priv = netdev_priv(dev);
1156
1157 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1158 if (netif_running(dev)) {
1159 netif_device_attach(dev);
1160 netif_start_queue(dev);
1161 }
1162 flexcan_chip_enable(priv);
1163
1164 return 0;
1165}
1166#else
1167#define flexcan_suspend NULL
1168#define flexcan_resume NULL
1169#endif
1170
1171static struct platform_driver flexcan_driver = {
1172 .driver = {
1173 .name = DRV_NAME,
1174 .owner = THIS_MODULE,
1175 .of_match_table = flexcan_of_match,
1176 },
1177 .probe = flexcan_probe,
1178 .remove = flexcan_remove,
1179 .suspend = flexcan_suspend,
1180 .resume = flexcan_resume,
1181 .id_table = flexcan_id_table,
1182};
1183
1184module_platform_driver(flexcan_driver);
1185
1186MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1187 "Marc Kleine-Budde <kernel@pengutronix.de>");
1188MODULE_LICENSE("GPL v2");
1189MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1190
