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33#include <linux/highmem.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/interrupt.h>
42#include <linux/delay.h>
43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
48#include <linux/kmod.h>
49#include <linux/mlx5/mlx5_ifc.h>
50#include <linux/mlx5/vport.h>
51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
54#include <net/devlink.h>
55#include "mlx5_core.h"
56#include "lib/eq.h"
57#include "fs_core.h"
58#include "lib/mpfs.h"
59#include "eswitch.h"
60#include "lib/mlx5.h"
61#include "fpga/core.h"
62#include "fpga/ipsec.h"
63#include "accel/ipsec.h"
64#include "accel/tls.h"
65#include "lib/clock.h"
66#include "lib/vxlan.h"
67#include "lib/devcom.h"
68#include "diag/fw_tracer.h"
69
70MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
71MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
72MODULE_LICENSE("Dual BSD/GPL");
73MODULE_VERSION(DRIVER_VERSION);
74
75unsigned int mlx5_core_debug_mask;
76module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
77MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
78
79#define MLX5_DEFAULT_PROF 2
80static unsigned int prof_sel = MLX5_DEFAULT_PROF;
81module_param_named(prof_sel, prof_sel, uint, 0444);
82MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
83
84static u32 sw_owner_id[4];
85
86enum {
87 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
88 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
89};
90
91static struct mlx5_profile profile[] = {
92 [0] = {
93 .mask = 0,
94 },
95 [1] = {
96 .mask = MLX5_PROF_MASK_QP_SIZE,
97 .log_max_qp = 12,
98 },
99 [2] = {
100 .mask = MLX5_PROF_MASK_QP_SIZE |
101 MLX5_PROF_MASK_MR_CACHE,
102 .log_max_qp = 18,
103 .mr_cache[0] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[1] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[2] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[3] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[4] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[5] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[6] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[7] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[8] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[9] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[10] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[11] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[12] = {
152 .size = 64,
153 .limit = 32
154 },
155 .mr_cache[13] = {
156 .size = 32,
157 .limit = 16
158 },
159 .mr_cache[14] = {
160 .size = 16,
161 .limit = 8
162 },
163 .mr_cache[15] = {
164 .size = 8,
165 .limit = 4
166 },
167 },
168};
169
170#define FW_INIT_TIMEOUT_MILI 2000
171#define FW_INIT_WAIT_MS 2
172#define FW_PRE_INIT_TIMEOUT_MILI 10000
173
174static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
175{
176 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
177 int err = 0;
178
179 while (fw_initializing(dev)) {
180 if (time_after(jiffies, end)) {
181 err = -EBUSY;
182 break;
183 }
184 msleep(FW_INIT_WAIT_MS);
185 }
186
187 return err;
188}
189
190static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
191{
192 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
193 driver_version);
194 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
195 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
196 int remaining_size = driver_ver_sz;
197 char *string;
198
199 if (!MLX5_CAP_GEN(dev, driver_version))
200 return;
201
202 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
203
204 strncpy(string, "Linux", remaining_size);
205
206 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
207 strncat(string, ",", remaining_size);
208
209 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
210 strncat(string, DRIVER_NAME, remaining_size);
211
212 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
213 strncat(string, ",", remaining_size);
214
215 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
216 strncat(string, DRIVER_VERSION, remaining_size);
217
218
219 MLX5_SET(set_driver_version_in, in, opcode,
220 MLX5_CMD_OP_SET_DRIVER_VERSION);
221
222 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
223}
224
225static int set_dma_caps(struct pci_dev *pdev)
226{
227 int err;
228
229 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
230 if (err) {
231 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
232 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
233 if (err) {
234 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
235 return err;
236 }
237 }
238
239 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
240 if (err) {
241 dev_warn(&pdev->dev,
242 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
243 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
244 if (err) {
245 dev_err(&pdev->dev,
246 "Can't set consistent PCI DMA mask, aborting\n");
247 return err;
248 }
249 }
250
251 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
252 return err;
253}
254
255static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
256{
257 struct pci_dev *pdev = dev->pdev;
258 int err = 0;
259
260 mutex_lock(&dev->pci_status_mutex);
261 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
262 err = pci_enable_device(pdev);
263 if (!err)
264 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
265 }
266 mutex_unlock(&dev->pci_status_mutex);
267
268 return err;
269}
270
271static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
272{
273 struct pci_dev *pdev = dev->pdev;
274
275 mutex_lock(&dev->pci_status_mutex);
276 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
277 pci_disable_device(pdev);
278 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
279 }
280 mutex_unlock(&dev->pci_status_mutex);
281}
282
283static int request_bar(struct pci_dev *pdev)
284{
285 int err = 0;
286
287 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
288 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
289 return -ENODEV;
290 }
291
292 err = pci_request_regions(pdev, DRIVER_NAME);
293 if (err)
294 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
295
296 return err;
297}
298
299static void release_bar(struct pci_dev *pdev)
300{
301 pci_release_regions(pdev);
302}
303
304struct mlx5_reg_host_endianness {
305 u8 he;
306 u8 rsvd[15];
307};
308
309#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
310
311enum {
312 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
313 MLX5_DEV_CAP_FLAG_DCT,
314};
315
316static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
317{
318 switch (size) {
319 case 128:
320 return 0;
321 case 256:
322 return 1;
323 case 512:
324 return 2;
325 case 1024:
326 return 3;
327 case 2048:
328 return 4;
329 case 4096:
330 return 5;
331 default:
332 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
333 return 0;
334 }
335}
336
337static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
338 enum mlx5_cap_type cap_type,
339 enum mlx5_cap_mode cap_mode)
340{
341 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
342 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
343 void *out, *hca_caps;
344 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
345 int err;
346
347 memset(in, 0, sizeof(in));
348 out = kzalloc(out_sz, GFP_KERNEL);
349 if (!out)
350 return -ENOMEM;
351
352 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
353 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
354 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
355 if (err) {
356 mlx5_core_warn(dev,
357 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
358 cap_type, cap_mode, err);
359 goto query_ex;
360 }
361
362 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
363
364 switch (cap_mode) {
365 case HCA_CAP_OPMOD_GET_MAX:
366 memcpy(dev->caps.hca_max[cap_type], hca_caps,
367 MLX5_UN_SZ_BYTES(hca_cap_union));
368 break;
369 case HCA_CAP_OPMOD_GET_CUR:
370 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
371 MLX5_UN_SZ_BYTES(hca_cap_union));
372 break;
373 default:
374 mlx5_core_warn(dev,
375 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
376 cap_type, cap_mode);
377 err = -EINVAL;
378 break;
379 }
380query_ex:
381 kfree(out);
382 return err;
383}
384
385int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
386{
387 int ret;
388
389 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
390 if (ret)
391 return ret;
392 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
393}
394
395static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
396{
397 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
398
399 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
400 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
401 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
402}
403
404static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
405{
406 void *set_ctx;
407 void *set_hca_cap;
408 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
409 int req_endianness;
410 int err;
411
412 if (MLX5_CAP_GEN(dev, atomic)) {
413 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
414 if (err)
415 return err;
416 } else {
417 return 0;
418 }
419
420 req_endianness =
421 MLX5_CAP_ATOMIC(dev,
422 supported_atomic_req_8B_endianness_mode_1);
423
424 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
425 return 0;
426
427 set_ctx = kzalloc(set_sz, GFP_KERNEL);
428 if (!set_ctx)
429 return -ENOMEM;
430
431 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
432
433
434 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
435 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
436
437 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
438
439 kfree(set_ctx);
440 return err;
441}
442
443static int handle_hca_cap(struct mlx5_core_dev *dev)
444{
445 void *set_ctx = NULL;
446 struct mlx5_profile *prof = dev->profile;
447 int err = -ENOMEM;
448 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
449 void *set_hca_cap;
450
451 set_ctx = kzalloc(set_sz, GFP_KERNEL);
452 if (!set_ctx)
453 goto query_ex;
454
455 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
456 if (err)
457 goto query_ex;
458
459 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
460 capability);
461 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
462 MLX5_ST_SZ_BYTES(cmd_hca_cap));
463
464 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
465 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
466 128);
467
468 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
469 to_fw_pkey_sz(dev, 128));
470
471
472 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
473 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
474 profile[prof_sel].log_max_qp,
475 MLX5_CAP_GEN_MAX(dev, log_max_qp));
476 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
477 }
478 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
479 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
480 prof->log_max_qp);
481
482
483 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
484
485
486
487
488 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
489 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
490
491 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
492
493 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
494 MLX5_SET(cmd_hca_cap,
495 set_hca_cap,
496 cache_line_128byte,
497 cache_line_size() >= 128 ? 1 : 0);
498
499 if (MLX5_CAP_GEN_MAX(dev, dct))
500 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
501
502 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
503 MLX5_SET(cmd_hca_cap,
504 set_hca_cap,
505 num_vhca_ports,
506 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
507
508 err = set_caps(dev, set_ctx, set_sz,
509 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
510
511query_ex:
512 kfree(set_ctx);
513 return err;
514}
515
516static int set_hca_ctrl(struct mlx5_core_dev *dev)
517{
518 struct mlx5_reg_host_endianness he_in;
519 struct mlx5_reg_host_endianness he_out;
520 int err;
521
522 if (!mlx5_core_is_pf(dev))
523 return 0;
524
525 memset(&he_in, 0, sizeof(he_in));
526 he_in.he = MLX5_SET_HOST_ENDIANNESS;
527 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
528 &he_out, sizeof(he_out),
529 MLX5_REG_HOST_ENDIANNESS, 0, 1);
530 return err;
531}
532
533static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
534{
535 int ret = 0;
536
537
538 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
539 ret = mlx5_nic_vport_update_local_lb(dev, false);
540
541 return ret;
542}
543
544int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
545{
546 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
547 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
548
549 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
550 MLX5_SET(enable_hca_in, in, function_id, func_id);
551 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
552}
553
554int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
555{
556 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
557 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
558
559 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
560 MLX5_SET(disable_hca_in, in, function_id, func_id);
561 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
562}
563
564u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
565 struct ptp_system_timestamp *sts)
566{
567 u32 timer_h, timer_h1, timer_l;
568
569 timer_h = ioread32be(&dev->iseg->internal_timer_h);
570 ptp_read_system_prets(sts);
571 timer_l = ioread32be(&dev->iseg->internal_timer_l);
572 ptp_read_system_postts(sts);
573 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
574 if (timer_h != timer_h1) {
575
576 ptp_read_system_prets(sts);
577 timer_l = ioread32be(&dev->iseg->internal_timer_l);
578 ptp_read_system_postts(sts);
579 }
580
581 return (u64)timer_l | (u64)timer_h1 << 32;
582}
583
584static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
585{
586 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
587 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
588 u32 sup_issi;
589 int err;
590
591 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
592 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
593 query_out, sizeof(query_out));
594 if (err) {
595 u32 syndrome;
596 u8 status;
597
598 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
599 if (!status || syndrome == MLX5_DRIVER_SYND) {
600 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
601 err, status, syndrome);
602 return err;
603 }
604
605 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
606 dev->issi = 0;
607 return 0;
608 }
609
610 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
611
612 if (sup_issi & (1 << 1)) {
613 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
614 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
615
616 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
617 MLX5_SET(set_issi_in, set_in, current_issi, 1);
618 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
619 set_out, sizeof(set_out));
620 if (err) {
621 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
622 err);
623 return err;
624 }
625
626 dev->issi = 1;
627
628 return 0;
629 } else if (sup_issi & (1 << 0) || !sup_issi) {
630 return 0;
631 }
632
633 return -EOPNOTSUPP;
634}
635
636
637static const struct pci_device_id mlx5_core_hw_unsupp_pci_table[] = {
638 { PCI_VDEVICE(MELLANOX, 0x101d) },
639 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF},
640 { 0, }
641};
642
643static char mlx5_pci_id[32];
644
645
646
647
648
649
650
651static void mlx5_check_hw_unsupp_status(struct pci_dev *pdev)
652{
653 const struct pci_device_id *found_id = NULL;
654
655 found_id = pci_match_id(mlx5_core_hw_unsupp_pci_table, pdev);
656
657 if (found_id) {
658 sprintf(mlx5_pci_id, "%s: %04x:%02x:%02x.%01x\n", "pci-device",
659 pci_domain_nr(pdev->bus), pdev->bus->number,
660 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
661
662 mark_hardware_unsupported(mlx5_pci_id);
663 }
664}
665
666static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
667{
668 struct pci_dev *pdev = dev->pdev;
669 int err = 0;
670
671 pci_set_drvdata(dev->pdev, dev);
672 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
673 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
674
675 mutex_init(&priv->pgdir_mutex);
676 INIT_LIST_HEAD(&priv->pgdir_list);
677 spin_lock_init(&priv->mkey_lock);
678
679 mutex_init(&priv->alloc_mutex);
680
681 priv->numa_node = dev_to_node(&dev->pdev->dev);
682
683 if (mlx5_debugfs_root)
684 priv->dbg_root =
685 debugfs_create_dir(pci_name(pdev), mlx5_debugfs_root);
686
687 err = mlx5_pci_enable_device(dev);
688 if (err) {
689 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
690 goto err_dbg;
691 }
692
693 err = request_bar(pdev);
694 if (err) {
695 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
696 goto err_disable;
697 }
698
699 pci_set_master(pdev);
700
701 err = set_dma_caps(pdev);
702 if (err) {
703 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
704 goto err_clr_master;
705 }
706
707 dev->iseg_base = pci_resource_start(dev->pdev, 0);
708 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
709 if (!dev->iseg) {
710 err = -ENOMEM;
711 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
712 goto err_clr_master;
713 }
714
715 mlx5_check_hw_unsupp_status(pdev);
716 return 0;
717
718err_clr_master:
719 pci_clear_master(dev->pdev);
720 release_bar(dev->pdev);
721err_disable:
722 mlx5_pci_disable_device(dev);
723
724err_dbg:
725 debugfs_remove(priv->dbg_root);
726 return err;
727}
728
729static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
730{
731 iounmap(dev->iseg);
732 pci_clear_master(dev->pdev);
733 release_bar(dev->pdev);
734 mlx5_pci_disable_device(dev);
735 debugfs_remove_recursive(priv->dbg_root);
736}
737
738static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
739{
740 struct pci_dev *pdev = dev->pdev;
741 int err;
742
743 priv->devcom = mlx5_devcom_register_device(dev);
744 if (IS_ERR(priv->devcom))
745 dev_err(&pdev->dev, "failed to register with devcom (0x%p)\n",
746 priv->devcom);
747
748 err = mlx5_query_board_id(dev);
749 if (err) {
750 dev_err(&pdev->dev, "query board id failed\n");
751 goto err_devcom;
752 }
753
754 err = mlx5_eq_table_init(dev);
755 if (err) {
756 dev_err(&pdev->dev, "failed to initialize eq\n");
757 goto err_devcom;
758 }
759
760 err = mlx5_cq_debugfs_init(dev);
761 if (err) {
762 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
763 goto err_eq_cleanup;
764 }
765
766 mlx5_init_qp_table(dev);
767
768 mlx5_init_srq_table(dev);
769
770 mlx5_init_mkey_table(dev);
771
772 mlx5_init_reserved_gids(dev);
773
774 mlx5_init_clock(dev);
775
776 dev->vxlan = mlx5_vxlan_create(dev);
777
778 err = mlx5_init_rl_table(dev);
779 if (err) {
780 dev_err(&pdev->dev, "Failed to init rate limiting\n");
781 goto err_tables_cleanup;
782 }
783
784 err = mlx5_mpfs_init(dev);
785 if (err) {
786 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
787 goto err_rl_cleanup;
788 }
789
790 err = mlx5_eswitch_init(dev);
791 if (err) {
792 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
793 goto err_mpfs_cleanup;
794 }
795
796 err = mlx5_sriov_init(dev);
797 if (err) {
798 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
799 goto err_eswitch_cleanup;
800 }
801
802 err = mlx5_fpga_init(dev);
803 if (err) {
804 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
805 goto err_sriov_cleanup;
806 }
807
808 dev->tracer = mlx5_fw_tracer_create(dev);
809
810 return 0;
811
812err_sriov_cleanup:
813 mlx5_sriov_cleanup(dev);
814err_eswitch_cleanup:
815 mlx5_eswitch_cleanup(dev->priv.eswitch);
816err_mpfs_cleanup:
817 mlx5_mpfs_cleanup(dev);
818err_rl_cleanup:
819 mlx5_cleanup_rl_table(dev);
820err_tables_cleanup:
821 mlx5_vxlan_destroy(dev->vxlan);
822 mlx5_cleanup_mkey_table(dev);
823 mlx5_cleanup_srq_table(dev);
824 mlx5_cleanup_qp_table(dev);
825 mlx5_cq_debugfs_cleanup(dev);
826
827err_eq_cleanup:
828 mlx5_eq_table_cleanup(dev);
829err_devcom:
830 mlx5_devcom_unregister_device(dev->priv.devcom);
831
832 return err;
833}
834
835static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
836{
837 mlx5_fw_tracer_destroy(dev->tracer);
838 mlx5_fpga_cleanup(dev);
839 mlx5_sriov_cleanup(dev);
840 mlx5_eswitch_cleanup(dev->priv.eswitch);
841 mlx5_mpfs_cleanup(dev);
842 mlx5_cleanup_rl_table(dev);
843 mlx5_vxlan_destroy(dev->vxlan);
844 mlx5_cleanup_clock(dev);
845 mlx5_cleanup_reserved_gids(dev);
846 mlx5_cleanup_mkey_table(dev);
847 mlx5_cleanup_srq_table(dev);
848 mlx5_cleanup_qp_table(dev);
849 mlx5_cq_debugfs_cleanup(dev);
850 mlx5_eq_table_cleanup(dev);
851 mlx5_devcom_unregister_device(dev->priv.devcom);
852}
853
854static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
855 bool boot)
856{
857 struct pci_dev *pdev = dev->pdev;
858 int err;
859
860 mutex_lock(&dev->intf_state_mutex);
861 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
862 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
863 __func__);
864 goto out;
865 }
866
867 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
868 fw_rev_min(dev), fw_rev_sub(dev));
869
870
871 if (mlx5_core_is_pf(dev))
872 pcie_print_link_status(dev->pdev);
873
874
875
876
877 dev->state = MLX5_DEVICE_STATE_UP;
878
879
880
881 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
882 if (err) {
883 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
884 FW_PRE_INIT_TIMEOUT_MILI);
885 goto out_err;
886 }
887
888 err = mlx5_cmd_init(dev);
889 if (err) {
890 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
891 goto out_err;
892 }
893
894 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
895 if (err) {
896 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
897 FW_INIT_TIMEOUT_MILI);
898 goto err_cmd_cleanup;
899 }
900
901 err = mlx5_core_enable_hca(dev, 0);
902 if (err) {
903 dev_err(&pdev->dev, "enable hca failed\n");
904 goto err_cmd_cleanup;
905 }
906
907 err = mlx5_core_set_issi(dev);
908 if (err) {
909 dev_err(&pdev->dev, "failed to set issi\n");
910 goto err_disable_hca;
911 }
912
913 err = mlx5_satisfy_startup_pages(dev, 1);
914 if (err) {
915 dev_err(&pdev->dev, "failed to allocate boot pages\n");
916 goto err_disable_hca;
917 }
918
919 err = set_hca_ctrl(dev);
920 if (err) {
921 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
922 goto reclaim_boot_pages;
923 }
924
925 err = handle_hca_cap(dev);
926 if (err) {
927 dev_err(&pdev->dev, "handle_hca_cap failed\n");
928 goto reclaim_boot_pages;
929 }
930
931 err = handle_hca_cap_atomic(dev);
932 if (err) {
933 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
934 goto reclaim_boot_pages;
935 }
936
937 err = mlx5_satisfy_startup_pages(dev, 0);
938 if (err) {
939 dev_err(&pdev->dev, "failed to allocate init pages\n");
940 goto reclaim_boot_pages;
941 }
942
943 err = mlx5_pagealloc_start(dev);
944 if (err) {
945 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
946 goto reclaim_boot_pages;
947 }
948
949 err = mlx5_cmd_init_hca(dev, sw_owner_id);
950 if (err) {
951 dev_err(&pdev->dev, "init hca failed\n");
952 goto err_pagealloc_stop;
953 }
954
955 mlx5_set_driver_version(dev);
956
957 mlx5_start_health_poll(dev);
958
959 err = mlx5_query_hca_caps(dev);
960 if (err) {
961 dev_err(&pdev->dev, "query hca failed\n");
962 goto err_stop_poll;
963 }
964
965 if (boot) {
966 err = mlx5_init_once(dev, priv);
967 if (err) {
968 dev_err(&pdev->dev, "sw objs init failed\n");
969 goto err_stop_poll;
970 }
971 }
972
973 dev->priv.uar = mlx5_get_uars_page(dev);
974 if (IS_ERR(dev->priv.uar)) {
975 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
976 err = PTR_ERR(dev->priv.uar);
977 goto err_get_uars;
978 }
979
980 err = mlx5_eq_table_create(dev);
981 if (err) {
982 dev_err(&pdev->dev, "Failed to create EQs\n");
983 goto err_eq_table;
984 }
985
986 err = mlx5_fw_tracer_init(dev->tracer);
987 if (err) {
988 dev_err(&pdev->dev, "Failed to init FW tracer\n");
989 goto err_fw_tracer;
990 }
991
992 err = mlx5_fpga_device_start(dev);
993 if (err) {
994 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
995 goto err_fpga_start;
996 }
997
998 err = mlx5_accel_ipsec_init(dev);
999 if (err) {
1000 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1001 goto err_ipsec_start;
1002 }
1003
1004 err = mlx5_accel_tls_init(dev);
1005 if (err) {
1006 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1007 goto err_tls_start;
1008 }
1009
1010 err = mlx5_init_fs(dev);
1011 if (err) {
1012 dev_err(&pdev->dev, "Failed to init flow steering\n");
1013 goto err_fs;
1014 }
1015
1016 err = mlx5_core_set_hca_defaults(dev);
1017 if (err) {
1018 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1019 goto err_sriov;
1020 }
1021
1022 err = mlx5_sriov_attach(dev);
1023 if (err) {
1024 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1025 goto err_sriov;
1026 }
1027
1028 if (mlx5_device_registered(dev)) {
1029 mlx5_attach_device(dev);
1030 } else {
1031 err = mlx5_register_device(dev);
1032 if (err) {
1033 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1034 goto err_reg_dev;
1035 }
1036 }
1037
1038 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1039out:
1040 mutex_unlock(&dev->intf_state_mutex);
1041
1042 return 0;
1043
1044err_reg_dev:
1045 mlx5_sriov_detach(dev);
1046
1047err_sriov:
1048 mlx5_cleanup_fs(dev);
1049
1050err_fs:
1051 mlx5_accel_tls_cleanup(dev);
1052
1053err_tls_start:
1054 mlx5_accel_ipsec_cleanup(dev);
1055
1056err_ipsec_start:
1057 mlx5_fpga_device_stop(dev);
1058
1059err_fpga_start:
1060 mlx5_fw_tracer_cleanup(dev->tracer);
1061
1062err_fw_tracer:
1063 mlx5_eq_table_destroy(dev);
1064
1065err_eq_table:
1066 mlx5_put_uars_page(dev, priv->uar);
1067
1068err_get_uars:
1069 if (boot)
1070 mlx5_cleanup_once(dev);
1071
1072err_stop_poll:
1073 mlx5_stop_health_poll(dev, boot);
1074 if (mlx5_cmd_teardown_hca(dev)) {
1075 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1076 goto out_err;
1077 }
1078
1079err_pagealloc_stop:
1080 mlx5_pagealloc_stop(dev);
1081
1082reclaim_boot_pages:
1083 mlx5_reclaim_startup_pages(dev);
1084
1085err_disable_hca:
1086 mlx5_core_disable_hca(dev, 0);
1087
1088err_cmd_cleanup:
1089 mlx5_cmd_cleanup(dev);
1090
1091out_err:
1092 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1093 mutex_unlock(&dev->intf_state_mutex);
1094
1095 return err;
1096}
1097
1098static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1099 bool cleanup)
1100{
1101 int err = 0;
1102
1103 if (cleanup)
1104 mlx5_drain_health_recovery(dev);
1105
1106 mutex_lock(&dev->intf_state_mutex);
1107 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1108 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1109 __func__);
1110 if (cleanup)
1111 mlx5_cleanup_once(dev);
1112 goto out;
1113 }
1114
1115 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1116
1117 if (mlx5_device_registered(dev))
1118 mlx5_detach_device(dev);
1119
1120 mlx5_sriov_detach(dev);
1121 mlx5_cleanup_fs(dev);
1122 mlx5_accel_ipsec_cleanup(dev);
1123 mlx5_accel_tls_cleanup(dev);
1124 mlx5_fpga_device_stop(dev);
1125 mlx5_fw_tracer_cleanup(dev->tracer);
1126 mlx5_eq_table_destroy(dev);
1127 mlx5_put_uars_page(dev, priv->uar);
1128 if (cleanup)
1129 mlx5_cleanup_once(dev);
1130 mlx5_stop_health_poll(dev, cleanup);
1131 err = mlx5_cmd_teardown_hca(dev);
1132 if (err) {
1133 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1134 goto out;
1135 }
1136 mlx5_pagealloc_stop(dev);
1137 mlx5_reclaim_startup_pages(dev);
1138 mlx5_core_disable_hca(dev, 0);
1139 mlx5_cmd_cleanup(dev);
1140
1141out:
1142 mutex_unlock(&dev->intf_state_mutex);
1143 return err;
1144}
1145
1146struct mlx5_core_event_handler {
1147 void (*event)(struct mlx5_core_dev *dev,
1148 enum mlx5_dev_event event,
1149 void *data);
1150};
1151
1152static const struct devlink_ops mlx5_devlink_ops = {
1153#ifdef CONFIG_MLX5_ESWITCH
1154 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1155 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1156 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1157 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1158 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1159 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1160#endif
1161};
1162
1163#define MLX5_IB_MOD "mlx5_ib"
1164static int init_one(struct pci_dev *pdev,
1165 const struct pci_device_id *id)
1166{
1167 struct mlx5_core_dev *dev;
1168 struct devlink *devlink;
1169 struct mlx5_priv *priv;
1170 int err;
1171
1172 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1173 if (!devlink) {
1174 dev_err(&pdev->dev, "kzalloc failed\n");
1175 return -ENOMEM;
1176 }
1177
1178 dev = devlink_priv(devlink);
1179 priv = &dev->priv;
1180 priv->pci_dev_data = id->driver_data;
1181
1182 pci_set_drvdata(pdev, dev);
1183
1184 dev->pdev = pdev;
1185 dev->event = mlx5_core_event;
1186 dev->profile = &profile[prof_sel];
1187
1188 INIT_LIST_HEAD(&priv->ctx_list);
1189 spin_lock_init(&priv->ctx_lock);
1190 mutex_init(&dev->pci_status_mutex);
1191 mutex_init(&dev->intf_state_mutex);
1192
1193 INIT_LIST_HEAD(&priv->waiting_events_list);
1194 priv->is_accum_events = false;
1195
1196 mutex_init(&priv->bfregs.reg_head.lock);
1197 mutex_init(&priv->bfregs.wc_head.lock);
1198 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1199 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1200
1201 err = mlx5_pci_init(dev, priv);
1202 if (err) {
1203 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1204 goto clean_dev;
1205 }
1206
1207 err = mlx5_health_init(dev);
1208 if (err) {
1209 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1210 goto close_pci;
1211 }
1212
1213 mlx5_pagealloc_init(dev);
1214
1215 err = mlx5_load_one(dev, priv, true);
1216 if (err) {
1217 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1218 goto clean_health;
1219 }
1220
1221 request_module_nowait(MLX5_IB_MOD);
1222
1223 err = devlink_register(devlink, &pdev->dev);
1224 if (err)
1225 goto clean_load;
1226
1227 pci_save_state(pdev);
1228 return 0;
1229
1230clean_load:
1231 mlx5_unload_one(dev, priv, true);
1232clean_health:
1233 mlx5_pagealloc_cleanup(dev);
1234 mlx5_health_cleanup(dev);
1235close_pci:
1236 mlx5_pci_close(dev, priv);
1237clean_dev:
1238 devlink_free(devlink);
1239
1240 return err;
1241}
1242
1243static void remove_one(struct pci_dev *pdev)
1244{
1245 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1246 struct devlink *devlink = priv_to_devlink(dev);
1247 struct mlx5_priv *priv = &dev->priv;
1248
1249 devlink_unregister(devlink);
1250 mlx5_unregister_device(dev);
1251
1252 if (mlx5_unload_one(dev, priv, true)) {
1253 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1254 mlx5_health_cleanup(dev);
1255 return;
1256 }
1257
1258 mlx5_pagealloc_cleanup(dev);
1259 mlx5_health_cleanup(dev);
1260 mlx5_pci_close(dev, priv);
1261 devlink_free(devlink);
1262}
1263
1264static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1265 pci_channel_state_t state)
1266{
1267 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1268 struct mlx5_priv *priv = &dev->priv;
1269
1270 dev_info(&pdev->dev, "%s was called\n", __func__);
1271
1272 mlx5_enter_error_state(dev);
1273 mlx5_unload_one(dev, priv, false);
1274
1275 if (state) {
1276 mlx5_drain_health_wq(dev);
1277 mlx5_pci_disable_device(dev);
1278 }
1279
1280 return state == pci_channel_io_perm_failure ?
1281 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1282}
1283
1284
1285
1286
1287static int wait_vital(struct pci_dev *pdev)
1288{
1289 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1290 struct mlx5_core_health *health = &dev->priv.health;
1291 const int niter = 100;
1292 u32 last_count = 0;
1293 u32 count;
1294 int i;
1295
1296 for (i = 0; i < niter; i++) {
1297 count = ioread32be(health->health_counter);
1298 if (count && count != 0xffffffff) {
1299 if (last_count && last_count != count) {
1300 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1301 return 0;
1302 }
1303 last_count = count;
1304 }
1305 msleep(50);
1306 }
1307
1308 return -ETIMEDOUT;
1309}
1310
1311static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1312{
1313 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1314 int err;
1315
1316 dev_info(&pdev->dev, "%s was called\n", __func__);
1317
1318 err = mlx5_pci_enable_device(dev);
1319 if (err) {
1320 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1321 , __func__, err);
1322 return PCI_ERS_RESULT_DISCONNECT;
1323 }
1324
1325 pci_set_master(pdev);
1326 pci_restore_state(pdev);
1327 pci_save_state(pdev);
1328
1329 if (wait_vital(pdev)) {
1330 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1331 return PCI_ERS_RESULT_DISCONNECT;
1332 }
1333
1334 return PCI_ERS_RESULT_RECOVERED;
1335}
1336
1337static void mlx5_pci_resume(struct pci_dev *pdev)
1338{
1339 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1340 struct mlx5_priv *priv = &dev->priv;
1341 int err;
1342
1343 dev_info(&pdev->dev, "%s was called\n", __func__);
1344
1345 err = mlx5_load_one(dev, priv, false);
1346 if (err)
1347 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1348 , __func__, err);
1349 else
1350 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1351}
1352
1353static const struct pci_error_handlers mlx5_err_handler = {
1354 .error_detected = mlx5_pci_err_detected,
1355 .slot_reset = mlx5_pci_slot_reset,
1356 .resume = mlx5_pci_resume
1357};
1358
1359static void shutdown(struct pci_dev *pdev)
1360{
1361 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1362 struct mlx5_priv *priv = &dev->priv;
1363
1364 dev_info(&pdev->dev, "Shutdown was called\n");
1365 mlx5_unload_one(dev, priv, false);
1366 mlx5_pci_disable_device(dev);
1367}
1368
1369static const struct pci_device_id mlx5_core_pci_table[] = {
1370 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1371 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},
1372 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1373 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},
1374 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1375 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},
1376 { PCI_VDEVICE(MELLANOX, 0x1017) },
1377 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},
1378 { PCI_VDEVICE(MELLANOX, 0x1019) },
1379 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF},
1380 { PCI_VDEVICE(MELLANOX, 0x101b) },
1381 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF},
1382 { PCI_VDEVICE(MELLANOX, 0x101d) },
1383 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF},
1384 { PCI_VDEVICE(MELLANOX, 0xa2d2) },
1385 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF},
1386 { 0, }
1387};
1388
1389MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1390
1391void mlx5_disable_device(struct mlx5_core_dev *dev)
1392{
1393 mlx5_pci_err_detected(dev->pdev, 0);
1394}
1395
1396void mlx5_recover_device(struct mlx5_core_dev *dev)
1397{
1398 mlx5_pci_disable_device(dev);
1399 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1400 mlx5_pci_resume(dev->pdev);
1401}
1402
1403static struct pci_driver mlx5_core_driver = {
1404 .name = DRIVER_NAME,
1405 .id_table = mlx5_core_pci_table,
1406 .probe = init_one,
1407 .remove = remove_one,
1408 .shutdown = shutdown,
1409 .err_handler = &mlx5_err_handler,
1410 .sriov_configure = mlx5_core_sriov_configure,
1411};
1412
1413static void mlx5_core_verify_params(void)
1414{
1415 if (prof_sel >= ARRAY_SIZE(profile)) {
1416 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1417 prof_sel,
1418 ARRAY_SIZE(profile) - 1,
1419 MLX5_DEFAULT_PROF);
1420 prof_sel = MLX5_DEFAULT_PROF;
1421 }
1422}
1423
1424static int __init init(void)
1425{
1426 int err;
1427
1428 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1429
1430 mlx5_core_verify_params();
1431 mlx5_fpga_ipsec_build_fs_cmds();
1432 mlx5_register_debugfs();
1433
1434 err = pci_register_driver(&mlx5_core_driver);
1435 if (err)
1436 goto err_debug;
1437
1438#ifdef CONFIG_MLX5_CORE_EN
1439 mlx5e_init();
1440#endif
1441
1442 return 0;
1443
1444err_debug:
1445 mlx5_unregister_debugfs();
1446 return err;
1447}
1448
1449static void __exit cleanup(void)
1450{
1451#ifdef CONFIG_MLX5_CORE_EN
1452 mlx5e_cleanup();
1453#endif
1454 pci_unregister_driver(&mlx5_core_driver);
1455 mlx5_unregister_debugfs();
1456}
1457
1458module_init(init);
1459module_exit(cleanup);
1460
