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26#ifndef __RTL8723BE_DEF_H__
27#define __RTL8723BE_DEF_H__
28
29#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
30#define HAL_PRIME_CHNL_OFFSET_LOWER 1
31#define HAL_PRIME_CHNL_OFFSET_UPPER 2
32
33
34#define RX_MPDU_QUEUE 0
35#define CHIP_8723B (BIT(1) | BIT(2))
36#define NORMAL_CHIP BIT(3)
37#define CHIP_VENDOR_SMIC BIT(8)
38
39#define EXT_VENDOR_ID (BIT(18) | BIT(19))
40
41enum rx_packet_type {
42 NORMAL_RX,
43 TX_REPORT1,
44 TX_REPORT2,
45 HIS_REPORT,
46 C2H_PACKET,
47};
48
49enum rtl_desc_qsel {
50 QSLT_BK = 0x2,
51 QSLT_BE = 0x0,
52 QSLT_VI = 0x5,
53 QSLT_VO = 0x7,
54 QSLT_BEACON = 0x10,
55 QSLT_HIGH = 0x11,
56 QSLT_MGNT = 0x12,
57 QSLT_CMD = 0x13,
58};
59
60enum rtl_desc8723e_rate {
61 DESC92C_RATE1M = 0x00,
62 DESC92C_RATE2M = 0x01,
63 DESC92C_RATE5_5M = 0x02,
64 DESC92C_RATE11M = 0x03,
65
66 DESC92C_RATE6M = 0x04,
67 DESC92C_RATE9M = 0x05,
68 DESC92C_RATE12M = 0x06,
69 DESC92C_RATE18M = 0x07,
70 DESC92C_RATE24M = 0x08,
71 DESC92C_RATE36M = 0x09,
72 DESC92C_RATE48M = 0x0a,
73 DESC92C_RATE54M = 0x0b,
74
75 DESC92C_RATEMCS0 = 0x0c,
76 DESC92C_RATEMCS1 = 0x0d,
77 DESC92C_RATEMCS2 = 0x0e,
78 DESC92C_RATEMCS3 = 0x0f,
79 DESC92C_RATEMCS4 = 0x10,
80 DESC92C_RATEMCS5 = 0x11,
81 DESC92C_RATEMCS6 = 0x12,
82 DESC92C_RATEMCS7 = 0x13,
83 DESC92C_RATEMCS8 = 0x14,
84 DESC92C_RATEMCS9 = 0x15,
85 DESC92C_RATEMCS10 = 0x16,
86 DESC92C_RATEMCS11 = 0x17,
87 DESC92C_RATEMCS12 = 0x18,
88 DESC92C_RATEMCS13 = 0x19,
89 DESC92C_RATEMCS14 = 0x1a,
90 DESC92C_RATEMCS15 = 0x1b,
91};
92#endif
93