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15#undef DEBUG
16#undef VERBOSE
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/ioport.h>
21#include <linux/types.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/timer.h>
26#include <linux/list.h>
27#include <linux/interrupt.h>
28#include <linux/proc_fs.h>
29#include <linux/mm.h>
30#include <linux/moduleparam.h>
31#include <linux/platform_device.h>
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
34#include <linux/usb/otg.h>
35#include <linux/dma-mapping.h>
36#include <linux/clk.h>
37#include <linux/err.h>
38#include <linux/prefetch.h>
39#include <linux/io.h>
40
41#include <asm/byteorder.h>
42#include <asm/irq.h>
43#include <asm/unaligned.h>
44#include <asm/mach-types.h>
45
46#include <linux/omap-dma.h>
47
48#include <mach/usb.h>
49
50#include "omap_udc.h"
51
52#undef USB_TRACE
53
54
55#define USE_DMA
56
57
58#define USE_ISO
59
60#define DRIVER_DESC "OMAP UDC driver"
61#define DRIVER_VERSION "4 October 2004"
62
63#define OMAP_DMA_USB_W2FC_TX0 29
64#define OMAP_DMA_USB_W2FC_RX0 26
65
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86#ifdef USE_ISO
87static unsigned fifo_mode = 3;
88#else
89static unsigned fifo_mode;
90#endif
91
92
93
94
95module_param(fifo_mode, uint, 0);
96MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
97
98#ifdef USE_DMA
99static bool use_dma = 1;
100
101
102
103
104module_param(use_dma, bool, 0);
105MODULE_PARM_DESC(use_dma, "enable/disable DMA");
106#else
107
108
109#define use_dma 0
110#endif
111
112
113static const char driver_name[] = "omap_udc";
114static const char driver_desc[] = DRIVER_DESC;
115
116
117
118
119
120
121
122static void use_ep(struct omap_ep *ep, u16 select)
123{
124 u16 num = ep->bEndpointAddress & 0x0f;
125
126 if (ep->bEndpointAddress & USB_DIR_IN)
127 num |= UDC_EP_DIR;
128 omap_writew(num | select, UDC_EP_NUM);
129
130}
131
132static inline void deselect_ep(void)
133{
134 u16 w;
135
136 w = omap_readw(UDC_EP_NUM);
137 w &= ~UDC_EP_SEL;
138 omap_writew(w, UDC_EP_NUM);
139
140}
141
142static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
143
144
145
146static int omap_ep_enable(struct usb_ep *_ep,
147 const struct usb_endpoint_descriptor *desc)
148{
149 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
150 struct omap_udc *udc;
151 unsigned long flags;
152 u16 maxp;
153
154
155 if (!_ep || !desc
156 || desc->bDescriptorType != USB_DT_ENDPOINT
157 || ep->bEndpointAddress != desc->bEndpointAddress
158 || ep->maxpacket < usb_endpoint_maxp(desc)) {
159 DBG("%s, bad ep or descriptor\n", __func__);
160 return -EINVAL;
161 }
162 maxp = usb_endpoint_maxp(desc);
163 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
164 && maxp != ep->maxpacket)
165 || usb_endpoint_maxp(desc) > ep->maxpacket
166 || !desc->wMaxPacketSize) {
167 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
168 return -ERANGE;
169 }
170
171#ifdef USE_ISO
172 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
173 && desc->bInterval != 1)) {
174
175 DBG("%s, unsupported ISO period %dms\n", _ep->name,
176 1 << (desc->bInterval - 1));
177 return -EDOM;
178 }
179#else
180 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
181 DBG("%s, ISO nyet\n", _ep->name);
182 return -EDOM;
183 }
184#endif
185
186
187 if (ep->bmAttributes != desc->bmAttributes
188 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
189 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
190 DBG("%s, %s type mismatch\n", __func__, _ep->name);
191 return -EINVAL;
192 }
193
194 udc = ep->udc;
195 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
196 DBG("%s, bogus device state\n", __func__);
197 return -ESHUTDOWN;
198 }
199
200 spin_lock_irqsave(&udc->lock, flags);
201
202 ep->ep.desc = desc;
203 ep->irqs = 0;
204 ep->stopped = 0;
205 ep->ep.maxpacket = maxp;
206
207
208 ep->dma_channel = 0;
209 ep->has_dma = 0;
210 ep->lch = -1;
211 use_ep(ep, UDC_EP_SEL);
212 omap_writew(udc->clr_halt, UDC_CTRL);
213 ep->ackwait = 0;
214 deselect_ep();
215
216 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
217 list_add(&ep->iso, &udc->iso);
218
219
220 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
221
222 dma_channel_claim(ep, 0);
223
224
225 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
226 && !ep->has_dma
227 && !(ep->bEndpointAddress & USB_DIR_IN)) {
228 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
229 ep->ackwait = 1 + ep->double_buf;
230 }
231
232 spin_unlock_irqrestore(&udc->lock, flags);
233 VDBG("%s enabled\n", _ep->name);
234 return 0;
235}
236
237static void nuke(struct omap_ep *, int status);
238
239static int omap_ep_disable(struct usb_ep *_ep)
240{
241 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
242 unsigned long flags;
243
244 if (!_ep || !ep->ep.desc) {
245 DBG("%s, %s not enabled\n", __func__,
246 _ep ? ep->ep.name : NULL);
247 return -EINVAL;
248 }
249
250 spin_lock_irqsave(&ep->udc->lock, flags);
251 ep->ep.desc = NULL;
252 nuke(ep, -ESHUTDOWN);
253 ep->ep.maxpacket = ep->maxpacket;
254 ep->has_dma = 0;
255 omap_writew(UDC_SET_HALT, UDC_CTRL);
256 list_del_init(&ep->iso);
257 del_timer(&ep->timer);
258
259 spin_unlock_irqrestore(&ep->udc->lock, flags);
260
261 VDBG("%s disabled\n", _ep->name);
262 return 0;
263}
264
265
266
267static struct usb_request *
268omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
269{
270 struct omap_req *req;
271
272 req = kzalloc(sizeof(*req), gfp_flags);
273 if (!req)
274 return NULL;
275
276 INIT_LIST_HEAD(&req->queue);
277
278 return &req->req;
279}
280
281static void
282omap_free_request(struct usb_ep *ep, struct usb_request *_req)
283{
284 struct omap_req *req = container_of(_req, struct omap_req, req);
285
286 kfree(req);
287}
288
289
290
291static void
292done(struct omap_ep *ep, struct omap_req *req, int status)
293{
294 struct omap_udc *udc = ep->udc;
295 unsigned stopped = ep->stopped;
296
297 list_del_init(&req->queue);
298
299 if (req->req.status == -EINPROGRESS)
300 req->req.status = status;
301 else
302 status = req->req.status;
303
304 if (use_dma && ep->has_dma)
305 usb_gadget_unmap_request(&udc->gadget, &req->req,
306 (ep->bEndpointAddress & USB_DIR_IN));
307
308#ifndef USB_TRACE
309 if (status && status != -ESHUTDOWN)
310#endif
311 VDBG("complete %s req %p stat %d len %u/%u\n",
312 ep->ep.name, &req->req, status,
313 req->req.actual, req->req.length);
314
315
316 ep->stopped = 1;
317 spin_unlock(&ep->udc->lock);
318 req->req.complete(&ep->ep, &req->req);
319 spin_lock(&ep->udc->lock);
320 ep->stopped = stopped;
321}
322
323
324
325#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
326#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
327
328#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
329#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
330
331static inline int
332write_packet(u8 *buf, struct omap_req *req, unsigned max)
333{
334 unsigned len;
335 u16 *wp;
336
337 len = min(req->req.length - req->req.actual, max);
338 req->req.actual += len;
339
340 max = len;
341 if (likely((((int)buf) & 1) == 0)) {
342 wp = (u16 *)buf;
343 while (max >= 2) {
344 omap_writew(*wp++, UDC_DATA);
345 max -= 2;
346 }
347 buf = (u8 *)wp;
348 }
349 while (max--)
350 omap_writeb(*buf++, UDC_DATA);
351 return len;
352}
353
354
355
356
357
358static int write_fifo(struct omap_ep *ep, struct omap_req *req)
359{
360 u8 *buf;
361 unsigned count;
362 int is_last;
363 u16 ep_stat;
364
365 buf = req->req.buf + req->req.actual;
366 prefetch(buf);
367
368
369 ep_stat = omap_readw(UDC_STAT_FLG);
370 if (ep_stat & UDC_FIFO_UNWRITABLE)
371 return 0;
372
373 count = ep->ep.maxpacket;
374 count = write_packet(buf, req, count);
375 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
376 ep->ackwait = 1;
377
378
379 if (count != ep->ep.maxpacket)
380 is_last = 1;
381 else if (req->req.length == req->req.actual
382 && !req->req.zero)
383 is_last = 1;
384 else
385 is_last = 0;
386
387
388
389
390
391 if (is_last)
392 done(ep, req, 0);
393 return is_last;
394}
395
396static inline int
397read_packet(u8 *buf, struct omap_req *req, unsigned avail)
398{
399 unsigned len;
400 u16 *wp;
401
402 len = min(req->req.length - req->req.actual, avail);
403 req->req.actual += len;
404 avail = len;
405
406 if (likely((((int)buf) & 1) == 0)) {
407 wp = (u16 *)buf;
408 while (avail >= 2) {
409 *wp++ = omap_readw(UDC_DATA);
410 avail -= 2;
411 }
412 buf = (u8 *)wp;
413 }
414 while (avail--)
415 *buf++ = omap_readb(UDC_DATA);
416 return len;
417}
418
419
420static int read_fifo(struct omap_ep *ep, struct omap_req *req)
421{
422 u8 *buf;
423 unsigned count, avail;
424 int is_last;
425
426 buf = req->req.buf + req->req.actual;
427 prefetchw(buf);
428
429 for (;;) {
430 u16 ep_stat = omap_readw(UDC_STAT_FLG);
431
432 is_last = 0;
433 if (ep_stat & FIFO_EMPTY) {
434 if (!ep->double_buf)
435 break;
436 ep->fnf = 1;
437 }
438 if (ep_stat & UDC_EP_HALTED)
439 break;
440
441 if (ep_stat & UDC_FIFO_FULL)
442 avail = ep->ep.maxpacket;
443 else {
444 avail = omap_readw(UDC_RXFSTAT);
445 ep->fnf = ep->double_buf;
446 }
447 count = read_packet(buf, req, avail);
448
449
450 if (count < ep->ep.maxpacket) {
451 is_last = 1;
452
453 if (count != avail) {
454 req->req.status = -EOVERFLOW;
455 avail -= count;
456 while (avail--)
457 omap_readw(UDC_DATA);
458 }
459 } else if (req->req.length == req->req.actual)
460 is_last = 1;
461 else
462 is_last = 0;
463
464 if (!ep->bEndpointAddress)
465 break;
466 if (is_last)
467 done(ep, req, 0);
468 break;
469 }
470 return is_last;
471}
472
473
474
475static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
476{
477 dma_addr_t end;
478
479
480
481
482 if (cpu_is_omap15xx())
483 return 0;
484
485 end = omap_get_dma_src_pos(ep->lch);
486 if (end == ep->dma_counter)
487 return 0;
488
489 end |= start & (0xffff << 16);
490 if (end < start)
491 end += 0x10000;
492 return end - start;
493}
494
495static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
496{
497 dma_addr_t end;
498
499 end = omap_get_dma_dst_pos(ep->lch);
500 if (end == ep->dma_counter)
501 return 0;
502
503 end |= start & (0xffff << 16);
504 if (cpu_is_omap15xx())
505 end++;
506 if (end < start)
507 end += 0x10000;
508 return end - start;
509}
510
511
512
513
514
515
516
517static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
518{
519 u16 txdma_ctrl, w;
520 unsigned length = req->req.length - req->req.actual;
521 const int sync_mode = cpu_is_omap15xx()
522 ? OMAP_DMA_SYNC_FRAME
523 : OMAP_DMA_SYNC_ELEMENT;
524 int dma_trigger = 0;
525
526
527 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
528 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
529 txdma_ctrl = UDC_TXN_EOT | length;
530 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
531 length, 1, sync_mode, dma_trigger, 0);
532 } else {
533 length = min(length / ep->maxpacket,
534 (unsigned) UDC_TXN_TSC + 1);
535 txdma_ctrl = length;
536 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
537 ep->ep.maxpacket >> 1, length, sync_mode,
538 dma_trigger, 0);
539 length *= ep->maxpacket;
540 }
541 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
542 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
543 0, 0);
544
545 omap_start_dma(ep->lch);
546 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
547 w = omap_readw(UDC_DMA_IRQ_EN);
548 w |= UDC_TX_DONE_IE(ep->dma_channel);
549 omap_writew(w, UDC_DMA_IRQ_EN);
550 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
551 req->dma_bytes = length;
552}
553
554static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
555{
556 u16 w;
557
558 if (status == 0) {
559 req->req.actual += req->dma_bytes;
560
561
562 if (req->req.actual < req->req.length)
563 return;
564 if (req->req.zero
565 && req->dma_bytes != 0
566 && (req->req.actual % ep->maxpacket) == 0)
567 return;
568 } else
569 req->req.actual += dma_src_len(ep, req->req.dma
570 + req->req.actual);
571
572
573 omap_stop_dma(ep->lch);
574 w = omap_readw(UDC_DMA_IRQ_EN);
575 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
576 omap_writew(w, UDC_DMA_IRQ_EN);
577 done(ep, req, status);
578}
579
580static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
581{
582 unsigned packets = req->req.length - req->req.actual;
583 int dma_trigger = 0;
584 u16 w;
585
586
587 packets /= ep->ep.maxpacket;
588 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
589 req->dma_bytes = packets * ep->ep.maxpacket;
590 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
591 ep->ep.maxpacket >> 1, packets,
592 OMAP_DMA_SYNC_ELEMENT,
593 dma_trigger, 0);
594 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
595 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
596 0, 0);
597 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
598
599 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
600 w = omap_readw(UDC_DMA_IRQ_EN);
601 w |= UDC_RX_EOT_IE(ep->dma_channel);
602 omap_writew(w, UDC_DMA_IRQ_EN);
603 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
604 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
605
606 omap_start_dma(ep->lch);
607}
608
609static void
610finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
611{
612 u16 count, w;
613
614 if (status == 0)
615 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
616 count = dma_dest_len(ep, req->req.dma + req->req.actual);
617 count += req->req.actual;
618 if (one)
619 count--;
620 if (count <= req->req.length)
621 req->req.actual = count;
622
623 if (count != req->dma_bytes || status)
624 omap_stop_dma(ep->lch);
625
626
627 else if (req->req.actual < req->req.length)
628 return;
629
630
631 w = omap_readw(UDC_DMA_IRQ_EN);
632 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
633 omap_writew(w, UDC_DMA_IRQ_EN);
634 done(ep, req, status);
635}
636
637static void dma_irq(struct omap_udc *udc, u16 irq_src)
638{
639 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
640 struct omap_ep *ep;
641 struct omap_req *req;
642
643
644 if (irq_src & UDC_TXN_DONE) {
645 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
646 ep->irqs++;
647
648 if (!list_empty(&ep->queue)) {
649 req = container_of(ep->queue.next,
650 struct omap_req, queue);
651 finish_in_dma(ep, req, 0);
652 }
653 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
654
655 if (!list_empty(&ep->queue)) {
656 req = container_of(ep->queue.next,
657 struct omap_req, queue);
658 next_in_dma(ep, req);
659 }
660 }
661
662
663 if (irq_src & UDC_RXN_EOT) {
664 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
665 ep->irqs++;
666
667 if (!list_empty(&ep->queue)) {
668 req = container_of(ep->queue.next,
669 struct omap_req, queue);
670 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
671 }
672 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
673
674 if (!list_empty(&ep->queue)) {
675 req = container_of(ep->queue.next,
676 struct omap_req, queue);
677 next_out_dma(ep, req);
678 }
679 }
680
681 if (irq_src & UDC_RXN_CNT) {
682 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
683 ep->irqs++;
684
685 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
686 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
687 }
688}
689
690static void dma_error(int lch, u16 ch_status, void *data)
691{
692 struct omap_ep *ep = data;
693
694
695
696 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
697
698
699}
700
701static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
702{
703 u16 reg;
704 int status, restart, is_in;
705 int dma_channel;
706
707 is_in = ep->bEndpointAddress & USB_DIR_IN;
708 if (is_in)
709 reg = omap_readw(UDC_TXDMA_CFG);
710 else
711 reg = omap_readw(UDC_RXDMA_CFG);
712 reg |= UDC_DMA_REQ;
713
714 ep->dma_channel = 0;
715 ep->lch = -1;
716 if (channel == 0 || channel > 3) {
717 if ((reg & 0x0f00) == 0)
718 channel = 3;
719 else if ((reg & 0x00f0) == 0)
720 channel = 2;
721 else if ((reg & 0x000f) == 0)
722 channel = 1;
723 else {
724 status = -EMLINK;
725 goto just_restart;
726 }
727 }
728 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
729 ep->dma_channel = channel;
730
731 if (is_in) {
732 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
733 status = omap_request_dma(dma_channel,
734 ep->ep.name, dma_error, ep, &ep->lch);
735 if (status == 0) {
736 omap_writew(reg, UDC_TXDMA_CFG);
737
738 omap_set_dma_src_burst_mode(ep->lch,
739 OMAP_DMA_DATA_BURST_4);
740 omap_set_dma_src_data_pack(ep->lch, 1);
741
742 omap_set_dma_dest_params(ep->lch,
743 OMAP_DMA_PORT_TIPB,
744 OMAP_DMA_AMODE_CONSTANT,
745 UDC_DATA_DMA,
746 0, 0);
747 }
748 } else {
749 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
750 status = omap_request_dma(dma_channel,
751 ep->ep.name, dma_error, ep, &ep->lch);
752 if (status == 0) {
753 omap_writew(reg, UDC_RXDMA_CFG);
754
755 omap_set_dma_src_params(ep->lch,
756 OMAP_DMA_PORT_TIPB,
757 OMAP_DMA_AMODE_CONSTANT,
758 UDC_DATA_DMA,
759 0, 0);
760
761 omap_set_dma_dest_burst_mode(ep->lch,
762 OMAP_DMA_DATA_BURST_4);
763 omap_set_dma_dest_data_pack(ep->lch, 1);
764 }
765 }
766 if (status)
767 ep->dma_channel = 0;
768 else {
769 ep->has_dma = 1;
770 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
771
772
773 if (!cpu_is_omap15xx())
774 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
775 }
776
777just_restart:
778
779 restart = !ep->stopped && !list_empty(&ep->queue);
780
781 if (status)
782 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
783 restart ? " (restart)" : "");
784 else
785 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
786 is_in ? 't' : 'r',
787 ep->dma_channel - 1, ep->lch,
788 restart ? " (restart)" : "");
789
790 if (restart) {
791 struct omap_req *req;
792 req = container_of(ep->queue.next, struct omap_req, queue);
793 if (ep->has_dma)
794 (is_in ? next_in_dma : next_out_dma)(ep, req);
795 else {
796 use_ep(ep, UDC_EP_SEL);
797 (is_in ? write_fifo : read_fifo)(ep, req);
798 deselect_ep();
799 if (!is_in) {
800 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
801 ep->ackwait = 1 + ep->double_buf;
802 }
803
804 }
805 }
806}
807
808static void dma_channel_release(struct omap_ep *ep)
809{
810 int shift = 4 * (ep->dma_channel - 1);
811 u16 mask = 0x0f << shift;
812 struct omap_req *req;
813 int active;
814
815
816 if (!list_empty(&ep->queue))
817 req = container_of(ep->queue.next, struct omap_req, queue);
818 else
819 req = NULL;
820
821 active = omap_get_dma_active_status(ep->lch);
822
823 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
824 active ? "active" : "idle",
825 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
826 ep->dma_channel - 1, req);
827
828
829
830
831
832
833 if (ep->bEndpointAddress & USB_DIR_IN) {
834 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
835 UDC_TXDMA_CFG);
836
837 if (req) {
838 finish_in_dma(ep, req, -ECONNRESET);
839
840
841 use_ep(ep, UDC_EP_SEL);
842 omap_writew(UDC_CLR_EP, UDC_CTRL);
843 deselect_ep();
844 }
845 while (omap_readw(UDC_TXDMA_CFG) & mask)
846 udelay(10);
847 } else {
848 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
849 UDC_RXDMA_CFG);
850
851
852 while (omap_readw(UDC_RXDMA_CFG) & mask)
853 udelay(10);
854 if (req)
855 finish_out_dma(ep, req, -ECONNRESET, 0);
856 }
857 omap_free_dma(ep->lch);
858 ep->dma_channel = 0;
859 ep->lch = -1;
860
861}
862
863
864
865
866static int
867omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
868{
869 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
870 struct omap_req *req = container_of(_req, struct omap_req, req);
871 struct omap_udc *udc;
872 unsigned long flags;
873 int is_iso = 0;
874
875
876 if (!_req || !req->req.complete || !req->req.buf
877 || !list_empty(&req->queue)) {
878 DBG("%s, bad params\n", __func__);
879 return -EINVAL;
880 }
881 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
882 DBG("%s, bad ep\n", __func__);
883 return -EINVAL;
884 }
885 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
886 if (req->req.length > ep->ep.maxpacket)
887 return -EMSGSIZE;
888 is_iso = 1;
889 }
890
891
892
893
894 if (use_dma
895 && ep->has_dma
896 && ep->bEndpointAddress != 0
897 && (ep->bEndpointAddress & USB_DIR_IN) == 0
898 && (req->req.length % ep->ep.maxpacket) != 0) {
899 DBG("%s, no partial packet OUT reads\n", __func__);
900 return -EMSGSIZE;
901 }
902
903 udc = ep->udc;
904 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
905 return -ESHUTDOWN;
906
907 if (use_dma && ep->has_dma)
908 usb_gadget_map_request(&udc->gadget, &req->req,
909 (ep->bEndpointAddress & USB_DIR_IN));
910
911 VDBG("%s queue req %p, len %d buf %p\n",
912 ep->ep.name, _req, _req->length, _req->buf);
913
914 spin_lock_irqsave(&udc->lock, flags);
915
916 req->req.status = -EINPROGRESS;
917 req->req.actual = 0;
918
919
920 if (is_iso) {
921 u16 w;
922
923 w = omap_readw(UDC_IRQ_EN);
924 w |= UDC_SOF_IE;
925 omap_writew(w, UDC_IRQ_EN);
926 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
927 int is_in;
928
929 if (ep->bEndpointAddress == 0) {
930 if (!udc->ep0_pending || !list_empty(&ep->queue)) {
931 spin_unlock_irqrestore(&udc->lock, flags);
932 return -EL2HLT;
933 }
934
935
936 is_in = udc->ep0_in;
937 if (!req->req.length) {
938
939
940
941
942
943 if (udc->ep0_set_config) {
944 u16 irq_en = omap_readw(UDC_IRQ_EN);
945
946 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
947 if (!udc->ep0_reset_config)
948 irq_en |= UDC_EPN_RX_IE
949 | UDC_EPN_TX_IE;
950 omap_writew(irq_en, UDC_IRQ_EN);
951 }
952
953
954
955
956
957 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
958 UDC_EP_NUM);
959 omap_writew(UDC_CLR_EP, UDC_CTRL);
960 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
961 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
962
963
964 udc->ep0_pending = 0;
965 done(ep, req, 0);
966 req = NULL;
967
968
969 } else if (is_in) {
970 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
971 UDC_EP_NUM);
972 } else {
973 if (udc->ep0_setup)
974 goto irq_wait;
975 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
976 }
977 } else {
978 is_in = ep->bEndpointAddress & USB_DIR_IN;
979 if (!ep->has_dma)
980 use_ep(ep, UDC_EP_SEL);
981
982 }
983
984 if (ep->has_dma)
985 (is_in ? next_in_dma : next_out_dma)(ep, req);
986 else if (req) {
987 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
988 req = NULL;
989 deselect_ep();
990 if (!is_in) {
991 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
992 ep->ackwait = 1 + ep->double_buf;
993 }
994
995 }
996 }
997
998irq_wait:
999
1000 if (req != NULL)
1001 list_add_tail(&req->queue, &ep->queue);
1002 spin_unlock_irqrestore(&udc->lock, flags);
1003
1004 return 0;
1005}
1006
1007static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1008{
1009 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1010 struct omap_req *req;
1011 unsigned long flags;
1012
1013 if (!_ep || !_req)
1014 return -EINVAL;
1015
1016 spin_lock_irqsave(&ep->udc->lock, flags);
1017
1018
1019 list_for_each_entry(req, &ep->queue, queue) {
1020 if (&req->req == _req)
1021 break;
1022 }
1023 if (&req->req != _req) {
1024 spin_unlock_irqrestore(&ep->udc->lock, flags);
1025 return -EINVAL;
1026 }
1027
1028 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029 int channel = ep->dma_channel;
1030
1031
1032
1033
1034 dma_channel_release(ep);
1035 dma_channel_claim(ep, channel);
1036 } else
1037 done(ep, req, -ECONNRESET);
1038 spin_unlock_irqrestore(&ep->udc->lock, flags);
1039 return 0;
1040}
1041
1042
1043
1044static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045{
1046 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1047 unsigned long flags;
1048 int status = -EOPNOTSUPP;
1049
1050 spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052
1053 if (ep->bEndpointAddress == 0) {
1054 if (!ep->udc->ep0_pending)
1055 status = -EINVAL;
1056 else if (value) {
1057 if (ep->udc->ep0_set_config) {
1058 WARNING("error changing config?\n");
1059 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060 }
1061 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062 ep->udc->ep0_pending = 0;
1063 status = 0;
1064 } else
1065 status = 0;
1066
1067
1068 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070
1071 if ((ep->bEndpointAddress & USB_DIR_IN)
1072 && !list_empty(&ep->queue)) {
1073 status = -EAGAIN;
1074 goto done;
1075 }
1076
1077 if (value) {
1078 int channel;
1079
1080 if (use_dma && ep->dma_channel
1081 && !list_empty(&ep->queue)) {
1082 channel = ep->dma_channel;
1083 dma_channel_release(ep);
1084 } else
1085 channel = 0;
1086
1087 use_ep(ep, UDC_EP_SEL);
1088 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089 omap_writew(UDC_SET_HALT, UDC_CTRL);
1090 status = 0;
1091 } else
1092 status = -EAGAIN;
1093 deselect_ep();
1094
1095 if (channel)
1096 dma_channel_claim(ep, channel);
1097 } else {
1098 use_ep(ep, 0);
1099 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100 ep->ackwait = 0;
1101 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103 ep->ackwait = 1 + ep->double_buf;
1104 }
1105 }
1106 }
1107done:
1108 VDBG("%s %s halt stat %d\n", ep->ep.name,
1109 value ? "set" : "clear", status);
1110
1111 spin_unlock_irqrestore(&ep->udc->lock, flags);
1112 return status;
1113}
1114
1115static struct usb_ep_ops omap_ep_ops = {
1116 .enable = omap_ep_enable,
1117 .disable = omap_ep_disable,
1118
1119 .alloc_request = omap_alloc_request,
1120 .free_request = omap_free_request,
1121
1122 .queue = omap_ep_queue,
1123 .dequeue = omap_ep_dequeue,
1124
1125 .set_halt = omap_ep_set_halt,
1126
1127
1128};
1129
1130
1131
1132static int omap_get_frame(struct usb_gadget *gadget)
1133{
1134 u16 sof = omap_readw(UDC_SOF);
1135 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136}
1137
1138static int omap_wakeup(struct usb_gadget *gadget)
1139{
1140 struct omap_udc *udc;
1141 unsigned long flags;
1142 int retval = -EHOSTUNREACH;
1143
1144 udc = container_of(gadget, struct omap_udc, gadget);
1145
1146 spin_lock_irqsave(&udc->lock, flags);
1147 if (udc->devstat & UDC_SUS) {
1148
1149
1150
1151 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152 DBG("remote wakeup...\n");
1153 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154 retval = 0;
1155 }
1156
1157
1158 } else if (!(udc->devstat & UDC_ATT)) {
1159 if (!IS_ERR_OR_NULL(udc->transceiver))
1160 retval = otg_start_srp(udc->transceiver->otg);
1161 }
1162 spin_unlock_irqrestore(&udc->lock, flags);
1163
1164 return retval;
1165}
1166
1167static int
1168omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169{
1170 struct omap_udc *udc;
1171 unsigned long flags;
1172 u16 syscon1;
1173
1174 udc = container_of(gadget, struct omap_udc, gadget);
1175 spin_lock_irqsave(&udc->lock, flags);
1176 syscon1 = omap_readw(UDC_SYSCON1);
1177 if (is_selfpowered)
1178 syscon1 |= UDC_SELF_PWR;
1179 else
1180 syscon1 &= ~UDC_SELF_PWR;
1181 omap_writew(syscon1, UDC_SYSCON1);
1182 spin_unlock_irqrestore(&udc->lock, flags);
1183
1184 return 0;
1185}
1186
1187static int can_pullup(struct omap_udc *udc)
1188{
1189 return udc->driver && udc->softconnect && udc->vbus_active;
1190}
1191
1192static void pullup_enable(struct omap_udc *udc)
1193{
1194 u16 w;
1195
1196 w = omap_readw(UDC_SYSCON1);
1197 w |= UDC_PULLUP_EN;
1198 omap_writew(w, UDC_SYSCON1);
1199 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1200 u32 l;
1201
1202 l = omap_readl(OTG_CTRL);
1203 l |= OTG_BSESSVLD;
1204 omap_writel(l, OTG_CTRL);
1205 }
1206 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1207}
1208
1209static void pullup_disable(struct omap_udc *udc)
1210{
1211 u16 w;
1212
1213 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1214 u32 l;
1215
1216 l = omap_readl(OTG_CTRL);
1217 l &= ~OTG_BSESSVLD;
1218 omap_writel(l, OTG_CTRL);
1219 }
1220 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1221 w = omap_readw(UDC_SYSCON1);
1222 w &= ~UDC_PULLUP_EN;
1223 omap_writew(w, UDC_SYSCON1);
1224}
1225
1226static struct omap_udc *udc;
1227
1228static void omap_udc_enable_clock(int enable)
1229{
1230 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1231 return;
1232
1233 if (enable) {
1234 clk_enable(udc->dc_clk);
1235 clk_enable(udc->hhc_clk);
1236 udelay(100);
1237 } else {
1238 clk_disable(udc->hhc_clk);
1239 clk_disable(udc->dc_clk);
1240 }
1241}
1242
1243
1244
1245
1246
1247static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1248{
1249 struct omap_udc *udc;
1250 unsigned long flags;
1251 u32 l;
1252
1253 udc = container_of(gadget, struct omap_udc, gadget);
1254 spin_lock_irqsave(&udc->lock, flags);
1255 VDBG("VBUS %s\n", is_active ? "on" : "off");
1256 udc->vbus_active = (is_active != 0);
1257 if (cpu_is_omap15xx()) {
1258
1259 l = omap_readl(FUNC_MUX_CTRL_0);
1260 if (is_active)
1261 l |= VBUS_CTRL_1510;
1262 else
1263 l &= ~VBUS_CTRL_1510;
1264 omap_writel(l, FUNC_MUX_CTRL_0);
1265 }
1266 if (udc->dc_clk != NULL && is_active) {
1267 if (!udc->clk_requested) {
1268 omap_udc_enable_clock(1);
1269 udc->clk_requested = 1;
1270 }
1271 }
1272 if (can_pullup(udc))
1273 pullup_enable(udc);
1274 else
1275 pullup_disable(udc);
1276 if (udc->dc_clk != NULL && !is_active) {
1277 if (udc->clk_requested) {
1278 omap_udc_enable_clock(0);
1279 udc->clk_requested = 0;
1280 }
1281 }
1282 spin_unlock_irqrestore(&udc->lock, flags);
1283 return 0;
1284}
1285
1286static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1287{
1288 struct omap_udc *udc;
1289
1290 udc = container_of(gadget, struct omap_udc, gadget);
1291 if (!IS_ERR_OR_NULL(udc->transceiver))
1292 return usb_phy_set_power(udc->transceiver, mA);
1293 return -EOPNOTSUPP;
1294}
1295
1296static int omap_pullup(struct usb_gadget *gadget, int is_on)
1297{
1298 struct omap_udc *udc;
1299 unsigned long flags;
1300
1301 udc = container_of(gadget, struct omap_udc, gadget);
1302 spin_lock_irqsave(&udc->lock, flags);
1303 udc->softconnect = (is_on != 0);
1304 if (can_pullup(udc))
1305 pullup_enable(udc);
1306 else
1307 pullup_disable(udc);
1308 spin_unlock_irqrestore(&udc->lock, flags);
1309 return 0;
1310}
1311
1312static int omap_udc_start(struct usb_gadget *g,
1313 struct usb_gadget_driver *driver);
1314static int omap_udc_stop(struct usb_gadget *g,
1315 struct usb_gadget_driver *driver);
1316
1317static const struct usb_gadget_ops omap_gadget_ops = {
1318 .get_frame = omap_get_frame,
1319 .wakeup = omap_wakeup,
1320 .set_selfpowered = omap_set_selfpowered,
1321 .vbus_session = omap_vbus_session,
1322 .vbus_draw = omap_vbus_draw,
1323 .pullup = omap_pullup,
1324 .udc_start = omap_udc_start,
1325 .udc_stop = omap_udc_stop,
1326};
1327
1328
1329
1330
1331static void nuke(struct omap_ep *ep, int status)
1332{
1333 struct omap_req *req;
1334
1335 ep->stopped = 1;
1336
1337 if (use_dma && ep->dma_channel)
1338 dma_channel_release(ep);
1339
1340 use_ep(ep, 0);
1341 omap_writew(UDC_CLR_EP, UDC_CTRL);
1342 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1343 omap_writew(UDC_SET_HALT, UDC_CTRL);
1344
1345 while (!list_empty(&ep->queue)) {
1346 req = list_entry(ep->queue.next, struct omap_req, queue);
1347 done(ep, req, status);
1348 }
1349}
1350
1351
1352static void udc_quiesce(struct omap_udc *udc)
1353{
1354 struct omap_ep *ep;
1355
1356 udc->gadget.speed = USB_SPEED_UNKNOWN;
1357 nuke(&udc->ep[0], -ESHUTDOWN);
1358 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1359 nuke(ep, -ESHUTDOWN);
1360}
1361
1362
1363
1364static void update_otg(struct omap_udc *udc)
1365{
1366 u16 devstat;
1367
1368 if (!gadget_is_otg(&udc->gadget))
1369 return;
1370
1371 if (omap_readl(OTG_CTRL) & OTG_ID)
1372 devstat = omap_readw(UDC_DEVSTAT);
1373 else
1374 devstat = 0;
1375
1376 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1377 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1378 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1379
1380
1381
1382
1383 if (udc->gadget.b_hnp_enable) {
1384 u32 l;
1385
1386 l = omap_readl(OTG_CTRL);
1387 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1388 l &= ~OTG_PULLUP;
1389 omap_writel(l, OTG_CTRL);
1390 }
1391}
1392
1393static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1394{
1395 struct omap_ep *ep0 = &udc->ep[0];
1396 struct omap_req *req = NULL;
1397
1398 ep0->irqs++;
1399
1400
1401
1402
1403 if (irq_src & UDC_SETUP) {
1404 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1405
1406 nuke(ep0, 0);
1407 if (ack) {
1408 omap_writew(ack, UDC_IRQ_SRC);
1409 irq_src = UDC_SETUP;
1410 }
1411 }
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421 if (!list_empty(&ep0->queue))
1422 req = container_of(ep0->queue.next, struct omap_req, queue);
1423
1424
1425 if (irq_src & UDC_EP0_TX) {
1426 int stat;
1427
1428 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1429 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1430 stat = omap_readw(UDC_STAT_FLG);
1431 if (stat & UDC_ACK) {
1432 if (udc->ep0_in) {
1433
1434
1435
1436 if (req)
1437 stat = write_fifo(ep0, req);
1438 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1439 if (!req && udc->ep0_pending) {
1440 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1441 omap_writew(UDC_CLR_EP, UDC_CTRL);
1442 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1443 omap_writew(0, UDC_EP_NUM);
1444 udc->ep0_pending = 0;
1445 }
1446 } else {
1447
1448 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1449 if (req)
1450 done(ep0, req, 0);
1451 }
1452 req = NULL;
1453 } else if (stat & UDC_STALL) {
1454 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1455 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1456 } else {
1457 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1458 }
1459 }
1460
1461
1462 if (irq_src & UDC_EP0_RX) {
1463 int stat;
1464
1465 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1466 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467 stat = omap_readw(UDC_STAT_FLG);
1468 if (stat & UDC_ACK) {
1469 if (!udc->ep0_in) {
1470 stat = 0;
1471
1472
1473
1474 stat = read_fifo(ep0, req);
1475 if (!req || stat < 0) {
1476 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1477 udc->ep0_pending = 0;
1478 stat = 0;
1479 } else if (stat == 0)
1480 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1481 omap_writew(0, UDC_EP_NUM);
1482
1483
1484 if (stat == 1) {
1485 done(ep0, req, 0);
1486
1487 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1488 UDC_EP_NUM);
1489 omap_writew(UDC_CLR_EP, UDC_CTRL);
1490 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1491 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1492 udc->ep0_pending = 0;
1493 }
1494 } else {
1495
1496 omap_writew(0, UDC_EP_NUM);
1497 if (req)
1498 done(ep0, req, 0);
1499 }
1500 } else if (stat & UDC_STALL) {
1501 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1502 omap_writew(0, UDC_EP_NUM);
1503 } else {
1504 omap_writew(0, UDC_EP_NUM);
1505 }
1506 }
1507
1508
1509 if (irq_src & UDC_SETUP) {
1510 union u {
1511 u16 word[4];
1512 struct usb_ctrlrequest r;
1513 } u;
1514 int status = -EINVAL;
1515 struct omap_ep *ep;
1516
1517
1518 do {
1519 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1520
1521 u.word[0] = omap_readw(UDC_DATA);
1522 u.word[1] = omap_readw(UDC_DATA);
1523 u.word[2] = omap_readw(UDC_DATA);
1524 u.word[3] = omap_readw(UDC_DATA);
1525 omap_writew(0, UDC_EP_NUM);
1526 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1527
1528#define w_value le16_to_cpu(u.r.wValue)
1529#define w_index le16_to_cpu(u.r.wIndex)
1530#define w_length le16_to_cpu(u.r.wLength)
1531
1532
1533
1534
1535
1536 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1537 udc->ep0_set_config = 0;
1538 udc->ep0_pending = 1;
1539 ep0->stopped = 0;
1540 ep0->ackwait = 0;
1541 switch (u.r.bRequest) {
1542 case USB_REQ_SET_CONFIGURATION:
1543
1544 if (u.r.bRequestType != USB_RECIP_DEVICE)
1545 goto delegate;
1546 if (w_length != 0)
1547 goto do_stall;
1548 udc->ep0_set_config = 1;
1549 udc->ep0_reset_config = (w_value == 0);
1550 VDBG("set config %d\n", w_value);
1551
1552
1553
1554
1555
1556 if (udc->ep0_reset_config)
1557 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1558 else
1559 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1560 update_otg(udc);
1561 goto delegate;
1562 case USB_REQ_CLEAR_FEATURE:
1563
1564 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1565 goto delegate;
1566 if (w_value != USB_ENDPOINT_HALT
1567 || w_length != 0)
1568 goto do_stall;
1569 ep = &udc->ep[w_index & 0xf];
1570 if (ep != ep0) {
1571 if (w_index & USB_DIR_IN)
1572 ep += 16;
1573 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1574 || !ep->ep.desc)
1575 goto do_stall;
1576 use_ep(ep, 0);
1577 omap_writew(udc->clr_halt, UDC_CTRL);
1578 ep->ackwait = 0;
1579 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1580 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1581 ep->ackwait = 1 + ep->double_buf;
1582 }
1583
1584
1585
1586
1587
1588 }
1589 VDBG("%s halt cleared by host\n", ep->name);
1590 goto ep0out_status_stage;
1591 case USB_REQ_SET_FEATURE:
1592
1593 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594 goto delegate;
1595 if (w_value != USB_ENDPOINT_HALT
1596 || w_length != 0)
1597 goto do_stall;
1598 ep = &udc->ep[w_index & 0xf];
1599 if (w_index & USB_DIR_IN)
1600 ep += 16;
1601 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1602 || ep == ep0 || !ep->ep.desc)
1603 goto do_stall;
1604 if (use_dma && ep->has_dma) {
1605
1606
1607
1608 DBG("%s host set_halt, NYET\n", ep->name);
1609 goto do_stall;
1610 }
1611 use_ep(ep, 0);
1612
1613 omap_writew(UDC_CLR_EP, UDC_CTRL);
1614 omap_writew(UDC_SET_HALT, UDC_CTRL);
1615 VDBG("%s halted by host\n", ep->name);
1616ep0out_status_stage:
1617 status = 0;
1618 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1619 omap_writew(UDC_CLR_EP, UDC_CTRL);
1620 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1621 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1622 udc->ep0_pending = 0;
1623 break;
1624 case USB_REQ_GET_STATUS:
1625
1626 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1627 goto intf_status;
1628
1629
1630 if (!(w_index & 0xf))
1631 goto zero_status;
1632
1633
1634 ep = &udc->ep[w_index & 0xf];
1635 if (w_index & USB_DIR_IN)
1636 ep += 16;
1637 if (!ep->ep.desc)
1638 goto do_stall;
1639
1640
1641 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1642 goto zero_status;
1643
1644
1645 ERR("%s status, can't report\n", ep->ep.name);
1646 goto do_stall;
1647
1648intf_status:
1649
1650
1651
1652 if (u.r.bRequestType
1653 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1654 goto delegate;
1655
1656zero_status:
1657
1658 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1659 omap_writew(0, UDC_DATA);
1660 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1661 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1662 status = 0;
1663 VDBG("GET_STATUS, interface %d\n", w_index);
1664
1665 break;
1666 default:
1667delegate:
1668
1669 if (!udc->ep0_in && w_length) {
1670 omap_writew(0, UDC_EP_NUM);
1671 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1672 }
1673
1674
1675
1676
1677
1678 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1679 u.r.bRequestType, u.r.bRequest,
1680 w_value, w_index, w_length);
1681
1682#undef w_value
1683#undef w_index
1684#undef w_length
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697 udc->ep0_setup = 1;
1698 spin_unlock(&udc->lock);
1699 status = udc->driver->setup(&udc->gadget, &u.r);
1700 spin_lock(&udc->lock);
1701 udc->ep0_setup = 0;
1702 }
1703
1704 if (status < 0) {
1705do_stall:
1706 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1707 u.r.bRequestType, u.r.bRequest, status);
1708 if (udc->ep0_set_config) {
1709 if (udc->ep0_reset_config)
1710 WARNING("error resetting config?\n");
1711 else
1712 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1713 }
1714 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1715 udc->ep0_pending = 0;
1716 }
1717 }
1718}
1719
1720
1721
1722#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1723
1724static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1725{
1726 u16 devstat, change;
1727
1728 devstat = omap_readw(UDC_DEVSTAT);
1729 change = devstat ^ udc->devstat;
1730 udc->devstat = devstat;
1731
1732 if (change & (UDC_USB_RESET|UDC_ATT)) {
1733 udc_quiesce(udc);
1734
1735 if (change & UDC_ATT) {
1736
1737
1738
1739 if (devstat & UDC_ATT) {
1740 udc->gadget.speed = USB_SPEED_FULL;
1741 VDBG("connect\n");
1742 if (IS_ERR_OR_NULL(udc->transceiver))
1743 pullup_enable(udc);
1744
1745 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1746 udc->gadget.speed = USB_SPEED_UNKNOWN;
1747 if (IS_ERR_OR_NULL(udc->transceiver))
1748 pullup_disable(udc);
1749 DBG("disconnect, gadget %s\n",
1750 udc->driver->driver.name);
1751 if (udc->driver->disconnect) {
1752 spin_unlock(&udc->lock);
1753 udc->driver->disconnect(&udc->gadget);
1754 spin_lock(&udc->lock);
1755 }
1756 }
1757 change &= ~UDC_ATT;
1758 }
1759
1760 if (change & UDC_USB_RESET) {
1761 if (devstat & UDC_USB_RESET) {
1762 VDBG("RESET=1\n");
1763 } else {
1764 udc->gadget.speed = USB_SPEED_FULL;
1765 INFO("USB reset done, gadget %s\n",
1766 udc->driver->driver.name);
1767
1768 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1769 UDC_IRQ_EN);
1770 }
1771 change &= ~UDC_USB_RESET;
1772 }
1773 }
1774 if (change & UDC_SUS) {
1775 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1776
1777 if (devstat & UDC_SUS) {
1778 VDBG("suspend\n");
1779 update_otg(udc);
1780
1781 if (udc->gadget.speed == USB_SPEED_FULL
1782 && udc->driver->suspend) {
1783 spin_unlock(&udc->lock);
1784 udc->driver->suspend(&udc->gadget);
1785 spin_lock(&udc->lock);
1786 }
1787 if (!IS_ERR_OR_NULL(udc->transceiver))
1788 usb_phy_set_suspend(
1789 udc->transceiver, 1);
1790 } else {
1791 VDBG("resume\n");
1792 if (!IS_ERR_OR_NULL(udc->transceiver))
1793 usb_phy_set_suspend(
1794 udc->transceiver, 0);
1795 if (udc->gadget.speed == USB_SPEED_FULL
1796 && udc->driver->resume) {
1797 spin_unlock(&udc->lock);
1798 udc->driver->resume(&udc->gadget);
1799 spin_lock(&udc->lock);
1800 }
1801 }
1802 }
1803 change &= ~UDC_SUS;
1804 }
1805 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806 update_otg(udc);
1807 change &= ~OTG_FLAGS;
1808 }
1809
1810 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811 if (change)
1812 VDBG("devstat %03x, ignore change %03x\n",
1813 devstat, change);
1814
1815 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1816}
1817
1818static irqreturn_t omap_udc_irq(int irq, void *_udc)
1819{
1820 struct omap_udc *udc = _udc;
1821 u16 irq_src;
1822 irqreturn_t status = IRQ_NONE;
1823 unsigned long flags;
1824
1825 spin_lock_irqsave(&udc->lock, flags);
1826 irq_src = omap_readw(UDC_IRQ_SRC);
1827
1828
1829 if (irq_src & UDC_DS_CHG) {
1830 devstate_irq(_udc, irq_src);
1831 status = IRQ_HANDLED;
1832 irq_src &= ~UDC_DS_CHG;
1833 }
1834
1835
1836 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1837 ep0_irq(_udc, irq_src);
1838 status = IRQ_HANDLED;
1839 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1840 }
1841
1842
1843 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1844 dma_irq(_udc, irq_src);
1845 status = IRQ_HANDLED;
1846 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1847 }
1848
1849 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1850 if (irq_src)
1851 DBG("udc_irq, unhandled %03x\n", irq_src);
1852 spin_unlock_irqrestore(&udc->lock, flags);
1853
1854 return status;
1855}
1856
1857
1858#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1859#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1860
1861static void pio_out_timer(unsigned long _ep)
1862{
1863 struct omap_ep *ep = (void *) _ep;
1864 unsigned long flags;
1865 u16 stat_flg;
1866
1867 spin_lock_irqsave(&ep->udc->lock, flags);
1868 if (!list_empty(&ep->queue) && ep->ackwait) {
1869 use_ep(ep, UDC_EP_SEL);
1870 stat_flg = omap_readw(UDC_STAT_FLG);
1871
1872 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1873 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1874 struct omap_req *req;
1875
1876 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1877 req = container_of(ep->queue.next,
1878 struct omap_req, queue);
1879 (void) read_fifo(ep, req);
1880 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1881 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1882 ep->ackwait = 1 + ep->double_buf;
1883 } else
1884 deselect_ep();
1885 }
1886 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1887 spin_unlock_irqrestore(&ep->udc->lock, flags);
1888}
1889
1890static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1891{
1892 u16 epn_stat, irq_src;
1893 irqreturn_t status = IRQ_NONE;
1894 struct omap_ep *ep;
1895 int epnum;
1896 struct omap_udc *udc = _dev;
1897 struct omap_req *req;
1898 unsigned long flags;
1899
1900 spin_lock_irqsave(&udc->lock, flags);
1901 epn_stat = omap_readw(UDC_EPN_STAT);
1902 irq_src = omap_readw(UDC_IRQ_SRC);
1903
1904
1905 if (irq_src & UDC_EPN_RX) {
1906 epnum = (epn_stat >> 8) & 0x0f;
1907 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1908 status = IRQ_HANDLED;
1909 ep = &udc->ep[epnum];
1910 ep->irqs++;
1911
1912 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1913 ep->fnf = 0;
1914 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1915 ep->ackwait--;
1916 if (!list_empty(&ep->queue)) {
1917 int stat;
1918 req = container_of(ep->queue.next,
1919 struct omap_req, queue);
1920 stat = read_fifo(ep, req);
1921 if (!ep->double_buf)
1922 ep->fnf = 1;
1923 }
1924 }
1925
1926 epn_stat = omap_readw(UDC_EPN_STAT);
1927 epn_stat = omap_readw(UDC_EPN_STAT);
1928 omap_writew(epnum, UDC_EP_NUM);
1929
1930
1931
1932
1933 if (ep->fnf) {
1934 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935 ep->ackwait = 1 + ep->double_buf;
1936 }
1937 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1938 }
1939
1940
1941 else if (irq_src & UDC_EPN_TX) {
1942 epnum = epn_stat & 0x0f;
1943 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1944 status = IRQ_HANDLED;
1945 ep = &udc->ep[16 + epnum];
1946 ep->irqs++;
1947
1948 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1949 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1950 ep->ackwait = 0;
1951 if (!list_empty(&ep->queue)) {
1952 req = container_of(ep->queue.next,
1953 struct omap_req, queue);
1954 (void) write_fifo(ep, req);
1955 }
1956 }
1957
1958 epn_stat = omap_readw(UDC_EPN_STAT);
1959 epn_stat = omap_readw(UDC_EPN_STAT);
1960 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1961
1962 }
1963
1964 spin_unlock_irqrestore(&udc->lock, flags);
1965 return status;
1966}
1967
1968#ifdef USE_ISO
1969static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1970{
1971 struct omap_udc *udc = _dev;
1972 struct omap_ep *ep;
1973 int pending = 0;
1974 unsigned long flags;
1975
1976 spin_lock_irqsave(&udc->lock, flags);
1977
1978
1979 list_for_each_entry(ep, &udc->iso, iso) {
1980 u16 stat;
1981 struct omap_req *req;
1982
1983 if (ep->has_dma || list_empty(&ep->queue))
1984 continue;
1985 req = list_entry(ep->queue.next, struct omap_req, queue);
1986
1987 use_ep(ep, UDC_EP_SEL);
1988 stat = omap_readw(UDC_STAT_FLG);
1989
1990
1991
1992
1993 if (ep->bEndpointAddress & USB_DIR_IN) {
1994 if (stat & UDC_MISS_IN)
1995 ;
1996 else
1997 write_fifo(ep, req);
1998 } else {
1999 int status = 0;
2000
2001 if (stat & UDC_NO_RXPACKET)
2002 status = -EREMOTEIO;
2003 else if (stat & UDC_ISO_ERR)
2004 status = -EILSEQ;
2005 else if (stat & UDC_DATA_FLUSH)
2006 status = -ENOSR;
2007
2008 if (status)
2009 ;
2010 else
2011 read_fifo(ep, req);
2012 }
2013 deselect_ep();
2014
2015
2016 ep->irqs++;
2017 if (!list_empty(&ep->queue))
2018 pending = 1;
2019 }
2020 if (!pending) {
2021 u16 w;
2022
2023 w = omap_readw(UDC_IRQ_EN);
2024 w &= ~UDC_SOF_IE;
2025 omap_writew(w, UDC_IRQ_EN);
2026 }
2027 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2028
2029 spin_unlock_irqrestore(&udc->lock, flags);
2030 return IRQ_HANDLED;
2031}
2032#endif
2033
2034
2035
2036static inline int machine_without_vbus_sense(void)
2037{
2038 return machine_is_omap_innovator()
2039 || machine_is_omap_osk()
2040 || machine_is_sx1()
2041
2042 || cpu_is_omap7xx();
2043}
2044
2045static int omap_udc_start(struct usb_gadget *g,
2046 struct usb_gadget_driver *driver)
2047{
2048 int status = -ENODEV;
2049 struct omap_ep *ep;
2050 unsigned long flags;
2051
2052
2053 spin_lock_irqsave(&udc->lock, flags);
2054
2055 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2056 ep->irqs = 0;
2057 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2058 continue;
2059 use_ep(ep, 0);
2060 omap_writew(UDC_SET_HALT, UDC_CTRL);
2061 }
2062 udc->ep0_pending = 0;
2063 udc->ep[0].irqs = 0;
2064 udc->softconnect = 1;
2065
2066
2067 driver->driver.bus = NULL;
2068 udc->driver = driver;
2069 spin_unlock_irqrestore(&udc->lock, flags);
2070
2071 if (udc->dc_clk != NULL)
2072 omap_udc_enable_clock(1);
2073
2074 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2075
2076
2077 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2078 status = otg_set_peripheral(udc->transceiver->otg,
2079 &udc->gadget);
2080 if (status < 0) {
2081 ERR("can't bind to transceiver\n");
2082 if (driver->unbind) {
2083 driver->unbind(&udc->gadget);
2084 udc->driver = NULL;
2085 }
2086 goto done;
2087 }
2088 } else {
2089 if (can_pullup(udc))
2090 pullup_enable(udc);
2091 else
2092 pullup_disable(udc);
2093 }
2094
2095
2096
2097
2098 if (machine_without_vbus_sense())
2099 omap_vbus_session(&udc->gadget, 1);
2100
2101done:
2102 if (udc->dc_clk != NULL)
2103 omap_udc_enable_clock(0);
2104
2105 return status;
2106}
2107
2108static int omap_udc_stop(struct usb_gadget *g,
2109 struct usb_gadget_driver *driver)
2110{
2111 unsigned long flags;
2112 int status = -ENODEV;
2113
2114 if (udc->dc_clk != NULL)
2115 omap_udc_enable_clock(1);
2116
2117 if (machine_without_vbus_sense())
2118 omap_vbus_session(&udc->gadget, 0);
2119
2120 if (!IS_ERR_OR_NULL(udc->transceiver))
2121 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2122 else
2123 pullup_disable(udc);
2124
2125 spin_lock_irqsave(&udc->lock, flags);
2126 udc_quiesce(udc);
2127 spin_unlock_irqrestore(&udc->lock, flags);
2128
2129 udc->driver = NULL;
2130
2131 if (udc->dc_clk != NULL)
2132 omap_udc_enable_clock(0);
2133
2134 return status;
2135}
2136
2137
2138
2139#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2140
2141#include <linux/seq_file.h>
2142
2143static const char proc_filename[] = "driver/udc";
2144
2145#define FOURBITS "%s%s%s%s"
2146#define EIGHTBITS "%s%s%s%s%s%s%s%s"
2147
2148static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2149{
2150 u16 stat_flg;
2151 struct omap_req *req;
2152 char buf[20];
2153
2154 use_ep(ep, 0);
2155
2156 if (use_dma && ep->has_dma)
2157 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2158 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2159 ep->dma_channel - 1, ep->lch);
2160 else
2161 buf[0] = 0;
2162
2163 stat_flg = omap_readw(UDC_STAT_FLG);
2164 seq_printf(s,
2165 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2166 ep->name, buf,
2167 ep->double_buf ? "dbuf " : "",
2168 ({ char *s;
2169 switch (ep->ackwait) {
2170 case 0:
2171 s = "";
2172 break;
2173 case 1:
2174 s = "(ackw) ";
2175 break;
2176 case 2:
2177 s = "(ackw2) ";
2178 break;
2179 default:
2180 s = "(?) ";
2181 break;
2182 } s; }),
2183 ep->irqs, stat_flg,
2184 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2185 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2186 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2187 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2188 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2189 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2190 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2191 (stat_flg & UDC_STALL) ? "STALL " : "",
2192 (stat_flg & UDC_NAK) ? "NAK " : "",
2193 (stat_flg & UDC_ACK) ? "ACK " : "",
2194 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2195 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2196 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2197
2198 if (list_empty(&ep->queue))
2199 seq_printf(s, "\t(queue empty)\n");
2200 else
2201 list_for_each_entry(req, &ep->queue, queue) {
2202 unsigned length = req->req.actual;
2203
2204 if (use_dma && buf[0]) {
2205 length += ((ep->bEndpointAddress & USB_DIR_IN)
2206 ? dma_src_len : dma_dest_len)
2207 (ep, req->req.dma + length);
2208 buf[0] = 0;
2209 }
2210 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2211 &req->req, length,
2212 req->req.length, req->req.buf);
2213 }
2214}
2215
2216static char *trx_mode(unsigned m, int enabled)
2217{
2218 switch (m) {
2219 case 0:
2220 return enabled ? "*6wire" : "unused";
2221 case 1:
2222 return "4wire";
2223 case 2:
2224 return "3wire";
2225 case 3:
2226 return "6wire";
2227 default:
2228 return "unknown";
2229 }
2230}
2231
2232static int proc_otg_show(struct seq_file *s)
2233{
2234 u32 tmp;
2235 u32 trans = 0;
2236 char *ctrl_name = "(UNKNOWN)";
2237
2238 tmp = omap_readl(OTG_REV);
2239 ctrl_name = "tranceiver_ctrl";
2240 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2241 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2242 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2243 tmp = omap_readw(OTG_SYSCON_1);
2244 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2245 FOURBITS "\n", tmp,
2246 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2247 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2248 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2249 ? "internal"
2250 : trx_mode(USB0_TRX_MODE(tmp), 1),
2251 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2252 (tmp & HST_IDLE_EN) ? " !host" : "",
2253 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2254 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2255 tmp = omap_readl(OTG_SYSCON_2);
2256 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2257 " b_ase_brst=%d hmc=%d\n", tmp,
2258 (tmp & OTG_EN) ? " otg_en" : "",
2259 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2260
2261 (tmp & SRP_DATA) ? " srp_data" : "",
2262 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2263 (tmp & OTG_PADEN) ? " otg_paden" : "",
2264 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2265 (tmp & UHOST_EN) ? " uhost_en" : "",
2266 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2267 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2268 B_ASE_BRST(tmp),
2269 OTG_HMC(tmp));
2270 tmp = omap_readl(OTG_CTRL);
2271 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2272 (tmp & OTG_ASESSVLD) ? " asess" : "",
2273 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2274 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2275 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2276 (tmp & OTG_ID) ? " id" : "",
2277 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2278 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2279 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2280 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2281 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2282 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2283 (tmp & OTG_PULLDOWN) ? " down" : "",
2284 (tmp & OTG_PULLUP) ? " up" : "",
2285 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2286 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2287 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2288 (tmp & OTG_PU_ID) ? " pu_id" : ""
2289 );
2290 tmp = omap_readw(OTG_IRQ_EN);
2291 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2292 tmp = omap_readw(OTG_IRQ_SRC);
2293 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2294 tmp = omap_readw(OTG_OUTCTRL);
2295 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2296 tmp = omap_readw(OTG_TEST);
2297 seq_printf(s, "otg_test %04x" "\n", tmp);
2298 return 0;
2299}
2300
2301static int proc_udc_show(struct seq_file *s, void *_)
2302{
2303 u32 tmp;
2304 struct omap_ep *ep;
2305 unsigned long flags;
2306
2307 spin_lock_irqsave(&udc->lock, flags);
2308
2309 seq_printf(s, "%s, version: " DRIVER_VERSION
2310#ifdef USE_ISO
2311 " (iso)"
2312#endif
2313 "%s\n",
2314 driver_desc,
2315 use_dma ? " (dma)" : "");
2316
2317 tmp = omap_readw(UDC_REV) & 0xff;
2318 seq_printf(s,
2319 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2320 "hmc %d, transceiver %s\n",
2321 tmp >> 4, tmp & 0xf,
2322 fifo_mode,
2323 udc->driver ? udc->driver->driver.name : "(none)",
2324 HMC,
2325 udc->transceiver
2326 ? udc->transceiver->label
2327 : (cpu_is_omap1710()
2328 ? "external" : "(none)"));
2329 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2330 omap_readw(ULPD_CLOCK_CTRL),
2331 omap_readw(ULPD_SOFT_REQ),
2332 omap_readw(ULPD_STATUS_REQ));
2333
2334
2335 if (!cpu_is_omap15xx())
2336 proc_otg_show(s);
2337
2338 tmp = omap_readw(UDC_SYSCON1);
2339 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2340 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2341 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2342 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2343 (tmp & UDC_NAK_EN) ? " nak" : "",
2344 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2345 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2346 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2347 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2348
2349
2350
2351 if (!(tmp & UDC_PULLUP_EN)) {
2352 seq_printf(s, "(suspended)\n");
2353 spin_unlock_irqrestore(&udc->lock, flags);
2354 return 0;
2355 }
2356
2357 tmp = omap_readw(UDC_DEVSTAT);
2358 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2359 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2360 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2361 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2362 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2363 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2364 (tmp & UDC_SUS) ? " SUS" : "",
2365 (tmp & UDC_CFG) ? " CFG" : "",
2366 (tmp & UDC_ADD) ? " ADD" : "",
2367 (tmp & UDC_DEF) ? " DEF" : "",
2368 (tmp & UDC_ATT) ? " ATT" : "");
2369 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2370 tmp = omap_readw(UDC_IRQ_EN);
2371 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2372 (tmp & UDC_SOF_IE) ? " sof" : "",
2373 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2374 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2375 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2376 (tmp & UDC_EP0_IE) ? " ep0" : "");
2377 tmp = omap_readw(UDC_IRQ_SRC);
2378 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2379 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2380 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2381 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2382 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2383 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2384 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2385 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2386 (tmp & UDC_SETUP) ? " setup" : "",
2387 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2388 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2389 if (use_dma) {
2390 unsigned i;
2391
2392 tmp = omap_readw(UDC_DMA_IRQ_EN);
2393 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2394 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2395 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2396 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2397
2398 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2399 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2400 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2401
2402 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2403 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2404 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2405
2406 tmp = omap_readw(UDC_RXDMA_CFG);
2407 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2408 if (tmp) {
2409 for (i = 0; i < 3; i++) {
2410 if ((tmp & (0x0f << (i * 4))) == 0)
2411 continue;
2412 seq_printf(s, "rxdma[%d] %04x\n", i,
2413 omap_readw(UDC_RXDMA(i + 1)));
2414 }
2415 }
2416 tmp = omap_readw(UDC_TXDMA_CFG);
2417 seq_printf(s, "txdma_cfg %04x\n", tmp);
2418 if (tmp) {
2419 for (i = 0; i < 3; i++) {
2420 if (!(tmp & (0x0f << (i * 4))))
2421 continue;
2422 seq_printf(s, "txdma[%d] %04x\n", i,
2423 omap_readw(UDC_TXDMA(i + 1)));
2424 }
2425 }
2426 }
2427
2428 tmp = omap_readw(UDC_DEVSTAT);
2429 if (tmp & UDC_ATT) {
2430 proc_ep_show(s, &udc->ep[0]);
2431 if (tmp & UDC_ADD) {
2432 list_for_each_entry(ep, &udc->gadget.ep_list,
2433 ep.ep_list) {
2434 if (ep->ep.desc)
2435 proc_ep_show(s, ep);
2436 }
2437 }
2438 }
2439 spin_unlock_irqrestore(&udc->lock, flags);
2440 return 0;
2441}
2442
2443static int proc_udc_open(struct inode *inode, struct file *file)
2444{
2445 return single_open(file, proc_udc_show, NULL);
2446}
2447
2448static const struct file_operations proc_ops = {
2449 .owner = THIS_MODULE,
2450 .open = proc_udc_open,
2451 .read = seq_read,
2452 .llseek = seq_lseek,
2453 .release = single_release,
2454};
2455
2456static void create_proc_file(void)
2457{
2458 proc_create(proc_filename, 0, NULL, &proc_ops);
2459}
2460
2461static void remove_proc_file(void)
2462{
2463 remove_proc_entry(proc_filename, NULL);
2464}
2465
2466#else
2467
2468static inline void create_proc_file(void) {}
2469static inline void remove_proc_file(void) {}
2470
2471#endif
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483static unsigned
2484omap_ep_setup(char *name, u8 addr, u8 type,
2485 unsigned buf, unsigned maxp, int dbuf)
2486{
2487 struct omap_ep *ep;
2488 u16 epn_rxtx = 0;
2489
2490
2491 ep = &udc->ep[addr & 0xf];
2492 if (addr & USB_DIR_IN)
2493 ep += 16;
2494
2495
2496 BUG_ON(ep->name[0]);
2497
2498
2499 if (type == USB_ENDPOINT_XFER_ISOC) {
2500 switch (maxp) {
2501 case 8:
2502 epn_rxtx = 0 << 12;
2503 break;
2504 case 16:
2505 epn_rxtx = 1 << 12;
2506 break;
2507 case 32:
2508 epn_rxtx = 2 << 12;
2509 break;
2510 case 64:
2511 epn_rxtx = 3 << 12;
2512 break;
2513 case 128:
2514 epn_rxtx = 4 << 12;
2515 break;
2516 case 256:
2517 epn_rxtx = 5 << 12;
2518 break;
2519 case 512:
2520 epn_rxtx = 6 << 12;
2521 break;
2522 default:
2523 BUG();
2524 }
2525 epn_rxtx |= UDC_EPN_RX_ISO;
2526 dbuf = 1;
2527 } else {
2528
2529
2530
2531
2532 if (!use_dma || cpu_is_omap15xx())
2533 dbuf = 0;
2534
2535 switch (maxp) {
2536 case 8:
2537 epn_rxtx = 0 << 12;
2538 break;
2539 case 16:
2540 epn_rxtx = 1 << 12;
2541 break;
2542 case 32:
2543 epn_rxtx = 2 << 12;
2544 break;
2545 case 64:
2546 epn_rxtx = 3 << 12;
2547 break;
2548 default:
2549 BUG();
2550 }
2551 if (dbuf && addr)
2552 epn_rxtx |= UDC_EPN_RX_DB;
2553 init_timer(&ep->timer);
2554 ep->timer.function = pio_out_timer;
2555 ep->timer.data = (unsigned long) ep;
2556 }
2557 if (addr)
2558 epn_rxtx |= UDC_EPN_RX_VALID;
2559 BUG_ON(buf & 0x07);
2560 epn_rxtx |= buf >> 3;
2561
2562 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2563 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2564
2565 if (addr & USB_DIR_IN)
2566 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2567 else
2568 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2569
2570
2571 buf += maxp;
2572 if (dbuf)
2573 buf += maxp;
2574 BUG_ON(buf > 2048);
2575
2576
2577 BUG_ON(strlen(name) >= sizeof ep->name);
2578 strlcpy(ep->name, name, sizeof ep->name);
2579 INIT_LIST_HEAD(&ep->queue);
2580 INIT_LIST_HEAD(&ep->iso);
2581 ep->bEndpointAddress = addr;
2582 ep->bmAttributes = type;
2583 ep->double_buf = dbuf;
2584 ep->udc = udc;
2585
2586 ep->ep.name = ep->name;
2587 ep->ep.ops = &omap_ep_ops;
2588 ep->ep.maxpacket = ep->maxpacket = maxp;
2589 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2590
2591 return buf;
2592}
2593
2594static void omap_udc_release(struct device *dev)
2595{
2596 complete(udc->done);
2597 kfree(udc);
2598 udc = NULL;
2599}
2600
2601static int
2602omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2603{
2604 unsigned tmp, buf;
2605
2606
2607 omap_writew(0, UDC_SYSCON1);
2608 omap_writew(0, UDC_IRQ_EN);
2609 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2610 omap_writew(0, UDC_DMA_IRQ_EN);
2611 omap_writew(0, UDC_RXDMA_CFG);
2612 omap_writew(0, UDC_TXDMA_CFG);
2613
2614
2615
2616
2617 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2618 if (!udc)
2619 return -ENOMEM;
2620
2621 spin_lock_init(&udc->lock);
2622
2623 udc->gadget.ops = &omap_gadget_ops;
2624 udc->gadget.ep0 = &udc->ep[0].ep;
2625 INIT_LIST_HEAD(&udc->gadget.ep_list);
2626 INIT_LIST_HEAD(&udc->iso);
2627 udc->gadget.speed = USB_SPEED_UNKNOWN;
2628 udc->gadget.max_speed = USB_SPEED_FULL;
2629 udc->gadget.name = driver_name;
2630 udc->transceiver = xceiv;
2631
2632
2633 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2634 8 , 64 , 0);
2635 list_del_init(&udc->ep[0].ep.ep_list);
2636
2637
2638 for (tmp = 1; tmp < 15; tmp++) {
2639 omap_writew(0, UDC_EP_RX(tmp));
2640 omap_writew(0, UDC_EP_TX(tmp));
2641 }
2642
2643#define OMAP_BULK_EP(name, addr) \
2644 buf = omap_ep_setup(name "-bulk", addr, \
2645 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2646#define OMAP_INT_EP(name, addr, maxp) \
2647 buf = omap_ep_setup(name "-int", addr, \
2648 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2649#define OMAP_ISO_EP(name, addr, maxp) \
2650 buf = omap_ep_setup(name "-iso", addr, \
2651 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2652
2653 switch (fifo_mode) {
2654 case 0:
2655 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2656 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2657 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2658 break;
2659 case 1:
2660 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2661 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2662 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2663
2664 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2665 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2666 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2667
2668 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2669 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2670 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2671
2672 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2673 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2674 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2675
2676 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2677 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2678 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2679 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2680
2681 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2682 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2683 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2684 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2685
2686 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2687 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2688
2689 break;
2690
2691#ifdef USE_ISO
2692 case 2:
2693 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2694 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2695 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2696 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2697
2698 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2699
2700 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2701 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2702 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2703 break;
2704 case 3:
2705 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2706 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2707 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2708
2709 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2710 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2711 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2712
2713 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2714 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2715 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2716 break;
2717#endif
2718
2719
2720
2721 default:
2722 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2723 return -ENODEV;
2724 }
2725 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2726 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2727 return 0;
2728}
2729
2730static int omap_udc_probe(struct platform_device *pdev)
2731{
2732 int status = -ENODEV;
2733 int hmc;
2734 struct usb_phy *xceiv = NULL;
2735 const char *type = NULL;
2736 struct omap_usb_config *config = pdev->dev.platform_data;
2737 struct clk *dc_clk = NULL;
2738 struct clk *hhc_clk = NULL;
2739
2740 if (cpu_is_omap7xx())
2741 use_dma = 0;
2742
2743
2744 if (!request_mem_region(pdev->resource[0].start,
2745 pdev->resource[0].end - pdev->resource[0].start + 1,
2746 driver_name)) {
2747 DBG("request_mem_region failed\n");
2748 return -EBUSY;
2749 }
2750
2751 if (cpu_is_omap16xx()) {
2752 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2753 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2754 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2755
2756 clk_enable(dc_clk);
2757 clk_enable(hhc_clk);
2758 udelay(100);
2759 }
2760
2761 if (cpu_is_omap7xx()) {
2762 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2763 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2764 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2765
2766 clk_enable(dc_clk);
2767 clk_enable(hhc_clk);
2768 udelay(100);
2769 }
2770
2771 INFO("OMAP UDC rev %d.%d%s\n",
2772 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2773 config->otg ? ", Mini-AB" : "");
2774
2775
2776 if (cpu_is_omap15xx()) {
2777 hmc = HMC_1510;
2778 type = "(unknown)";
2779
2780 if (machine_without_vbus_sense()) {
2781
2782
2783
2784
2785
2786
2787 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2788 tmp &= ~VBUS_CTRL_1510;
2789 omap_writel(tmp, FUNC_MUX_CTRL_0);
2790 tmp |= VBUS_MODE_1510;
2791 tmp &= ~VBUS_CTRL_1510;
2792 omap_writel(tmp, FUNC_MUX_CTRL_0);
2793 }
2794 } else {
2795
2796
2797
2798
2799
2800 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2801 if (!IS_ERR_OR_NULL(xceiv))
2802 type = xceiv->label;
2803 else if (config->otg) {
2804 DBG("OTG requires external transceiver!\n");
2805 goto cleanup0;
2806 }
2807
2808 hmc = HMC_1610;
2809
2810 switch (hmc) {
2811 case 0:
2812 case 4:
2813 case 12:
2814 case 20:
2815 if (!cpu_is_omap1710()) {
2816 type = "integrated";
2817 break;
2818 }
2819
2820 case 3:
2821 case 11:
2822 case 16:
2823 case 19:
2824 case 25:
2825 if (IS_ERR_OR_NULL(xceiv)) {
2826 DBG("external transceiver not registered!\n");
2827 type = "unknown";
2828 }
2829 break;
2830 case 21:
2831 type = "loopback";
2832 break;
2833 case 14:
2834 if (cpu_is_omap1710())
2835 goto bad_on_1710;
2836
2837 case 13:
2838 case 15:
2839 type = "no";
2840 break;
2841
2842 default:
2843bad_on_1710:
2844 ERR("unrecognized UDC HMC mode %d\n", hmc);
2845 goto cleanup0;
2846 }
2847 }
2848
2849 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2850
2851
2852 status = omap_udc_setup(pdev, xceiv);
2853 if (status)
2854 goto cleanup0;
2855
2856 xceiv = NULL;
2857
2858 pullup_disable(udc);
2859#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2860 udc->gadget.is_otg = (config->otg != 0);
2861#endif
2862
2863
2864 if (omap_readw(UDC_REV) >= 0x61)
2865 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2866 else
2867 udc->clr_halt = UDC_RESET_EP;
2868
2869
2870 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2871 0, driver_name, udc);
2872 if (status != 0) {
2873 ERR("can't get irq %d, err %d\n",
2874 (int) pdev->resource[1].start, status);
2875 goto cleanup1;
2876 }
2877
2878
2879 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2880 0, "omap_udc pio", udc);
2881 if (status != 0) {
2882 ERR("can't get irq %d, err %d\n",
2883 (int) pdev->resource[2].start, status);
2884 goto cleanup2;
2885 }
2886#ifdef USE_ISO
2887 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2888 0, "omap_udc iso", udc);
2889 if (status != 0) {
2890 ERR("can't get irq %d, err %d\n",
2891 (int) pdev->resource[3].start, status);
2892 goto cleanup3;
2893 }
2894#endif
2895 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2896 udc->dc_clk = dc_clk;
2897 udc->hhc_clk = hhc_clk;
2898 clk_disable(hhc_clk);
2899 clk_disable(dc_clk);
2900 }
2901
2902 create_proc_file();
2903 status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2904 omap_udc_release);
2905 if (status)
2906 goto cleanup4;
2907
2908 return 0;
2909
2910cleanup4:
2911 remove_proc_file();
2912
2913#ifdef USE_ISO
2914cleanup3:
2915 free_irq(pdev->resource[2].start, udc);
2916#endif
2917
2918cleanup2:
2919 free_irq(pdev->resource[1].start, udc);
2920
2921cleanup1:
2922 kfree(udc);
2923 udc = NULL;
2924
2925cleanup0:
2926 if (!IS_ERR_OR_NULL(xceiv))
2927 usb_put_phy(xceiv);
2928
2929 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2930 clk_disable(hhc_clk);
2931 clk_disable(dc_clk);
2932 clk_put(hhc_clk);
2933 clk_put(dc_clk);
2934 }
2935
2936 release_mem_region(pdev->resource[0].start,
2937 pdev->resource[0].end - pdev->resource[0].start + 1);
2938
2939 return status;
2940}
2941
2942static int omap_udc_remove(struct platform_device *pdev)
2943{
2944 DECLARE_COMPLETION_ONSTACK(done);
2945
2946 if (!udc)
2947 return -ENODEV;
2948
2949 usb_del_gadget_udc(&udc->gadget);
2950 if (udc->driver)
2951 return -EBUSY;
2952
2953 udc->done = &done;
2954
2955 pullup_disable(udc);
2956 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2957 usb_put_phy(udc->transceiver);
2958 udc->transceiver = NULL;
2959 }
2960 omap_writew(0, UDC_SYSCON1);
2961
2962 remove_proc_file();
2963
2964#ifdef USE_ISO
2965 free_irq(pdev->resource[3].start, udc);
2966#endif
2967 free_irq(pdev->resource[2].start, udc);
2968 free_irq(pdev->resource[1].start, udc);
2969
2970 if (udc->dc_clk) {
2971 if (udc->clk_requested)
2972 omap_udc_enable_clock(0);
2973 clk_put(udc->hhc_clk);
2974 clk_put(udc->dc_clk);
2975 }
2976
2977 release_mem_region(pdev->resource[0].start,
2978 pdev->resource[0].end - pdev->resource[0].start + 1);
2979
2980 wait_for_completion(&done);
2981
2982 return 0;
2983}
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2996{
2997 u32 devstat;
2998
2999 devstat = omap_readw(UDC_DEVSTAT);
3000
3001
3002
3003
3004
3005 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3006 WARNING("session active; suspend requires disconnect\n");
3007 omap_pullup(&udc->gadget, 0);
3008 }
3009
3010 return 0;
3011}
3012
3013static int omap_udc_resume(struct platform_device *dev)
3014{
3015 DBG("resume + wakeup/SRP\n");
3016 omap_pullup(&udc->gadget, 1);
3017
3018
3019 msleep(100);
3020 return omap_wakeup(&udc->gadget);
3021}
3022
3023
3024
3025static struct platform_driver udc_driver = {
3026 .probe = omap_udc_probe,
3027 .remove = omap_udc_remove,
3028 .suspend = omap_udc_suspend,
3029 .resume = omap_udc_resume,
3030 .driver = {
3031 .owner = THIS_MODULE,
3032 .name = (char *) driver_name,
3033 },
3034};
3035
3036module_platform_driver(udc_driver);
3037
3038MODULE_DESCRIPTION(DRIVER_DESC);
3039MODULE_LICENSE("GPL");
3040MODULE_ALIAS("platform:omap_udc");
3041