1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20#ifndef __LINUX_KVM_POWERPC_H 21#define __LINUX_KVM_POWERPC_H 22 23#include <linux/types.h> 24 25/* Select powerpc specific features in <linux/kvm.h> */ 26#define __KVM_HAVE_SPAPR_TCE 27#define __KVM_HAVE_PPC_SMT 28#define __KVM_HAVE_IRQCHIP 29#define __KVM_HAVE_IRQ_LINE 30 31struct kvm_regs { 32 __u64 pc; 33 __u64 cr; 34 __u64 ctr; 35 __u64 lr; 36 __u64 xer; 37 __u64 msr; 38 __u64 srr0; 39 __u64 srr1; 40 __u64 pid; 41 42 __u64 sprg0; 43 __u64 sprg1; 44 __u64 sprg2; 45 __u64 sprg3; 46 __u64 sprg4; 47 __u64 sprg5; 48 __u64 sprg6; 49 __u64 sprg7; 50 51 __u64 gpr[32]; 52}; 53 54#define KVM_SREGS_E_IMPL_NONE 0 55#define KVM_SREGS_E_IMPL_FSL 1 56 57#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ 58 59/* 60 * Feature bits indicate which sections of the sregs struct are valid, 61 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers 62 * corresponding to unset feature bits will not be modified. This allows 63 * restoring a checkpoint made without that feature, while keeping the 64 * default values of the new registers. 65 * 66 * KVM_SREGS_E_BASE contains: 67 * CSRR0/1 (refers to SRR2/3 on 40x) 68 * ESR 69 * DEAR 70 * MCSR 71 * TSR 72 * TCR 73 * DEC 74 * TB 75 * VRSAVE (USPRG0) 76 */ 77#define KVM_SREGS_E_BASE (1 << 0) 78 79/* 80 * KVM_SREGS_E_ARCH206 contains: 81 * 82 * PIR 83 * MCSRR0/1 84 * DECAR 85 * IVPR 86 */ 87#define KVM_SREGS_E_ARCH206 (1 << 1) 88 89/* 90 * Contains EPCR, plus the upper half of 64-bit registers 91 * that are 32-bit on 32-bit implementations. 92 */ 93#define KVM_SREGS_E_64 (1 << 2) 94 95#define KVM_SREGS_E_SPRG8 (1 << 3) 96#define KVM_SREGS_E_MCIVPR (1 << 4) 97 98/* 99 * IVORs are used -- contains IVOR0-15, plus additional IVORs 100 * in combination with an appropriate feature bit. 101 */ 102#define KVM_SREGS_E_IVOR (1 << 5) 103 104/* 105 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. 106 * Also TLBnPS if MMUCFG[MAVN] = 1. 107 */ 108#define KVM_SREGS_E_ARCH206_MMU (1 << 6) 109 110/* DBSR, DBCR, IAC, DAC, DVC */ 111#define KVM_SREGS_E_DEBUG (1 << 7) 112 113/* Enhanced debug -- DSRR0/1, SPRG9 */ 114#define KVM_SREGS_E_ED (1 << 8) 115 116/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ 117#define KVM_SREGS_E_SPE (1 << 9) 118 119/* 120 * DEPRECATED! USE ONE_REG FOR THIS ONE! 121 * External Proxy (EXP) -- EPR 122 */ 123#define KVM_SREGS_EXP (1 << 10) 124 125/* External PID (E.PD) -- EPSC/EPLC */ 126#define KVM_SREGS_E_PD (1 << 11) 127 128/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ 129#define KVM_SREGS_E_PC (1 << 12) 130 131/* Page table (E.PT) -- EPTCFG */ 132#define KVM_SREGS_E_PT (1 << 13) 133 134/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ 135#define KVM_SREGS_E_PM (1 << 14) 136 137/* 138 * Special updates: 139 * 140 * Some registers may change even while a vcpu is not running. 141 * To avoid losing these changes, by default these registers are 142 * not updated by KVM_SET_SREGS. To force an update, set the bit 143 * in u.e.update_special corresponding to the register to be updated. 144 * 145 * The update_special field is zero on return from KVM_GET_SREGS. 146 * 147 * When restoring a checkpoint, the caller can set update_special 148 * to 0xffffffff to ensure that everything is restored, even new features 149 * that the caller doesn't know about. 150 */ 151#define KVM_SREGS_E_UPDATE_MCSR (1 << 0) 152#define KVM_SREGS_E_UPDATE_TSR (1 << 1) 153#define KVM_SREGS_E_UPDATE_DEC (1 << 2) 154#define KVM_SREGS_E_UPDATE_DBSR (1 << 3) 155 156/* 157 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a 158 * previous KVM_GET_REGS. 159 * 160 * Unless otherwise indicated, setting any register with KVM_SET_SREGS 161 * directly sets its value. It does not trigger any special semantics such 162 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct 163 * just received from KVM_GET_SREGS is always a no-op. 164 */ 165struct kvm_sregs { 166 __u32 pvr; 167 union { 168 struct { 169 __u64 sdr1; 170 struct { 171 struct { 172 __u64 slbe; 173 __u64 slbv; 174 } slb[64]; 175 } ppc64; 176 struct { 177 __u32 sr[16]; 178 __u64 ibat[8]; 179 __u64 dbat[8]; 180 } ppc32; 181 } s; 182 struct { 183 union { 184 struct { /* KVM_SREGS_E_IMPL_FSL */ 185 __u32 features; /* KVM_SREGS_E_FSL_ */ 186 __u32 svr; 187 __u64 mcar; 188 __u32 hid0; 189 190 /* KVM_SREGS_E_FSL_PIDn */ 191 __u32 pid1, pid2; 192 } fsl; 193 __u8 pad[256]; 194 } impl; 195 196 __u32 features; /* KVM_SREGS_E_ */ 197 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */ 198 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */ 199 __u32 pir; /* read-only */ 200 __u64 sprg8; 201 __u64 sprg9; /* E.ED */ 202 __u64 csrr0; 203 __u64 dsrr0; /* E.ED */ 204 __u64 mcsrr0; 205 __u32 csrr1; 206 __u32 dsrr1; /* E.ED */ 207 __u32 mcsrr1; 208 __u32 esr; 209 __u64 dear; 210 __u64 ivpr; 211 __u64 mcivpr; 212 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ 213 214 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ 215 __u32 tcr; 216 __u32 decar; 217 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ 218 219 /* 220 * Userspace can read TB directly, but the 221 * value reported here is consistent with "dec". 222 * 223 * Read-only. 224 */ 225 __u64 tb; 226 227 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ 228 __u32 dbcr[3]; 229 /* 230 * iac/dac registers are 64bit wide, while this API 231 * interface provides only lower 32 bits on 64 bit 232 * processors. ONE_REG interface is added for 64bit 233 * iac/dac registers. 234 */ 235 __u32 iac[4]; 236 __u32 dac[2]; 237 __u32 dvc[2]; 238 __u8 num_iac; /* read-only */ 239 __u8 num_dac; /* read-only */ 240 __u8 num_dvc; /* read-only */ 241 __u8 pad; 242 243 __u32 epr; /* EXP */ 244 __u32 vrsave; /* a.k.a. USPRG0 */ 245 __u32 epcr; /* KVM_SREGS_E_64 */ 246 247 __u32 mas0; 248 __u32 mas1; 249 __u64 mas2; 250 __u64 mas7_3; 251 __u32 mas4; 252 __u32 mas6; 253 254 __u32 ivor_low[16]; /* IVOR0-15 */ 255 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */ 256 257 __u32 mmucfg; /* read-only */ 258 __u32 eptcfg; /* E.PT, read-only */ 259 __u32 tlbcfg[4];/* read-only */ 260 __u32 tlbps[4]; /* read-only */ 261 262 __u32 eplc, epsc; /* E.PD */ 263 } e; 264 __u8 pad[1020]; 265 } u; 266}; 267 268struct kvm_fpu { 269 __u64 fpr[32]; 270}; 271 272/* 273 * Defines for h/w breakpoint, watchpoint (read, write or both) and 274 * software breakpoint. 275 * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status" 276 * for KVM_DEBUG_EXIT. 277 */ 278#define KVMPPC_DEBUG_NONE 0x0 279#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1) 280#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2) 281#define KVMPPC_DEBUG_WATCH_READ (1UL << 3) 282struct kvm_debug_exit_arch { 283 __u64 address; 284 /* 285 * exiting to userspace because of h/w breakpoint, watchpoint 286 * (read, write or both) and software breakpoint. 287 */ 288 __u32 status; 289 __u32 reserved; 290}; 291 292/* for KVM_SET_GUEST_DEBUG */ 293struct kvm_guest_debug_arch { 294 struct { 295 /* H/W breakpoint/watchpoint address */ 296 __u64 addr; 297 /* 298 * Type denotes h/w breakpoint, read watchpoint, write 299 * watchpoint or watchpoint (both read and write). 300 */ 301 __u32 type; 302 __u32 reserved; 303 } bp[16]; 304}; 305 306/* Debug related defines */ 307/* 308 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic 309 * and upper 16 bits are architecture specific. Architecture specific defines 310 * that ioctl is for setting hardware breakpoint or software breakpoint. 311 */ 312#define KVM_GUESTDBG_USE_SW_BP 0x00010000 313#define KVM_GUESTDBG_USE_HW_BP 0x00020000 314 315/* definition of registers in kvm_run */ 316struct kvm_sync_regs { 317}; 318 319#define KVM_INTERRUPT_SET -1U 320#define KVM_INTERRUPT_UNSET -2U 321#define KVM_INTERRUPT_SET_LEVEL -3U 322 323#define KVM_CPU_440 1 324#define KVM_CPU_E500V2 2 325#define KVM_CPU_3S_32 3 326#define KVM_CPU_3S_64 4 327#define KVM_CPU_E500MC 5 328 329/* for KVM_CAP_SPAPR_TCE */ 330struct kvm_create_spapr_tce { 331 __u64 liobn; 332 __u32 window_size; 333}; 334 335/* for KVM_ALLOCATE_RMA */ 336struct kvm_allocate_rma { 337 __u64 rma_size; 338}; 339 340/* for KVM_CAP_PPC_RTAS */ 341struct kvm_rtas_token_args { 342 char name[120]; 343 __u64 token; /* Use a token of 0 to undefine a mapping */ 344}; 345 346struct kvm_book3e_206_tlb_entry { 347 __u32 mas8; 348 __u32 mas1; 349 __u64 mas2; 350 __u64 mas7_3; 351}; 352 353struct kvm_book3e_206_tlb_params { 354 /* 355 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: 356 * 357 * - The number of ways of TLB0 must be a power of two between 2 and 358 * 16. 359 * - TLB1 must be fully associative. 360 * - The size of TLB0 must be a multiple of the number of ways, and 361 * the number of sets must be a power of two. 362 * - The size of TLB1 may not exceed 64 entries. 363 * - TLB0 supports 4 KiB pages. 364 * - The page sizes supported by TLB1 are as indicated by 365 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) 366 * as returned by KVM_GET_SREGS. 367 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] 368 * and tlb_ways[] must be zero. 369 * 370 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative. 371 * 372 * KVM will adjust TLBnCFG based on the sizes configured here, 373 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY] 374 * set to zero. 375 */ 376 __u32 tlb_sizes[4]; 377 __u32 tlb_ways[4]; 378 __u32 reserved[8]; 379}; 380 381/* For KVM_PPC_GET_HTAB_FD */ 382struct kvm_get_htab_fd { 383 __u64 flags; 384 __u64 start_index; 385 __u64 reserved[2]; 386}; 387 388/* Values for kvm_get_htab_fd.flags */ 389#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) 390#define KVM_GET_HTAB_WRITE ((__u64)0x2) 391 392/* 393 * Data read on the file descriptor is formatted as a series of 394 * records, each consisting of a header followed by a series of 395 * `n_valid' HPTEs (16 bytes each), which are all valid. Following 396 * those valid HPTEs there are `n_invalid' invalid HPTEs, which 397 * are not represented explicitly in the stream. The same format 398 * is used for writing. 399 */ 400struct kvm_get_htab_header { 401 __u32 index; 402 __u16 n_valid; 403 __u16 n_invalid; 404}; 405 406/* Per-vcpu XICS interrupt controller state */ 407#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c) 408 409#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */ 410#define KVM_REG_PPC_ICP_CPPR_MASK 0xff 411#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */ 412#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff 413#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */ 414#define KVM_REG_PPC_ICP_MFRR_MASK 0xff 415#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */ 416#define KVM_REG_PPC_ICP_PPRI_MASK 0xff 417 418/* Device control API: PPC-specific devices */ 419#define KVM_DEV_MPIC_GRP_MISC 1 420#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */ 421 422#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */ 423#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */ 424 425/* One-Reg API: PPC-specific registers */ 426#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) 427#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) 428#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) 429#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) 430#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) 431#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) 432#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) 433#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) 434#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) 435#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) 436#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) 437#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) 438#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) 439#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) 440#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) 441 442#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) 443#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) 444#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) 445#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13) 446#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14) 447#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15) 448#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16) 449#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17) 450 451#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) 452#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) 453#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) 454#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) 455#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) 456#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) 457#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) 458#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) 459 460/* 32 floating-point registers */ 461#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) 462#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) 463#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) 464 465/* 32 VMX/Altivec vector registers */ 466#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) 467#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) 468#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) 469 470/* 32 double-width FP registers for VSX */ 471/* High-order halves overlap with FP regs */ 472#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) 473#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) 474#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) 475 476/* FP and vector status/control registers */ 477#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) 478#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) 479 480/* Virtual processor areas */ 481/* For SLB & DTL, address in high (first) half, length in low half */ 482#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) 483#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) 484#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) 485 486#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) 487#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86) 488 489/* Timer Status Register OR/CLEAR interface */ 490#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87) 491#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88) 492#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89) 493#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a) 494 495/* Debugging: Special instruction for software breakpoint */ 496#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b) 497 498/* MMU registers */ 499#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c) 500#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d) 501#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e) 502#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f) 503#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90) 504#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91) 505#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92) 506/* 507 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using 508 * KVM_CAP_SW_TLB ioctl 509 */ 510#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93) 511#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94) 512#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95) 513#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96) 514#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97) 515#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98) 516#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99) 517#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a) 518#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b) 519 520/* Timebase offset */ 521#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c) 522 523/* POWER8 registers */ 524#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d) 525#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e) 526#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f) 527#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0) 528#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1) 529#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2) 530#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3) 531#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4) 532#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5) 533#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6) 534#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7) 535#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8) 536#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9) 537#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa) 538#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab) 539#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac) 540#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad) 541#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae) 542#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf) 543#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0) 544#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1) 545#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2) 546#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3) 547 548#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4) 549#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5) 550#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5) 551#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6) 552 553/* Architecture compatibility level */ 554#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7) 555 556#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8) 557#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9) 558 559/* Transactional Memory checkpointed state: 560 * This is all GPRs, all VSX regs and a subset of SPRs 561 */ 562#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000) 563/* TM GPRs */ 564#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0) 565#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n)) 566#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f) 567/* TM VSX */ 568#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20) 569#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n)) 570#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f) 571/* TM SPRS */ 572#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60) 573#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61) 574#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62) 575#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63) 576#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64) 577#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65) 578#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66) 579#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67) 580#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68) 581#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69) 582 583/* PPC64 eXternal Interrupt Controller Specification */ 584#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ 585 586/* Layout of 64-bit source attribute values */ 587#define KVM_XICS_DESTINATION_SHIFT 0 588#define KVM_XICS_DESTINATION_MASK 0xffffffffULL 589#define KVM_XICS_PRIORITY_SHIFT 32 590#define KVM_XICS_PRIORITY_MASK 0xff 591#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40) 592#define KVM_XICS_MASKED (1ULL << 41) 593#define KVM_XICS_PENDING (1ULL << 42) 594#define KVM_XICS_PRESENTED (1ULL << 43) 595#define KVM_XICS_QUEUED (1ULL << 44) 596 597#endif /* __LINUX_KVM_POWERPC_H */ 598