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27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
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60
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65
66
67
68
69enum i915_mocs_table_index {
70
71
72
73
74 I915_MOCS_UNCACHED,
75
76
77
78
79
80 I915_MOCS_PTE,
81
82
83
84
85
86 I915_MOCS_CACHED,
87};
88
89
90
91#define I915_NR_TEX_REGIONS 255
92
93#define I915_LOG_MIN_TEX_REGION_SIZE 14
94
95typedef struct _drm_i915_init {
96 enum {
97 I915_INIT_DMA = 0x01,
98 I915_CLEANUP_DMA = 0x02,
99 I915_RESUME_DMA = 0x03
100 } func;
101 unsigned int mmio_offset;
102 int sarea_priv_offset;
103 unsigned int ring_start;
104 unsigned int ring_end;
105 unsigned int ring_size;
106 unsigned int front_offset;
107 unsigned int back_offset;
108 unsigned int depth_offset;
109 unsigned int w;
110 unsigned int h;
111 unsigned int pitch;
112 unsigned int pitch_bits;
113 unsigned int back_pitch;
114 unsigned int depth_pitch;
115 unsigned int cpp;
116 unsigned int chipset;
117} drm_i915_init_t;
118
119typedef struct _drm_i915_sarea {
120 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
121 int last_upload;
122 int last_enqueue;
123 int last_dispatch;
124 int ctxOwner;
125 int texAge;
126 int pf_enabled;
127 int pf_active;
128 int pf_current_page;
129 int perf_boxes;
130 int width, height;
131
132 drm_handle_t front_handle;
133 int front_offset;
134 int front_size;
135
136 drm_handle_t back_handle;
137 int back_offset;
138 int back_size;
139
140 drm_handle_t depth_handle;
141 int depth_offset;
142 int depth_size;
143
144 drm_handle_t tex_handle;
145 int tex_offset;
146 int tex_size;
147 int log_tex_granularity;
148 int pitch;
149 int rotation;
150 int rotated_offset;
151 int rotated_size;
152 int rotated_pitch;
153 int virtualX, virtualY;
154
155 unsigned int front_tiled;
156 unsigned int back_tiled;
157 unsigned int depth_tiled;
158 unsigned int rotated_tiled;
159 unsigned int rotated2_tiled;
160
161 int pipeA_x;
162 int pipeA_y;
163 int pipeA_w;
164 int pipeA_h;
165 int pipeB_x;
166 int pipeB_y;
167 int pipeB_w;
168 int pipeB_h;
169
170
171 drm_handle_t unused_handle;
172 __u32 unused1, unused2, unused3;
173
174
175
176
177 __u32 front_bo_handle;
178 __u32 back_bo_handle;
179 __u32 unused_bo_handle;
180 __u32 depth_bo_handle;
181
182} drm_i915_sarea_t;
183
184
185#define planeA_x pipeA_x
186#define planeA_y pipeA_y
187#define planeA_w pipeA_w
188#define planeA_h pipeA_h
189#define planeB_x pipeB_x
190#define planeB_y pipeB_y
191#define planeB_w pipeB_w
192#define planeB_h pipeB_h
193
194
195
196#define I915_BOX_RING_EMPTY 0x1
197#define I915_BOX_FLIP 0x2
198#define I915_BOX_WAIT 0x4
199#define I915_BOX_TEXTURE_LOAD 0x8
200#define I915_BOX_LOST_CONTEXT 0x10
201
202
203
204
205
206
207
208
209#define DRM_I915_INIT 0x00
210#define DRM_I915_FLUSH 0x01
211#define DRM_I915_FLIP 0x02
212#define DRM_I915_BATCHBUFFER 0x03
213#define DRM_I915_IRQ_EMIT 0x04
214#define DRM_I915_IRQ_WAIT 0x05
215#define DRM_I915_GETPARAM 0x06
216#define DRM_I915_SETPARAM 0x07
217#define DRM_I915_ALLOC 0x08
218#define DRM_I915_FREE 0x09
219#define DRM_I915_INIT_HEAP 0x0a
220#define DRM_I915_CMDBUFFER 0x0b
221#define DRM_I915_DESTROY_HEAP 0x0c
222#define DRM_I915_SET_VBLANK_PIPE 0x0d
223#define DRM_I915_GET_VBLANK_PIPE 0x0e
224#define DRM_I915_VBLANK_SWAP 0x0f
225#define DRM_I915_HWS_ADDR 0x11
226#define DRM_I915_GEM_INIT 0x13
227#define DRM_I915_GEM_EXECBUFFER 0x14
228#define DRM_I915_GEM_PIN 0x15
229#define DRM_I915_GEM_UNPIN 0x16
230#define DRM_I915_GEM_BUSY 0x17
231#define DRM_I915_GEM_THROTTLE 0x18
232#define DRM_I915_GEM_ENTERVT 0x19
233#define DRM_I915_GEM_LEAVEVT 0x1a
234#define DRM_I915_GEM_CREATE 0x1b
235#define DRM_I915_GEM_PREAD 0x1c
236#define DRM_I915_GEM_PWRITE 0x1d
237#define DRM_I915_GEM_MMAP 0x1e
238#define DRM_I915_GEM_SET_DOMAIN 0x1f
239#define DRM_I915_GEM_SW_FINISH 0x20
240#define DRM_I915_GEM_SET_TILING 0x21
241#define DRM_I915_GEM_GET_TILING 0x22
242#define DRM_I915_GEM_GET_APERTURE 0x23
243#define DRM_I915_GEM_MMAP_GTT 0x24
244#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
245#define DRM_I915_GEM_MADVISE 0x26
246#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
247#define DRM_I915_OVERLAY_ATTRS 0x28
248#define DRM_I915_GEM_EXECBUFFER2 0x29
249#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
250#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
251#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
252#define DRM_I915_GEM_WAIT 0x2c
253#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
254#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
255#define DRM_I915_GEM_SET_CACHING 0x2f
256#define DRM_I915_GEM_GET_CACHING 0x30
257#define DRM_I915_REG_READ 0x31
258#define DRM_I915_GET_RESET_STATS 0x32
259#define DRM_I915_GEM_USERPTR 0x33
260#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
261#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
262#define DRM_I915_PERF_OPEN 0x36
263
264#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
265#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
266#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
267#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
268#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
269#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
270#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
271#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
272#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
273#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
274#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
275#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
276#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
277#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
278#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
279#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
280#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
281#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
282#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
283#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
284#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
285#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
286#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
287#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
288#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
289#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
290#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
291#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
292#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
293#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
294#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
295#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
296#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
297#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
298#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
299#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
300#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
301#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
302#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
303#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
304#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
305#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
306#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
307#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
308#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
309#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
310#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
311#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
312#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
313#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
314#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
315#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
316#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
317#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
318
319
320
321
322typedef struct drm_i915_batchbuffer {
323 int start;
324 int used;
325 int DR1;
326 int DR4;
327 int num_cliprects;
328 struct drm_clip_rect __user *cliprects;
329} drm_i915_batchbuffer_t;
330
331
332
333
334typedef struct _drm_i915_cmdbuffer {
335 char __user *buf;
336 int sz;
337 int DR1;
338 int DR4;
339 int num_cliprects;
340 struct drm_clip_rect __user *cliprects;
341} drm_i915_cmdbuffer_t;
342
343
344
345typedef struct drm_i915_irq_emit {
346 int __user *irq_seq;
347} drm_i915_irq_emit_t;
348
349typedef struct drm_i915_irq_wait {
350 int irq_seq;
351} drm_i915_irq_wait_t;
352
353
354
355#define I915_PARAM_IRQ_ACTIVE 1
356#define I915_PARAM_ALLOW_BATCHBUFFER 2
357#define I915_PARAM_LAST_DISPATCH 3
358#define I915_PARAM_CHIPSET_ID 4
359#define I915_PARAM_HAS_GEM 5
360#define I915_PARAM_NUM_FENCES_AVAIL 6
361#define I915_PARAM_HAS_OVERLAY 7
362#define I915_PARAM_HAS_PAGEFLIPPING 8
363#define I915_PARAM_HAS_EXECBUF2 9
364#define I915_PARAM_HAS_BSD 10
365#define I915_PARAM_HAS_BLT 11
366#define I915_PARAM_HAS_RELAXED_FENCING 12
367#define I915_PARAM_HAS_COHERENT_RINGS 13
368#define I915_PARAM_HAS_EXEC_CONSTANTS 14
369#define I915_PARAM_HAS_RELAXED_DELTA 15
370#define I915_PARAM_HAS_GEN7_SOL_RESET 16
371#define I915_PARAM_HAS_LLC 17
372#define I915_PARAM_HAS_ALIASING_PPGTT 18
373#define I915_PARAM_HAS_WAIT_TIMEOUT 19
374#define I915_PARAM_HAS_SEMAPHORES 20
375#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
376#define I915_PARAM_HAS_VEBOX 22
377#define I915_PARAM_HAS_SECURE_BATCHES 23
378#define I915_PARAM_HAS_PINNED_BATCHES 24
379#define I915_PARAM_HAS_EXEC_NO_RELOC 25
380#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
381#define I915_PARAM_HAS_WT 27
382#define I915_PARAM_CMD_PARSER_VERSION 28
383#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
384#define I915_PARAM_MMAP_VERSION 30
385#define I915_PARAM_HAS_BSD2 31
386#define I915_PARAM_REVISION 32
387#define I915_PARAM_SUBSLICE_TOTAL 33
388#define I915_PARAM_EU_TOTAL 34
389#define I915_PARAM_HAS_GPU_RESET 35
390#define I915_PARAM_HAS_RESOURCE_STREAMER 36
391#define I915_PARAM_HAS_EXEC_SOFTPIN 37
392#define I915_PARAM_HAS_POOLED_EU 38
393#define I915_PARAM_MIN_EU_IN_POOL 39
394#define I915_PARAM_MMAP_GTT_VERSION 40
395
396
397
398
399#define I915_PARAM_HAS_SCHEDULER 41
400#define I915_PARAM_HUC_STATUS 42
401
402
403
404
405
406#define I915_PARAM_HAS_EXEC_ASYNC 43
407
408
409
410
411
412
413#define I915_PARAM_HAS_EXEC_FENCE 44
414
415
416
417
418
419#define I915_PARAM_HAS_EXEC_CAPTURE 45
420
421#define I915_PARAM_SLICE_MASK 46
422
423
424
425
426#define I915_PARAM_SUBSLICE_MASK 47
427
428
429
430
431
432#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
433
434typedef struct drm_i915_getparam {
435 __s32 param;
436
437
438
439
440 int __user *value;
441} drm_i915_getparam_t;
442
443
444
445#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
446#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
447#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
448#define I915_SETPARAM_NUM_USED_FENCES 4
449
450typedef struct drm_i915_setparam {
451 int param;
452 int value;
453} drm_i915_setparam_t;
454
455
456
457#define I915_MEM_REGION_AGP 1
458
459typedef struct drm_i915_mem_alloc {
460 int region;
461 int alignment;
462 int size;
463 int __user *region_offset;
464} drm_i915_mem_alloc_t;
465
466typedef struct drm_i915_mem_free {
467 int region;
468 int region_offset;
469} drm_i915_mem_free_t;
470
471typedef struct drm_i915_mem_init_heap {
472 int region;
473 int size;
474 int start;
475} drm_i915_mem_init_heap_t;
476
477
478
479
480typedef struct drm_i915_mem_destroy_heap {
481 int region;
482} drm_i915_mem_destroy_heap_t;
483
484
485
486#define DRM_I915_VBLANK_PIPE_A 1
487#define DRM_I915_VBLANK_PIPE_B 2
488
489typedef struct drm_i915_vblank_pipe {
490 int pipe;
491} drm_i915_vblank_pipe_t;
492
493
494
495typedef struct drm_i915_vblank_swap {
496 drm_drawable_t drawable;
497 enum drm_vblank_seq_type seqtype;
498 unsigned int sequence;
499} drm_i915_vblank_swap_t;
500
501typedef struct drm_i915_hws_addr {
502 __u64 addr;
503} drm_i915_hws_addr_t;
504
505struct drm_i915_gem_init {
506
507
508
509
510 __u64 gtt_start;
511
512
513
514
515 __u64 gtt_end;
516};
517
518struct drm_i915_gem_create {
519
520
521
522
523
524 __u64 size;
525
526
527
528
529
530 __u32 handle;
531 __u32 pad;
532};
533
534struct drm_i915_gem_pread {
535
536 __u32 handle;
537 __u32 pad;
538
539 __u64 offset;
540
541 __u64 size;
542
543
544
545
546
547 __u64 data_ptr;
548};
549
550struct drm_i915_gem_pwrite {
551
552 __u32 handle;
553 __u32 pad;
554
555 __u64 offset;
556
557 __u64 size;
558
559
560
561
562
563 __u64 data_ptr;
564};
565
566struct drm_i915_gem_mmap {
567
568 __u32 handle;
569 __u32 pad;
570
571 __u64 offset;
572
573
574
575
576
577 __u64 size;
578
579
580
581
582
583 __u64 addr_ptr;
584
585
586
587
588
589
590 __u64 flags;
591#define I915_MMAP_WC 0x1
592};
593
594struct drm_i915_gem_mmap_gtt {
595
596 __u32 handle;
597 __u32 pad;
598
599
600
601
602
603 __u64 offset;
604};
605
606struct drm_i915_gem_set_domain {
607
608 __u32 handle;
609
610
611 __u32 read_domains;
612
613
614 __u32 write_domain;
615};
616
617struct drm_i915_gem_sw_finish {
618
619 __u32 handle;
620};
621
622struct drm_i915_gem_relocation_entry {
623
624
625
626
627
628
629
630
631 __u32 target_handle;
632
633
634
635
636
637 __u32 delta;
638
639
640 __u64 offset;
641
642
643
644
645
646
647
648
649
650 __u64 presumed_offset;
651
652
653
654
655 __u32 read_domains;
656
657
658
659
660
661
662
663
664 __u32 write_domain;
665};
666
667
668
669
670
671
672
673
674
675#define I915_GEM_DOMAIN_CPU 0x00000001
676
677#define I915_GEM_DOMAIN_RENDER 0x00000002
678
679#define I915_GEM_DOMAIN_SAMPLER 0x00000004
680
681#define I915_GEM_DOMAIN_COMMAND 0x00000008
682
683#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
684
685#define I915_GEM_DOMAIN_VERTEX 0x00000020
686
687#define I915_GEM_DOMAIN_GTT 0x00000040
688
689#define I915_GEM_DOMAIN_WC 0x00000080
690
691
692struct drm_i915_gem_exec_object {
693
694
695
696
697 __u32 handle;
698
699
700 __u32 relocation_count;
701
702
703
704
705 __u64 relocs_ptr;
706
707
708 __u64 alignment;
709
710
711
712
713
714 __u64 offset;
715};
716
717struct drm_i915_gem_execbuffer {
718
719
720
721
722
723
724
725
726
727
728 __u64 buffers_ptr;
729 __u32 buffer_count;
730
731
732 __u32 batch_start_offset;
733
734 __u32 batch_len;
735 __u32 DR1;
736 __u32 DR4;
737 __u32 num_cliprects;
738
739 __u64 cliprects_ptr;
740};
741
742struct drm_i915_gem_exec_object2 {
743
744
745
746
747 __u32 handle;
748
749
750 __u32 relocation_count;
751
752
753
754
755 __u64 relocs_ptr;
756
757
758 __u64 alignment;
759
760
761
762
763
764
765
766
767
768 __u64 offset;
769
770#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
771#define EXEC_OBJECT_NEEDS_GTT (1<<1)
772#define EXEC_OBJECT_WRITE (1<<2)
773#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
774#define EXEC_OBJECT_PINNED (1<<4)
775#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796#define EXEC_OBJECT_ASYNC (1<<6)
797
798
799
800
801
802
803#define EXEC_OBJECT_CAPTURE (1<<7)
804
805#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
806 __u64 flags;
807
808 union {
809 __u64 rsvd1;
810 __u64 pad_to_size;
811 };
812 __u64 rsvd2;
813};
814
815struct drm_i915_gem_execbuffer2 {
816
817
818
819 __u64 buffers_ptr;
820 __u32 buffer_count;
821
822
823 __u32 batch_start_offset;
824
825 __u32 batch_len;
826 __u32 DR1;
827 __u32 DR4;
828 __u32 num_cliprects;
829
830 __u64 cliprects_ptr;
831#define I915_EXEC_RING_MASK (7<<0)
832#define I915_EXEC_DEFAULT (0<<0)
833#define I915_EXEC_RENDER (1<<0)
834#define I915_EXEC_BSD (2<<0)
835#define I915_EXEC_BLT (3<<0)
836#define I915_EXEC_VEBOX (4<<0)
837
838
839
840
841
842
843
844#define I915_EXEC_CONSTANTS_MASK (3<<6)
845#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)
846#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
847#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)
848 __u64 flags;
849 __u64 rsvd1;
850 __u64 rsvd2;
851};
852
853
854#define I915_EXEC_GEN7_SOL_RESET (1<<8)
855
856
857
858
859#define I915_EXEC_SECURE (1<<9)
860
861
862
863
864
865
866
867
868#define I915_EXEC_IS_PINNED (1<<10)
869
870
871
872
873
874
875#define I915_EXEC_NO_RELOC (1<<11)
876
877
878
879
880#define I915_EXEC_HANDLE_LUT (1<<12)
881
882
883#define I915_EXEC_BSD_SHIFT (13)
884#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
885
886#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
887#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
888#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
889
890
891
892
893#define I915_EXEC_RESOURCE_STREAMER (1<<15)
894
895
896
897
898
899
900
901#define I915_EXEC_FENCE_IN (1<<16)
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918#define I915_EXEC_FENCE_OUT (1<<17)
919
920
921
922
923
924
925
926
927
928
929#define I915_EXEC_BATCH_FIRST (1<<18)
930#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1))
931
932#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
933#define i915_execbuffer2_set_context_id(eb2, context) \
934 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
935#define i915_execbuffer2_get_context_id(eb2) \
936 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
937
938struct drm_i915_gem_pin {
939
940 __u32 handle;
941 __u32 pad;
942
943
944 __u64 alignment;
945
946
947 __u64 offset;
948};
949
950struct drm_i915_gem_unpin {
951
952 __u32 handle;
953 __u32 pad;
954};
955
956struct drm_i915_gem_busy {
957
958 __u32 handle;
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004 __u32 busy;
1005};
1006
1007
1008
1009
1010
1011
1012
1013#define I915_CACHING_NONE 0
1014
1015
1016
1017
1018
1019
1020
1021#define I915_CACHING_CACHED 1
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032#define I915_CACHING_DISPLAY 2
1033
1034struct drm_i915_gem_caching {
1035
1036
1037 __u32 handle;
1038
1039
1040
1041
1042
1043
1044
1045 __u32 caching;
1046};
1047
1048#define I915_TILING_NONE 0
1049#define I915_TILING_X 1
1050#define I915_TILING_Y 2
1051#define I915_TILING_LAST I915_TILING_Y
1052
1053#define I915_BIT_6_SWIZZLE_NONE 0
1054#define I915_BIT_6_SWIZZLE_9 1
1055#define I915_BIT_6_SWIZZLE_9_10 2
1056#define I915_BIT_6_SWIZZLE_9_11 3
1057#define I915_BIT_6_SWIZZLE_9_10_11 4
1058
1059#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1060
1061#define I915_BIT_6_SWIZZLE_9_17 6
1062#define I915_BIT_6_SWIZZLE_9_10_17 7
1063
1064struct drm_i915_gem_set_tiling {
1065
1066 __u32 handle;
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080 __u32 tiling_mode;
1081
1082
1083
1084
1085
1086 __u32 stride;
1087
1088
1089
1090
1091
1092 __u32 swizzle_mode;
1093};
1094
1095struct drm_i915_gem_get_tiling {
1096
1097 __u32 handle;
1098
1099
1100
1101
1102
1103 __u32 tiling_mode;
1104
1105
1106
1107
1108
1109 __u32 swizzle_mode;
1110
1111
1112
1113
1114
1115 __u32 phys_swizzle_mode;
1116};
1117
1118struct drm_i915_gem_get_aperture {
1119
1120 __u64 aper_size;
1121
1122
1123
1124
1125
1126 __u64 aper_available_size;
1127};
1128
1129struct drm_i915_get_pipe_from_crtc_id {
1130
1131 __u32 crtc_id;
1132
1133
1134 __u32 pipe;
1135};
1136
1137#define I915_MADV_WILLNEED 0
1138#define I915_MADV_DONTNEED 1
1139#define __I915_MADV_PURGED 2
1140
1141struct drm_i915_gem_madvise {
1142
1143 __u32 handle;
1144
1145
1146
1147
1148 __u32 madv;
1149
1150
1151 __u32 retained;
1152};
1153
1154
1155#define I915_OVERLAY_TYPE_MASK 0xff
1156#define I915_OVERLAY_YUV_PLANAR 0x01
1157#define I915_OVERLAY_YUV_PACKED 0x02
1158#define I915_OVERLAY_RGB 0x03
1159
1160#define I915_OVERLAY_DEPTH_MASK 0xff00
1161#define I915_OVERLAY_RGB24 0x1000
1162#define I915_OVERLAY_RGB16 0x2000
1163#define I915_OVERLAY_RGB15 0x3000
1164#define I915_OVERLAY_YUV422 0x0100
1165#define I915_OVERLAY_YUV411 0x0200
1166#define I915_OVERLAY_YUV420 0x0300
1167#define I915_OVERLAY_YUV410 0x0400
1168
1169#define I915_OVERLAY_SWAP_MASK 0xff0000
1170#define I915_OVERLAY_NO_SWAP 0x000000
1171#define I915_OVERLAY_UV_SWAP 0x010000
1172#define I915_OVERLAY_Y_SWAP 0x020000
1173#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1174
1175#define I915_OVERLAY_FLAGS_MASK 0xff000000
1176#define I915_OVERLAY_ENABLE 0x01000000
1177
1178struct drm_intel_overlay_put_image {
1179
1180 __u32 flags;
1181
1182 __u32 bo_handle;
1183
1184 __u16 stride_Y;
1185 __u16 stride_UV;
1186 __u32 offset_Y;
1187 __u32 offset_U;
1188 __u32 offset_V;
1189
1190 __u16 src_width;
1191 __u16 src_height;
1192
1193 __u16 src_scan_width;
1194 __u16 src_scan_height;
1195
1196 __u32 crtc_id;
1197 __u16 dst_x;
1198 __u16 dst_y;
1199 __u16 dst_width;
1200 __u16 dst_height;
1201};
1202
1203
1204#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1205#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1206#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1207struct drm_intel_overlay_attrs {
1208 __u32 flags;
1209 __u32 color_key;
1210 __s32 brightness;
1211 __u32 contrast;
1212 __u32 saturation;
1213 __u32 gamma0;
1214 __u32 gamma1;
1215 __u32 gamma2;
1216 __u32 gamma3;
1217 __u32 gamma4;
1218 __u32 gamma5;
1219};
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242#define I915_SET_COLORKEY_NONE (1<<0)
1243#define I915_SET_COLORKEY_DESTINATION (1<<1)
1244#define I915_SET_COLORKEY_SOURCE (1<<2)
1245struct drm_intel_sprite_colorkey {
1246 __u32 plane_id;
1247 __u32 min_value;
1248 __u32 channel_mask;
1249 __u32 max_value;
1250 __u32 flags;
1251};
1252
1253struct drm_i915_gem_wait {
1254
1255 __u32 bo_handle;
1256 __u32 flags;
1257
1258 __s64 timeout_ns;
1259};
1260
1261struct drm_i915_gem_context_create {
1262
1263 __u32 ctx_id;
1264 __u32 pad;
1265};
1266
1267struct drm_i915_gem_context_destroy {
1268 __u32 ctx_id;
1269 __u32 pad;
1270};
1271
1272struct drm_i915_reg_read {
1273
1274
1275
1276
1277
1278
1279 __u64 offset;
1280 __u64 val;
1281};
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291struct drm_i915_reset_stats {
1292 __u32 ctx_id;
1293 __u32 flags;
1294
1295
1296 __u32 reset_count;
1297
1298
1299 __u32 batch_active;
1300
1301
1302 __u32 batch_pending;
1303
1304 __u32 pad;
1305};
1306
1307struct drm_i915_gem_userptr {
1308 __u64 user_ptr;
1309 __u64 user_size;
1310 __u32 flags;
1311#define I915_USERPTR_READ_ONLY 0x1
1312#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1313
1314
1315
1316
1317
1318 __u32 handle;
1319};
1320
1321struct drm_i915_gem_context_param {
1322 __u32 ctx_id;
1323 __u32 size;
1324 __u64 param;
1325#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1326#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1327#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1328#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1329#define I915_CONTEXT_PARAM_BANNABLE 0x5
1330 __u64 value;
1331};
1332
1333enum drm_i915_oa_format {
1334 I915_OA_FORMAT_A13 = 1,
1335 I915_OA_FORMAT_A29,
1336 I915_OA_FORMAT_A13_B8_C8,
1337 I915_OA_FORMAT_B4_C8,
1338 I915_OA_FORMAT_A45_B8_C8,
1339 I915_OA_FORMAT_B4_C8_A16,
1340 I915_OA_FORMAT_C4_B8,
1341
1342
1343 I915_OA_FORMAT_A12,
1344 I915_OA_FORMAT_A12_B8_C8,
1345 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1346
1347 I915_OA_FORMAT_MAX
1348};
1349
1350enum drm_i915_perf_property_id {
1351
1352
1353
1354
1355
1356 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1357
1358
1359
1360
1361
1362 DRM_I915_PERF_PROP_SAMPLE_OA,
1363
1364
1365
1366
1367
1368 DRM_I915_PERF_PROP_OA_METRICS_SET,
1369
1370
1371
1372
1373 DRM_I915_PERF_PROP_OA_FORMAT,
1374
1375
1376
1377
1378
1379
1380
1381
1382 DRM_I915_PERF_PROP_OA_EXPONENT,
1383
1384 DRM_I915_PERF_PROP_MAX
1385};
1386
1387struct drm_i915_perf_open_param {
1388 __u32 flags;
1389#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1390#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1391#define I915_PERF_FLAG_DISABLED (1<<2)
1392
1393
1394 __u32 num_properties;
1395
1396
1397
1398
1399
1400 __u64 properties_ptr;
1401};
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1414
1415
1416
1417
1418
1419
1420#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1421
1422
1423
1424
1425struct drm_i915_perf_record_header {
1426 __u32 type;
1427 __u16 pad;
1428 __u16 size;
1429};
1430
1431enum drm_i915_perf_record_type {
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452 DRM_I915_PERF_RECORD_SAMPLE = 1,
1453
1454
1455
1456
1457
1458
1459
1460 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1461
1462
1463
1464
1465 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1466
1467 DRM_I915_PERF_RECORD_MAX
1468};
1469
1470#if defined(__cplusplus)
1471}
1472#endif
1473
1474#endif
1475