LXR linux/arch/arm/mach-s3c24xx/include/mach/dma.h

   1/* arch/arm/mach-s3c2410/include/mach/dma.h
   2 *
   3 * Copyright (C) 2003-2006 Simtec Electronics
   4 *      Ben Dooks <ben@simtec.co.uk>
   5 *
   6 * Samsung S3C24XX DMA support
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11*/
  12
  13#ifndef __ASM_ARCH_DMA_H
  14#define __ASM_ARCH_DMA_H __FILE__
  15
  16#include <linux/device.h>
  17
  18#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  19
  20/* We use `virtual` dma channels to hide the fact we have only a limited
  21 * number of DMA channels, and not of all of them (dependent on the device)
  22 * can be attached to any DMA source. We therefore let the DMA core handle
  23 * the allocation of hardware channels to clients.
  24*/
  25
  26enum dma_ch {
  27        DMACH_XD0 = 0,
  28        DMACH_XD1,
  29        DMACH_SDI,
  30        DMACH_SPI0,
  31        DMACH_SPI1,
  32        DMACH_UART0,
  33        DMACH_UART1,
  34        DMACH_UART2,
  35        DMACH_TIMER,
  36        DMACH_I2S_IN,
  37        DMACH_I2S_OUT,
  38        DMACH_PCM_IN,
  39        DMACH_PCM_OUT,
  40        DMACH_MIC_IN,
  41        DMACH_USB_EP1,
  42        DMACH_USB_EP2,
  43        DMACH_USB_EP3,
  44        DMACH_USB_EP4,
  45        DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
  46        DMACH_UART1_SRC2,
  47        DMACH_UART2_SRC2,
  48        DMACH_UART3,            /* s3c2443 has extra uart */
  49        DMACH_UART3_SRC2,
  50        DMACH_SPI0_TX,          /* s3c2443/2416/2450 hsspi0 */
  51        DMACH_SPI0_RX,          /* s3c2443/2416/2450 hsspi0 */
  52        DMACH_SPI1_TX,          /* s3c2443/2450 hsspi1 */
  53        DMACH_SPI1_RX,          /* s3c2443/2450 hsspi1 */
  54        DMACH_MAX,              /* the end entry */
  55};
  56
  57static inline bool samsung_dma_has_circular(void)
  58{
  59        return false;
  60}
  61
  62static inline bool samsung_dma_is_dmadev(void)
  63{
  64        return false;
  65}
  66
  67#include <plat/dma.h>
  68
  69#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
  70
  71/* we have 4 dma channels */
  72#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
  73#define S3C_DMA_CHANNELS                (4)
  74#else
  75#define S3C_DMA_CHANNELS                (6)
  76#endif
  77
  78/* types */
  79
  80enum s3c2410_dma_state {
  81        S3C2410_DMA_IDLE,
  82        S3C2410_DMA_RUNNING,
  83        S3C2410_DMA_PAUSED
  84};
  85
  86/* enum s3c2410_dma_loadst
  87 *
  88 * This represents the state of the DMA engine, wrt to the loaded / running
  89 * transfers. Since we don't have any way of knowing exactly the state of
  90 * the DMA transfers, we need to know the state to make decisions on whether
  91 * we can
  92 *
  93 * S3C2410_DMA_NONE
  94 *
  95 * There are no buffers loaded (the channel should be inactive)
  96 *
  97 * S3C2410_DMA_1LOADED
  98 *
  99 * There is one buffer loaded, however it has not been confirmed to be
 100 * loaded by the DMA engine. This may be because the channel is not
 101 * yet running, or the DMA driver decided that it was too costly to
 102 * sit and wait for it to happen.
 103 *
 104 * S3C2410_DMA_1RUNNING
 105 *
 106 * The buffer has been confirmed running, and not finisged
 107 *
 108 * S3C2410_DMA_1LOADED_1RUNNING
 109 *
 110 * There is a buffer waiting to be loaded by the DMA engine, and one
 111 * currently running.
 112*/
 113
 114enum s3c2410_dma_loadst {
 115        S3C2410_DMALOAD_NONE,
 116        S3C2410_DMALOAD_1LOADED,
 117        S3C2410_DMALOAD_1RUNNING,
 118        S3C2410_DMALOAD_1LOADED_1RUNNING,
 119};
 120
 121
 122/* flags */
 123
 124#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 125                                            * waiting for reloads */
 126#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 127
 128#define S3C2410_DMAF_CIRCULAR   (1 << 2)        /* no circular dma support */
 129
 130/* dma buffer */
 131
 132struct s3c2410_dma_buf;
 133
 134/* s3c2410_dma_buf
 135 *
 136 * internally used buffer structure to describe a queued or running
 137 * buffer.
 138*/
 139
 140struct s3c2410_dma_buf {
 141        struct s3c2410_dma_buf  *next;
 142        int                      magic;         /* magic */
 143        int                      size;          /* buffer size in bytes */
 144        dma_addr_t               data;          /* start of DMA data */
 145        dma_addr_t               ptr;           /* where the DMA got to [1] */
 146        void                    *id;            /* client's id */
 147};
 148
 149/* [1] is this updated for both recv/send modes? */
 150
 151struct s3c2410_dma_stats {
 152        unsigned long           loads;
 153        unsigned long           timeout_longest;
 154        unsigned long           timeout_shortest;
 155        unsigned long           timeout_avg;
 156        unsigned long           timeout_failed;
 157};
 158
 159struct s3c2410_dma_map;
 160
 161/* struct s3c2410_dma_chan
 162 *
 163 * full state information for each DMA channel
 164*/
 165
 166struct s3c2410_dma_chan {
 167        /* channel state flags and information */
 168        unsigned char            number;      /* number of this dma channel */
 169        unsigned char            in_use;      /* channel allocated */
 170        unsigned char            irq_claimed; /* irq claimed for channel */
 171        unsigned char            irq_enabled; /* irq enabled for channel */
 172        unsigned char            xfer_unit;   /* size of an transfer */
 173
 174        /* channel state */
 175
 176        enum s3c2410_dma_state   state;
 177        enum s3c2410_dma_loadst  load_state;
 178        struct s3c2410_dma_client *client;
 179
 180        /* channel configuration */
 181        enum dma_data_direction  source;
 182        enum dma_ch              req_ch;
 183        unsigned long            dev_addr;
 184        unsigned long            load_timeout;
 185        unsigned int             flags;         /* channel flags */
 186
 187        struct s3c24xx_dma_map  *map;           /* channel hw maps */
 188
 189        /* channel's hardware position and configuration */
 190        void __iomem            *regs;          /* channels registers */
 191        void __iomem            *addr_reg;      /* data address register */
 192        unsigned int             irq;           /* channel irq */
 193        unsigned long            dcon;          /* default value of DCON */
 194
 195        /* driver handles */
 196        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 197        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 198
 199        /* stats gathering */
 200        struct s3c2410_dma_stats *stats;
 201        struct s3c2410_dma_stats  stats_store;
 202
 203        /* buffer list and information */
 204        struct s3c2410_dma_buf  *curr;          /* current dma buffer */
 205        struct s3c2410_dma_buf  *next;          /* next buffer to load */
 206        struct s3c2410_dma_buf  *end;           /* end of queue */
 207
 208        /* system device */
 209        struct device   dev;
 210};
 211
 212typedef unsigned long dma_device_t;
 213
 214#endif /* __ASM_ARCH_DMA_H */
 215