LXR linux/arch/m68k/include/asm/m68360

   1/***********************************
   2 * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
   3 ***********************************
   4 *
   5 ***************************************
   6 * Definitions of QUICC memory structures
   7 ***************************************
   8 */
   9
  10#ifndef __M68360_QUICC_H
  11#define __M68360_QUICC_H
  12
  13/*
  14 * include registers and
  15 * parameter ram definitions files
  16 */
  17#include <asm/m68360_regs.h>
  18#include <asm/m68360_pram.h>
  19
  20
  21
  22/* Buffer Descriptors */
  23typedef struct quicc_bd {
  24    volatile unsigned short     status;
  25    volatile unsigned short     length;
  26    volatile unsigned char      *buf;     /* WARNING: This is only true if *char is 32 bits */
  27} QUICC_BD;
  28
  29
  30#ifdef MOTOROLA_ORIGINAL
  31struct user_data {
  32    /* BASE + 0x000: user data memory */
  33    volatile unsigned char      udata_bd_ucode[0x400]; /*user data bd's Ucode*/
  34    volatile unsigned char      udata_bd[0x200];       /*user data Ucode     */
  35    volatile unsigned char      ucode_ext[0x100];      /*Ucode Extension ram */
  36    volatile unsigned char      RESERVED1[0x500];      /* Reserved area      */
  37};
  38#else
  39struct user_data {
  40    /* BASE + 0x000: user data memory */
  41    volatile unsigned char      udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
  42    volatile unsigned char      udata_bd1[0x200];       /* user, bds */
  43    volatile unsigned char      ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
  44    volatile unsigned char      udata_bd2[0x100];       /* user, bds */
  45    volatile unsigned char      RESERVED1[0x400];      /* Reserved area      */
  46};
  47#endif
  48
  49
  50/*
  51 * internal ram
  52 */
  53typedef struct quicc {
  54        union {
  55                struct quicc32_pram ch_pram_tbl[32];    /* 32*64(bytes) per channel */  
  56                struct user_data                u;
  57        }ch_or_u;       /* multipul or user space */
  58
  59    /* BASE + 0xc00: PARAMETER RAM */
  60        union {
  61                struct scc_pram {
  62                        union {
  63                                struct hdlc_pram        h;
  64                                struct uart_pram        u;
  65                                struct bisync_pram      b;
  66                                struct transparent_pram t;
  67                                unsigned char   RESERVED66[0x70];
  68                        } pscc;               /* scc parameter area (protocol dependent) */
  69                        union {
  70                                struct {
  71                                        unsigned char       RESERVED70[0x10];
  72                                        struct spi_pram     spi;
  73                                        unsigned char       RESERVED72[0x8];
  74                                        struct timer_pram   timer;
  75                                } timer_spi;
  76                                struct {
  77                                        struct idma_pram idma;
  78                                        unsigned char       RESERVED67[0x4];
  79                                        union {
  80                                                struct smc_uart_pram u;
  81                                                struct smc_trnsp_pram t;
  82                                        } psmc;
  83                                } idma_smc;
  84                        } pothers;
  85                } scc;
  86                struct ethernet_pram    enet_scc;
  87                struct global_multi_pram        m;
  88                unsigned char   pr[0x100];
  89        } pram[4];
  90
  91    /* reserved */
  92
  93    /* BASE + 0x1000: INTERNAL REGISTERS */
  94    /* SIM */
  95    volatile unsigned long      sim_mcr;        /* module configuration reg */
  96    volatile unsigned short     sim_simtr;      /* module test register     */
  97    volatile unsigned char      RESERVED2[0x2]; /* Reserved area            */
  98    volatile unsigned char      sim_avr;        /* auto vector reg          */
  99    volatile unsigned char      sim_rsr;        /* reset status reg         */
 100    volatile unsigned char      RESERVED3[0x2]; /* Reserved area            */
 101    volatile unsigned char      sim_clkocr;     /* CLCO control register    */
 102    volatile unsigned char      RESERVED62[0x3];        /* Reserved area    */
 103    volatile unsigned short     sim_pllcr;      /* PLL control register     */
 104    volatile unsigned char      RESERVED63[0x2];        /* Reserved area    */
 105    volatile unsigned short     sim_cdvcr;      /* Clock devider control register */
 106    volatile unsigned short     sim_pepar;      /* Port E pin assignment register */
 107    volatile unsigned char      RESERVED64[0xa];        /* Reserved area    */
 108    volatile unsigned char      sim_sypcr;      /* system protection control*/
 109    volatile unsigned char      sim_swiv;       /* software interrupt vector*/
 110    volatile unsigned char      RESERVED6[0x2]; /* Reserved area            */
 111    volatile unsigned short     sim_picr;       /* periodic interrupt control reg */
 112    volatile unsigned char      RESERVED7[0x2]; /* Reserved area            */
 113    volatile unsigned short     sim_pitr;       /* periodic interrupt timing reg */
 114    volatile unsigned char      RESERVED8[0x3]; /* Reserved area            */
 115    volatile unsigned char      sim_swsr;       /* software service         */
 116    volatile unsigned long      sim_bkar;       /* breakpoint address register*/
 117    volatile unsigned long      sim_bkcr;       /* breakpoint control register*/
 118    volatile unsigned char      RESERVED10[0x8];        /* Reserved area    */
 119    /* MEMC */
 120    volatile unsigned long      memc_gmr;       /* Global memory register   */
 121    volatile unsigned short     memc_mstat;     /* MEMC status register     */
 122    volatile unsigned char      RESERVED11[0xa];        /* Reserved area    */
 123    volatile unsigned long      memc_br0;       /* base register 0          */
 124    volatile unsigned long      memc_or0;       /* option register 0        */
 125    volatile unsigned char      RESERVED12[0x8];        /* Reserved area    */
 126    volatile unsigned long      memc_br1;       /* base register 1          */
 127    volatile unsigned long      memc_or1;       /* option register 1        */
 128    volatile unsigned char      RESERVED13[0x8];        /* Reserved area    */
 129    volatile unsigned long      memc_br2;       /* base register 2          */
 130    volatile unsigned long      memc_or2;       /* option register 2        */
 131    volatile unsigned char      RESERVED14[0x8];        /* Reserved area    */
 132    volatile unsigned long      memc_br3;       /* base register 3          */
 133    volatile unsigned long      memc_or3;       /* option register 3        */
 134    volatile unsigned char      RESERVED15[0x8];        /* Reserved area    */
 135    volatile unsigned long      memc_br4;       /* base register 3          */
 136    volatile unsigned long      memc_or4;       /* option register 3        */
 137    volatile unsigned char      RESERVED16[0x8];        /* Reserved area    */
 138    volatile unsigned long      memc_br5;       /* base register 3          */
 139    volatile unsigned long      memc_or5;       /* option register 3        */
 140    volatile unsigned char      RESERVED17[0x8];        /* Reserved area    */
 141    volatile unsigned long      memc_br6;       /* base register 3          */
 142    volatile unsigned long      memc_or6;       /* option register 3        */
 143    volatile unsigned char      RESERVED18[0x8];        /* Reserved area    */
 144    volatile unsigned long      memc_br7;       /* base register 3          */
 145    volatile unsigned long      memc_or7;       /* option register 3        */
 146    volatile unsigned char      RESERVED9[0x28];        /* Reserved area    */
 147    /* TEST */
 148    volatile unsigned short     test_tstmra;    /* master shift a           */
 149    volatile unsigned short     test_tstmrb;    /* master shift b           */
 150    volatile unsigned short     test_tstsc;     /* shift count              */
 151    volatile unsigned short     test_tstrc;     /* repetition counter       */
 152    volatile unsigned short     test_creg;      /* control                  */
 153    volatile unsigned short     test_dreg;      /* destributed register     */
 154    volatile unsigned char      RESERVED58[0x404];      /* Reserved area    */
 155    /* IDMA1 */
 156    volatile unsigned short     idma_iccr;      /* channel configuration reg*/
 157    volatile unsigned char      RESERVED19[0x2];        /* Reserved area    */
 158    volatile unsigned short     idma1_cmr;      /* dma mode reg             */
 159    volatile unsigned char      RESERVED68[0x2];        /* Reserved area    */
 160    volatile unsigned long      idma1_sapr;     /* dma source addr ptr      */
 161    volatile unsigned long      idma1_dapr;     /* dma destination addr ptr */
 162    volatile unsigned long      idma1_bcr;      /* dma byte count reg       */
 163    volatile unsigned char      idma1_fcr;      /* function code reg        */
 164    volatile unsigned char      RESERVED20;     /* Reserved area            */
 165    volatile unsigned char      idma1_cmar;     /* channel mask reg         */
 166    volatile unsigned char      RESERVED21;     /* Reserved area            */
 167    volatile unsigned char      idma1_csr;      /* channel status reg       */
 168    volatile unsigned char      RESERVED22[0x3];        /* Reserved area    */
 169    /* SDMA */
 170    volatile unsigned char      sdma_sdsr;      /* status reg               */
 171    volatile unsigned char      RESERVED23;     /* Reserved area            */
 172    volatile unsigned short     sdma_sdcr;      /* configuration reg        */
 173    volatile unsigned long      sdma_sdar;      /* address reg              */
 174    /* IDMA2 */
 175    volatile unsigned char      RESERVED69[0x2];        /* Reserved area    */
 176    volatile unsigned short     idma2_cmr;      /* dma mode reg             */
 177    volatile unsigned long      idma2_sapr;     /* dma source addr ptr      */
 178    volatile unsigned long      idma2_dapr;     /* dma destination addr ptr */
 179    volatile unsigned long      idma2_bcr;      /* dma byte count reg       */
 180    volatile unsigned char      idma2_fcr;      /* function code reg        */
 181    volatile unsigned char      RESERVED24;     /* Reserved area            */
 182    volatile unsigned char      idma2_cmar;     /* channel mask reg         */
 183    volatile unsigned char      RESERVED25;     /* Reserved area            */
 184    volatile unsigned char      idma2_csr;      /* channel status reg       */
 185    volatile unsigned char      RESERVED26[0x7];        /* Reserved area    */
 186    /* Interrupt Controller */
 187    volatile unsigned long      intr_cicr;      /* CP interrupt configuration reg*/
 188    volatile unsigned long      intr_cipr;      /* CP interrupt pending reg */
 189    volatile unsigned long      intr_cimr;      /* CP interrupt mask reg    */
 190    volatile unsigned long      intr_cisr;      /* CP interrupt in service reg*/
 191    /* Parallel I/O */
 192    volatile unsigned short     pio_padir;      /* port A data direction reg */
 193    volatile unsigned short     pio_papar;      /* port A pin assignment reg */
 194    volatile unsigned short     pio_paodr;      /* port A open drain reg    */
 195    volatile unsigned short     pio_padat;      /* port A data register     */
 196    volatile unsigned char      RESERVED28[0x8];        /* Reserved area    */
 197    volatile unsigned short     pio_pcdir;      /* port C data direction reg*/
 198    volatile unsigned short     pio_pcpar;      /* port C pin assignment reg*/
 199    volatile unsigned short     pio_pcso;       /* port C special options   */
 200    volatile unsigned short     pio_pcdat;      /* port C data register     */
 201    volatile unsigned short     pio_pcint;      /* port C interrupt cntrl reg */
 202    volatile unsigned char      RESERVED29[0x16];       /* Reserved area    */
 203    /* Timer */
 204    volatile unsigned short     timer_tgcr;     /* timer global configuration reg */
 205    volatile unsigned char      RESERVED30[0xe];        /* Reserved area    */
 206    volatile unsigned short     timer_tmr1;     /* timer 1 mode reg         */
 207    volatile unsigned short     timer_tmr2;     /* timer 2 mode reg         */
 208    volatile unsigned short     timer_trr1;     /* timer 1 referance reg    */
 209    volatile unsigned short     timer_trr2;     /* timer 2 referance reg    */
 210    volatile unsigned short     timer_tcr1;     /* timer 1 capture reg      */
 211    volatile unsigned short     timer_tcr2;     /* timer 2 capture reg      */
 212    volatile unsigned short     timer_tcn1;     /* timer 1 counter reg      */
 213    volatile unsigned short     timer_tcn2;     /* timer 2 counter reg      */
 214    volatile unsigned short     timer_tmr3;     /* timer 3 mode reg         */
 215    volatile unsigned short     timer_tmr4;     /* timer 4 mode reg         */
 216    volatile unsigned short     timer_trr3;     /* timer 3 referance reg    */
 217    volatile unsigned short     timer_trr4;     /* timer 4 referance reg    */
 218    volatile unsigned short     timer_tcr3;     /* timer 3 capture reg      */
 219    volatile unsigned short     timer_tcr4;     /* timer 4 capture reg      */
 220    volatile unsigned short     timer_tcn3;     /* timer 3 counter reg      */
 221    volatile unsigned short     timer_tcn4;     /* timer 4 counter reg      */
 222    volatile unsigned short     timer_ter1;     /* timer 1 event reg        */
 223    volatile unsigned short     timer_ter2;     /* timer 2 event reg        */
 224    volatile unsigned short     timer_ter3;     /* timer 3 event reg        */
 225    volatile unsigned short     timer_ter4;     /* timer 4 event reg        */
 226    volatile unsigned char      RESERVED34[0x8];        /* Reserved area    */
 227    /* CP */
 228    volatile unsigned short     cp_cr;          /* command register         */
 229    volatile unsigned char      RESERVED35[0x2];        /* Reserved area    */
 230    volatile unsigned short     cp_rccr;        /* main configuration reg   */
 231    volatile unsigned char      RESERVED37;     /* Reserved area            */
 232    volatile unsigned char      cp_rmds;        /* development support status reg */
 233    volatile unsigned long      cp_rmdr;        /* development support control reg */
 234    volatile unsigned short     cp_rctr1;       /* ram break register 1     */
 235    volatile unsigned short     cp_rctr2;       /* ram break register 2     */
 236    volatile unsigned short     cp_rctr3;       /* ram break register 3     */
 237    volatile unsigned short     cp_rctr4;       /* ram break register 4     */
 238    volatile unsigned char      RESERVED59[0x2];        /* Reserved area    */
 239    volatile unsigned short     cp_rter;        /* RISC timers event reg    */
 240    volatile unsigned char      RESERVED38[0x2];        /* Reserved area    */
 241    volatile unsigned short     cp_rtmr;        /* RISC timers mask reg     */
 242    volatile unsigned char      RESERVED39[0x14];       /* Reserved area    */
 243    /* BRG */
 244    union {
 245        volatile unsigned long l;
 246        struct {
 247            volatile unsigned short BRGC_RESERV:14;
 248            volatile unsigned short rst:1;
 249            volatile unsigned short en:1;
 250            volatile unsigned short extc:2;
 251            volatile unsigned short atb:1;
 252            volatile unsigned short cd:12;
 253            volatile unsigned short div16:1;
 254        } b;
 255    } brgc[4];                                  /* BRG1-BRG4 configuration regs*/
 256    /* SCC registers */
 257    struct scc_regs {
 258        union {
 259            struct {
 260                /* Low word. */
 261                volatile unsigned short GSMR_RESERV2:1;
 262                volatile unsigned short edge:2;
 263                volatile unsigned short tci:1;
 264                volatile unsigned short tsnc:2;
 265                volatile unsigned short rinv:1;
 266                volatile unsigned short tinv:1;
 267                volatile unsigned short tpl:3;
 268                volatile unsigned short tpp:2;
 269                volatile unsigned short tend:1;
 270                volatile unsigned short tdcr:2;
 271                volatile unsigned short rdcr:2;
 272                volatile unsigned short renc:3;
 273                volatile unsigned short tenc:3;
 274                volatile unsigned short diag:2;
 275                volatile unsigned short enr:1;
 276                volatile unsigned short ent:1;
 277                volatile unsigned short mode:4;
 278                /* High word. */
 279                volatile unsigned short GSMR_RESERV1:14;
 280                volatile unsigned short pri:1;
 281                volatile unsigned short gde:1;
 282                volatile unsigned short tcrc:2;
 283                volatile unsigned short revd:1;
 284                volatile unsigned short trx:1;
 285                volatile unsigned short ttx:1;
 286                volatile unsigned short cdp:1;
 287                volatile unsigned short ctsp:1;
 288                volatile unsigned short cds:1;
 289                volatile unsigned short ctss:1;
 290                volatile unsigned short tfl:1;
 291                volatile unsigned short rfw:1;
 292                volatile unsigned short txsy:1;
 293                volatile unsigned short synl:2;
 294                volatile unsigned short rtsm:1;
 295                volatile unsigned short rsyn:1;
 296            } b;
 297            struct {
 298                volatile unsigned long low;
 299                volatile unsigned long high;
 300            } w;
 301        } scc_gsmr;                         /* SCC general mode reg         */
 302        volatile unsigned short scc_psmr;   /* protocol specific mode reg   */
 303        volatile unsigned char  RESERVED42[0x2]; /* Reserved area           */
 304        volatile unsigned short scc_todr; /* SCC transmit on demand         */
 305        volatile unsigned short scc_dsr;        /* SCC data sync reg        */
 306        volatile unsigned short scc_scce;       /* SCC event reg            */
 307        volatile unsigned char  RESERVED43[0x2];/* Reserved area            */
 308        volatile unsigned short scc_sccm;       /* SCC mask reg             */
 309        volatile unsigned char  RESERVED44[0x1];/* Reserved area            */
 310        volatile unsigned char  scc_sccs;       /* SCC status reg           */
 311        volatile unsigned char  RESERVED45[0x8]; /* Reserved area           */
 312    } scc_regs[4];
 313    /* SMC */
 314    struct smc_regs {
 315        volatile unsigned char  RESERVED46[0x2]; /* Reserved area           */
 316        volatile unsigned short smc_smcmr;       /* SMC mode reg            */
 317        volatile unsigned char  RESERVED60[0x2]; /* Reserved area           */
 318        volatile unsigned char  smc_smce;        /* SMC event reg           */
 319        volatile unsigned char  RESERVED47[0x3]; /* Reserved area           */
 320        volatile unsigned char  smc_smcm;        /* SMC mask reg            */
 321        volatile unsigned char  RESERVED48[0x5]; /* Reserved area           */
 322    } smc_regs[2];
 323    /* SPI */
 324    volatile unsigned short     spi_spmode;     /* SPI mode reg             */
 325    volatile unsigned char      RESERVED51[0x4];        /* Reserved area    */
 326    volatile unsigned char      spi_spie;       /* SPI event reg            */
 327    volatile unsigned char      RESERVED52[0x3];        /* Reserved area    */
 328    volatile unsigned char      spi_spim;       /* SPI mask reg             */
 329    volatile unsigned char      RESERVED53[0x2];        /* Reserved area    */
 330    volatile unsigned char      spi_spcom;      /* SPI command reg          */
 331    volatile unsigned char      RESERVED54[0x4];        /* Reserved area    */
 332    /* PIP */
 333    volatile unsigned short     pip_pipc;       /* pip configuration reg    */
 334    volatile unsigned char      RESERVED65[0x2];        /* Reserved area    */
 335    volatile unsigned short     pip_ptpr;       /* pip timing parameters reg */
 336    volatile unsigned long      pip_pbdir;      /* port b data direction reg */
 337    volatile unsigned long      pip_pbpar;      /* port b pin assignment reg */
 338    volatile unsigned long      pip_pbodr;      /* port b open drain reg    */
 339    volatile unsigned long      pip_pbdat;      /* port b data reg          */
 340    volatile unsigned char      RESERVED71[0x18];       /* Reserved area    */
 341    /* Serial Interface */
 342    volatile unsigned long      si_simode;      /* SI mode register         */
 343    volatile unsigned char      si_sigmr;       /* SI global mode register  */
 344    volatile unsigned char      RESERVED55;     /* Reserved area            */
 345    volatile unsigned char      si_sistr;       /* SI status register       */
 346    volatile unsigned char      si_sicmr;       /* SI command register      */
 347    volatile unsigned char      RESERVED56[0x4]; /* Reserved area           */
 348    volatile unsigned long      si_sicr;        /* SI clock routing         */
 349    volatile unsigned long      si_sirp;        /* SI ram pointers          */
 350    volatile unsigned char      RESERVED57[0xc]; /* Reserved area           */
 351    volatile unsigned short     si_siram[0x80]; /* SI routing ram          */
 352} QUICC;
 353
 354#endif
 355
 356/*
 357 * Local variables:
 358 *  c-indent-level: 4
 359 *  c-basic-offset: 4
 360 *  tab-width: 4
 361 * End:
 362 */
 363