1/* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/* Machine-generated file; do not edit. */ 16 17 18#ifndef __ARCH_TRIO_SHM_H__ 19#define __ARCH_TRIO_SHM_H__ 20 21#include <arch/abi.h> 22#include <arch/trio_shm_def.h> 23 24#ifndef __ASSEMBLER__ 25/** 26 * TRIO DMA Descriptor. 27 * The TRIO DMA descriptor is written by software and consumed by hardware. 28 * It is used to specify the location of transaction data in the IO and Tile 29 * domains. 30 */ 31 32__extension__ 33typedef union 34{ 35 struct 36 { 37 /* Word 0 */ 38 39#ifndef __BIG_ENDIAN__ 40 /** Tile side virtual address. */ 41 int_reg_t va : 42; 42 /** 43 * Encoded size of buffer used on push DMA when C=1: 44 * 0 = 128 bytes 45 * 1 = 256 bytes 46 * 2 = 512 bytes 47 * 3 = 1024 bytes 48 * 4 = 1664 bytes 49 * 5 = 4096 bytes 50 * 6 = 10368 bytes 51 * 7 = 16384 bytes 52 */ 53 uint_reg_t bsz : 3; 54 /** 55 * Chaining designation. Always zero for pull DMA 56 * 0 : Unchained buffer pointer 57 * 1 : Chained buffer pointer. Next buffer descriptor (e.g. VA) stored 58 * in 1st 8-bytes in buffer. For chained buffers, first 8-bytes of each 59 * buffer contain the next buffer descriptor formatted exactly like a PDE 60 * buffer descriptor. This allows a chained PDE buffer to be sent using 61 * push DMA. 62 */ 63 uint_reg_t c : 1; 64 /** 65 * Notification interrupt will be delivered when the transaction has 66 * completed (all data has been read from or written to the Tile-side 67 * buffer). 68 */ 69 uint_reg_t notif : 1; 70 /** 71 * When 0, the XSIZE field specifies the total byte count for the 72 * transaction. When 1, the XSIZE field is encoded as 2^(N+14) for N in 73 * {0..6}: 74 * 0 = 16KB 75 * 1 = 32KB 76 * 2 = 64KB 77 * 3 = 128KB 78 * 4 = 256KB 79 * 5 = 512KB 80 * 6 = 1MB 81 * All other encodings of the XSIZE field are reserved when SMOD=1 82 */ 83 uint_reg_t smod : 1; 84 /** 85 * Total number of bytes to move for this transaction. When SMOD=1, 86 * this field is encoded - see SMOD description. 87 */ 88 uint_reg_t xsize : 14; 89 /** Reserved. */ 90 uint_reg_t __reserved_0 : 1; 91 /** 92 * Generation number. Used to indicate a valid descriptor in ring. When 93 * a new descriptor is written into the ring, software must toggle this 94 * bit. The net effect is that the GEN bit being written into new 95 * descriptors toggles each time the ring tail pointer wraps. 96 */ 97 uint_reg_t gen : 1; 98#else /* __BIG_ENDIAN__ */ 99 uint_reg_t gen : 1; 100 uint_reg_t __reserved_0 : 1; 101 uint_reg_t xsize : 14; 102 uint_reg_t smod : 1; 103 uint_reg_t notif : 1; 104 uint_reg_t c : 1; 105 uint_reg_t bsz : 3; 106 int_reg_t va : 42; 107#endif 108 109 /* Word 1 */ 110 111#ifndef __BIG_ENDIAN__ 112 /** IO-side address */ 113 uint_reg_t io_address : 64; 114#else /* __BIG_ENDIAN__ */ 115 uint_reg_t io_address : 64; 116#endif 117 118 }; 119 120 /** Word access */ 121 uint_reg_t words[2]; 122} TRIO_DMA_DESC_t; 123#endif /* !defined(__ASSEMBLER__) */ 124 125#endif /* !defined(__ARCH_TRIO_SHM_H__) */ 126