linux/arch/x86/include/asm/qspinlock.h
<<
>>
Prefs
   1#ifndef _ASM_X86_QSPINLOCK_H
   2#define _ASM_X86_QSPINLOCK_H
   3
   4#include <asm/cpufeature.h>
   5#include <asm-generic/qspinlock_types.h>
   6#include <asm/paravirt.h>
   7
   8#define queued_spin_unlock queued_spin_unlock
   9/**
  10 * queued_spin_unlock - release a queued spinlock
  11 * @lock : Pointer to queued spinlock structure
  12 *
  13 * A smp_store_release() on the least-significant byte.
  14 */
  15static inline void native_queued_spin_unlock(struct qspinlock *lock)
  16{
  17        smp_store_release((u8 *)lock, 0);
  18}
  19
  20#ifdef CONFIG_PARAVIRT_SPINLOCKS
  21extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
  22extern void __pv_init_lock_hash(void);
  23extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
  24extern void __raw_callee_save___pv_queued_spin_unlock(struct qspinlock *lock);
  25
  26static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
  27{
  28        pv_queued_spin_lock_slowpath(lock, val);
  29}
  30
  31static inline void queued_spin_unlock(struct qspinlock *lock)
  32{
  33        pv_queued_spin_unlock(lock);
  34}
  35#else
  36static inline void queued_spin_unlock(struct qspinlock *lock)
  37{
  38        native_queued_spin_unlock(lock);
  39}
  40#endif
  41
  42#define virt_spin_lock virt_spin_lock
  43
  44/*
  45 * RHEL7 specific:
  46 * To provide backward compatibility with pre-7.4 kernel modules that
  47 * inlines the ticket spinlock unlock code. The virt_spin_lock() function
  48 * will have to recognize both a lock value of 0 or _Q_UNLOCKED_VAL as
  49 * being in an unlocked state.
  50 */
  51static inline bool virt_spin_lock(struct qspinlock *lock)
  52{
  53        int lockval;
  54
  55        if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
  56                return false;
  57
  58        /*
  59         * On hypervisors without PARAVIRT_SPINLOCKS support we fall
  60         * back to a Test-and-Set spinlock, because fair locks have
  61         * horrible lock 'holder' preemption issues.
  62         */
  63
  64        do {
  65                while ((lockval = atomic_read(&lock->val)) &&
  66                       (lockval != _Q_UNLOCKED_VAL))
  67                        cpu_relax();
  68        } while (atomic_cmpxchg(&lock->val, lockval, _Q_LOCKED_VAL) != lockval);
  69
  70        return true;
  71}
  72
  73#include <asm-generic/qspinlock.h>
  74
  75#endif /* _ASM_X86_QSPINLOCK_H */
  76