1#ifndef _ASM_X86_KVM_H
2#define _ASM_X86_KVM_H
3
4
5
6
7
8
9#include <linux/types.h>
10#include <linux/ioctl.h>
11
12#define DE_VECTOR 0
13#define DB_VECTOR 1
14#define BP_VECTOR 3
15#define OF_VECTOR 4
16#define BR_VECTOR 5
17#define UD_VECTOR 6
18#define NM_VECTOR 7
19#define DF_VECTOR 8
20#define TS_VECTOR 10
21#define NP_VECTOR 11
22#define SS_VECTOR 12
23#define GP_VECTOR 13
24#define PF_VECTOR 14
25#define MF_VECTOR 16
26#define AC_VECTOR 17
27#define MC_VECTOR 18
28
29
30#define __KVM_HAVE_PIT
31#define __KVM_HAVE_IOAPIC
32#define __KVM_HAVE_IRQ_LINE
33#define __KVM_HAVE_MSI
34#define __KVM_HAVE_USER_NMI
35#define __KVM_HAVE_GUEST_DEBUG
36#define __KVM_HAVE_MSIX
37#define __KVM_HAVE_MCE
38#define __KVM_HAVE_PIT_STATE2
39#define __KVM_HAVE_XEN_HVM
40#define __KVM_HAVE_VCPU_EVENTS
41#define __KVM_HAVE_DEBUGREGS
42#define __KVM_HAVE_XSAVE
43#define __KVM_HAVE_XCRS
44#define __KVM_HAVE_READONLY_MEM
45
46
47#define KVM_NR_INTERRUPTS 256
48
49struct kvm_memory_alias {
50 __u32 slot;
51 __u32 flags;
52 __u64 guest_phys_addr;
53 __u64 memory_size;
54 __u64 target_phys_addr;
55};
56
57
58struct kvm_pic_state {
59 __u8 last_irr;
60 __u8 irr;
61 __u8 imr;
62 __u8 isr;
63 __u8 priority_add;
64 __u8 irq_base;
65 __u8 read_reg_select;
66 __u8 poll;
67 __u8 special_mask;
68 __u8 init_state;
69 __u8 auto_eoi;
70 __u8 rotate_on_auto_eoi;
71 __u8 special_fully_nested_mode;
72 __u8 init4;
73 __u8 elcr;
74 __u8 elcr_mask;
75};
76
77#define KVM_IOAPIC_NUM_PINS 24
78struct kvm_ioapic_state {
79 __u64 base_address;
80 __u32 ioregsel;
81 __u32 id;
82 __u32 irr;
83 __u32 pad;
84 union {
85 __u64 bits;
86 struct {
87 __u8 vector;
88 __u8 delivery_mode:3;
89 __u8 dest_mode:1;
90 __u8 delivery_status:1;
91 __u8 polarity:1;
92 __u8 remote_irr:1;
93 __u8 trig_mode:1;
94 __u8 mask:1;
95 __u8 reserve:7;
96 __u8 reserved[4];
97 __u8 dest_id;
98 } fields;
99 } redirtbl[KVM_IOAPIC_NUM_PINS];
100};
101
102#define KVM_IRQCHIP_PIC_MASTER 0
103#define KVM_IRQCHIP_PIC_SLAVE 1
104#define KVM_IRQCHIP_IOAPIC 2
105#define KVM_NR_IRQCHIPS 3
106
107#define KVM_RUN_X86_SMM (1 << 0)
108
109
110struct kvm_regs {
111
112 __u64 rax, rbx, rcx, rdx;
113 __u64 rsi, rdi, rsp, rbp;
114 __u64 r8, r9, r10, r11;
115 __u64 r12, r13, r14, r15;
116 __u64 rip, rflags;
117};
118
119
120#define KVM_APIC_REG_SIZE 0x400
121struct kvm_lapic_state {
122 char regs[KVM_APIC_REG_SIZE];
123};
124
125struct kvm_segment {
126 __u64 base;
127 __u32 limit;
128 __u16 selector;
129 __u8 type;
130 __u8 present, dpl, db, s, l, g, avl;
131 __u8 unusable;
132 __u8 padding;
133};
134
135struct kvm_dtable {
136 __u64 base;
137 __u16 limit;
138 __u16 padding[3];
139};
140
141
142
143struct kvm_sregs {
144
145 struct kvm_segment cs, ds, es, fs, gs, ss;
146 struct kvm_segment tr, ldt;
147 struct kvm_dtable gdt, idt;
148 __u64 cr0, cr2, cr3, cr4, cr8;
149 __u64 efer;
150 __u64 apic_base;
151 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
152};
153
154
155struct kvm_fpu {
156 __u8 fpr[8][16];
157 __u16 fcw;
158 __u16 fsw;
159 __u8 ftwx;
160 __u8 pad1;
161 __u16 last_opcode;
162 __u64 last_ip;
163 __u64 last_dp;
164 __u8 xmm[16][16];
165 __u32 mxcsr;
166 __u32 pad2;
167};
168
169struct kvm_msr_entry {
170 __u32 index;
171 __u32 reserved;
172 __u64 data;
173};
174
175
176struct kvm_msrs {
177 __u32 nmsrs;
178 __u32 pad;
179
180 struct kvm_msr_entry entries[0];
181};
182
183
184struct kvm_msr_list {
185 __u32 nmsrs;
186 __u32 indices[0];
187};
188
189
190struct kvm_cpuid_entry {
191 __u32 function;
192 __u32 eax;
193 __u32 ebx;
194 __u32 ecx;
195 __u32 edx;
196 __u32 padding;
197};
198
199
200struct kvm_cpuid {
201 __u32 nent;
202 __u32 padding;
203 struct kvm_cpuid_entry entries[0];
204};
205
206struct kvm_cpuid_entry2 {
207 __u32 function;
208 __u32 index;
209 __u32 flags;
210 __u32 eax;
211 __u32 ebx;
212 __u32 ecx;
213 __u32 edx;
214 __u32 padding[3];
215};
216
217#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0)
218#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1)
219#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2)
220
221
222struct kvm_cpuid2 {
223 __u32 nent;
224 __u32 padding;
225 struct kvm_cpuid_entry2 entries[0];
226};
227
228
229struct kvm_pit_channel_state {
230 __u32 count;
231 __u16 latched_count;
232 __u8 count_latched;
233 __u8 status_latched;
234 __u8 status;
235 __u8 read_state;
236 __u8 write_state;
237 __u8 write_latch;
238 __u8 rw_mode;
239 __u8 mode;
240 __u8 bcd;
241 __u8 gate;
242 __s64 count_load_time;
243};
244
245struct kvm_debug_exit_arch {
246 __u32 exception;
247 __u32 pad;
248 __u64 pc;
249 __u64 dr6;
250 __u64 dr7;
251};
252
253#define KVM_GUESTDBG_USE_SW_BP 0x00010000
254#define KVM_GUESTDBG_USE_HW_BP 0x00020000
255#define KVM_GUESTDBG_INJECT_DB 0x00040000
256#define KVM_GUESTDBG_INJECT_BP 0x00080000
257
258
259struct kvm_guest_debug_arch {
260 __u64 debugreg[8];
261};
262
263struct kvm_pit_state {
264 struct kvm_pit_channel_state channels[3];
265};
266
267#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
268
269struct kvm_pit_state2 {
270 struct kvm_pit_channel_state channels[3];
271 __u32 flags;
272 __u32 reserved[9];
273};
274
275struct kvm_reinject_control {
276 __u8 pit_reinject;
277 __u8 reserved[31];
278};
279
280
281#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
282#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
283#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
284#define KVM_VCPUEVENT_VALID_SMM 0x00000008
285
286
287#define KVM_X86_SHADOW_INT_MOV_SS 0x01
288#define KVM_X86_SHADOW_INT_STI 0x02
289
290
291struct kvm_vcpu_events {
292 struct {
293 __u8 injected;
294 __u8 nr;
295 __u8 has_error_code;
296 __u8 pad;
297 __u32 error_code;
298 } exception;
299 struct {
300 __u8 injected;
301 __u8 nr;
302 __u8 soft;
303 __u8 shadow;
304 } interrupt;
305 struct {
306 __u8 injected;
307 __u8 pending;
308 __u8 masked;
309 __u8 pad;
310 } nmi;
311 __u32 sipi_vector;
312 __u32 flags;
313 struct {
314 __u8 smm;
315 __u8 pending;
316 __u8 smm_inside_nmi;
317 __u8 latched_init;
318 } smi;
319 __u32 reserved[9];
320};
321
322
323struct kvm_debugregs {
324 __u64 db[4];
325 __u64 dr6;
326 __u64 dr7;
327 __u64 flags;
328 __u64 reserved[9];
329};
330
331
332struct kvm_xsave {
333 __u32 region[1024];
334};
335
336#define KVM_MAX_XCRS 16
337
338struct kvm_xcr {
339 __u32 xcr;
340 __u32 reserved;
341 __u64 value;
342};
343
344struct kvm_xcrs {
345 __u32 nr_xcrs;
346 __u32 flags;
347 struct kvm_xcr xcrs[KVM_MAX_XCRS];
348 __u64 padding[16];
349};
350
351
352struct kvm_sync_regs {
353};
354
355#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
356#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
357#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
358
359#endif
360