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13#include <asm/unaligned.h>
14
15#include <drm/drmP.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19#include <drm/drm_atomic_helper.h>
20
21#include <linux/clk.h>
22#include <linux/gpio/consumer.h>
23#include <linux/irq.h>
24#include <linux/of_device.h>
25#include <linux/of_gpio.h>
26#include <linux/of_graph.h>
27#include <linux/phy/phy.h>
28#include <linux/regulator/consumer.h>
29#include <linux/component.h>
30
31#include <video/mipi_display.h>
32#include <video/videomode.h>
33
34#include "exynos_drm_crtc.h"
35#include "exynos_drm_drv.h"
36
37
38#define NEQV(a, b) (!(a) ^ !(b))
39
40
41#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
42#define DSIM_STOP_STATE_CLK (1 << 8)
43#define DSIM_TX_READY_HS_CLK (1 << 10)
44#define DSIM_PLL_STABLE (1 << 31)
45
46
47#define DSIM_FUNCRST (1 << 16)
48#define DSIM_SWRST (1 << 0)
49
50
51#define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
52#define DSIM_BTA_TIMEOUT(x) ((x) << 16)
53
54
55#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
56#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
57#define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
58#define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
59#define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
60#define DSIM_BYTE_CLKEN (1 << 24)
61#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
62#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
63#define DSIM_PLL_BYPASS (1 << 27)
64#define DSIM_ESC_CLKEN (1 << 28)
65#define DSIM_TX_REQUEST_HSCLK (1 << 31)
66
67
68#define DSIM_LANE_EN_CLK (1 << 0)
69#define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
70#define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
71#define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
72#define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
73#define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
74#define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
75#define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
76#define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
77#define DSIM_SUB_VC (((x) & 0x3) << 16)
78#define DSIM_MAIN_VC (((x) & 0x3) << 18)
79#define DSIM_HSA_MODE (1 << 20)
80#define DSIM_HBP_MODE (1 << 21)
81#define DSIM_HFP_MODE (1 << 22)
82#define DSIM_HSE_MODE (1 << 23)
83#define DSIM_AUTO_MODE (1 << 24)
84#define DSIM_VIDEO_MODE (1 << 25)
85#define DSIM_BURST_MODE (1 << 26)
86#define DSIM_SYNC_INFORM (1 << 27)
87#define DSIM_EOT_DISABLE (1 << 28)
88#define DSIM_MFLUSH_VS (1 << 29)
89
90#define DSIM_CLKLANE_STOP (1 << 30)
91
92
93#define DSIM_TX_TRIGGER_RST (1 << 4)
94#define DSIM_TX_LPDT_LP (1 << 6)
95#define DSIM_CMD_LPDT_LP (1 << 7)
96#define DSIM_FORCE_BTA (1 << 16)
97#define DSIM_FORCE_STOP_STATE (1 << 20)
98#define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
99#define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
100
101
102#define DSIM_MAIN_STAND_BY (1 << 31)
103#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
104#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
105
106
107#define DSIM_CMD_ALLOW(x) ((x) << 28)
108#define DSIM_STABLE_VFP(x) ((x) << 16)
109#define DSIM_MAIN_VBP(x) ((x) << 0)
110#define DSIM_CMD_ALLOW_MASK (0xf << 28)
111#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
112#define DSIM_MAIN_VBP_MASK (0x7ff << 0)
113
114
115#define DSIM_MAIN_HFP(x) ((x) << 16)
116#define DSIM_MAIN_HBP(x) ((x) << 0)
117#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
118#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
119
120
121#define DSIM_MAIN_VSA(x) ((x) << 22)
122#define DSIM_MAIN_HSA(x) ((x) << 0)
123#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
124#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
125
126
127#define DSIM_SUB_STANDY(x) ((x) << 31)
128#define DSIM_SUB_VRESOL(x) ((x) << 16)
129#define DSIM_SUB_HRESOL(x) ((x) << 0)
130#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
131#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
132#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
133
134
135#define DSIM_INT_PLL_STABLE (1 << 31)
136#define DSIM_INT_SW_RST_RELEASE (1 << 30)
137#define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
138#define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
139#define DSIM_INT_BTA (1 << 25)
140#define DSIM_INT_FRAME_DONE (1 << 24)
141#define DSIM_INT_RX_TIMEOUT (1 << 21)
142#define DSIM_INT_BTA_TIMEOUT (1 << 20)
143#define DSIM_INT_RX_DONE (1 << 18)
144#define DSIM_INT_RX_TE (1 << 17)
145#define DSIM_INT_RX_ACK (1 << 16)
146#define DSIM_INT_RX_ECC_ERR (1 << 15)
147#define DSIM_INT_RX_CRC_ERR (1 << 14)
148
149
150#define DSIM_RX_DATA_FULL (1 << 25)
151#define DSIM_RX_DATA_EMPTY (1 << 24)
152#define DSIM_SFR_HEADER_FULL (1 << 23)
153#define DSIM_SFR_HEADER_EMPTY (1 << 22)
154#define DSIM_SFR_PAYLOAD_FULL (1 << 21)
155#define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
156#define DSIM_I80_HEADER_FULL (1 << 19)
157#define DSIM_I80_HEADER_EMPTY (1 << 18)
158#define DSIM_I80_PAYLOAD_FULL (1 << 17)
159#define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
160#define DSIM_SD_HEADER_FULL (1 << 15)
161#define DSIM_SD_HEADER_EMPTY (1 << 14)
162#define DSIM_SD_PAYLOAD_FULL (1 << 13)
163#define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
164#define DSIM_MD_HEADER_FULL (1 << 11)
165#define DSIM_MD_HEADER_EMPTY (1 << 10)
166#define DSIM_MD_PAYLOAD_FULL (1 << 9)
167#define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
168#define DSIM_RX_FIFO (1 << 4)
169#define DSIM_SFR_FIFO (1 << 3)
170#define DSIM_I80_FIFO (1 << 2)
171#define DSIM_SD_FIFO (1 << 1)
172#define DSIM_MD_FIFO (1 << 0)
173
174
175#define DSIM_AFC_EN (1 << 14)
176#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
177
178
179#define DSIM_FREQ_BAND(x) ((x) << 24)
180#define DSIM_PLL_EN (1 << 23)
181#define DSIM_PLL_P(x) ((x) << 13)
182#define DSIM_PLL_M(x) ((x) << 4)
183#define DSIM_PLL_S(x) ((x) << 1)
184
185
186#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
187#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
188#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
189
190
191#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
192#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
193
194
195#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
196#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
197#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
198#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
199
200
201#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
202#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
203#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
204
205#define DSI_MAX_BUS_WIDTH 4
206#define DSI_NUM_VIRTUAL_CHANNELS 4
207#define DSI_TX_FIFO_SIZE 2048
208#define DSI_RX_FIFO_SIZE 256
209#define DSI_XFER_TIMEOUT_MS 100
210#define DSI_RX_FIFO_EMPTY 0x30800002
211
212#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
213
214static char *clk_names[5] = { "bus_clk", "sclk_mipi",
215 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
216 "sclk_rgb_vclk_to_dsim0" };
217
218enum exynos_dsi_transfer_type {
219 EXYNOS_DSI_TX,
220 EXYNOS_DSI_RX,
221};
222
223struct exynos_dsi_transfer {
224 struct list_head list;
225 struct completion completed;
226 int result;
227 struct mipi_dsi_packet packet;
228 u16 flags;
229 u16 tx_done;
230
231 u8 *rx_payload;
232 u16 rx_len;
233 u16 rx_done;
234};
235
236#define DSIM_STATE_ENABLED BIT(0)
237#define DSIM_STATE_INITIALIZED BIT(1)
238#define DSIM_STATE_CMD_LPM BIT(2)
239#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
240
241struct exynos_dsi_driver_data {
242 const unsigned int *reg_ofs;
243 unsigned int plltmr_reg;
244 unsigned int has_freqband:1;
245 unsigned int has_clklane_stop:1;
246 unsigned int num_clks;
247 unsigned int max_freq;
248 unsigned int wait_for_reset;
249 unsigned int num_bits_resol;
250 const unsigned int *reg_values;
251};
252
253struct exynos_dsi {
254 struct drm_encoder encoder;
255 struct mipi_dsi_host dsi_host;
256 struct drm_connector connector;
257 struct drm_panel *panel;
258 struct device *dev;
259
260 void __iomem *reg_base;
261 struct phy *phy;
262 struct clk **clks;
263 struct regulator_bulk_data supplies[2];
264 int irq;
265 int te_gpio;
266
267 u32 pll_clk_rate;
268 u32 burst_clk_rate;
269 u32 esc_clk_rate;
270 u32 lanes;
271 u32 mode_flags;
272 u32 format;
273 struct videomode vm;
274
275 int state;
276 struct drm_property *brightness;
277 struct completion completed;
278
279 spinlock_t transfer_lock;
280 struct list_head transfer_list;
281
282 const struct exynos_dsi_driver_data *driver_data;
283 struct device_node *bridge_node;
284};
285
286#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
287#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
288
289static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
290{
291 return container_of(e, struct exynos_dsi, encoder);
292}
293
294enum reg_idx {
295 DSIM_STATUS_REG,
296 DSIM_SWRST_REG,
297 DSIM_CLKCTRL_REG,
298 DSIM_TIMEOUT_REG,
299 DSIM_CONFIG_REG,
300 DSIM_ESCMODE_REG,
301 DSIM_MDRESOL_REG,
302 DSIM_MVPORCH_REG,
303 DSIM_MHPORCH_REG,
304 DSIM_MSYNC_REG,
305 DSIM_INTSRC_REG,
306 DSIM_INTMSK_REG,
307 DSIM_PKTHDR_REG,
308 DSIM_PAYLOAD_REG,
309 DSIM_RXFIFO_REG,
310 DSIM_FIFOCTRL_REG,
311 DSIM_PLLCTRL_REG,
312 DSIM_PHYCTRL_REG,
313 DSIM_PHYTIMING_REG,
314 DSIM_PHYTIMING1_REG,
315 DSIM_PHYTIMING2_REG,
316 NUM_REGS
317};
318
319static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
320 u32 val)
321{
322
323 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
324}
325
326static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
327{
328 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
329}
330
331static const unsigned int exynos_reg_ofs[] = {
332 [DSIM_STATUS_REG] = 0x00,
333 [DSIM_SWRST_REG] = 0x04,
334 [DSIM_CLKCTRL_REG] = 0x08,
335 [DSIM_TIMEOUT_REG] = 0x0c,
336 [DSIM_CONFIG_REG] = 0x10,
337 [DSIM_ESCMODE_REG] = 0x14,
338 [DSIM_MDRESOL_REG] = 0x18,
339 [DSIM_MVPORCH_REG] = 0x1c,
340 [DSIM_MHPORCH_REG] = 0x20,
341 [DSIM_MSYNC_REG] = 0x24,
342 [DSIM_INTSRC_REG] = 0x2c,
343 [DSIM_INTMSK_REG] = 0x30,
344 [DSIM_PKTHDR_REG] = 0x34,
345 [DSIM_PAYLOAD_REG] = 0x38,
346 [DSIM_RXFIFO_REG] = 0x3c,
347 [DSIM_FIFOCTRL_REG] = 0x44,
348 [DSIM_PLLCTRL_REG] = 0x4c,
349 [DSIM_PHYCTRL_REG] = 0x5c,
350 [DSIM_PHYTIMING_REG] = 0x64,
351 [DSIM_PHYTIMING1_REG] = 0x68,
352 [DSIM_PHYTIMING2_REG] = 0x6c,
353};
354
355static const unsigned int exynos5433_reg_ofs[] = {
356 [DSIM_STATUS_REG] = 0x04,
357 [DSIM_SWRST_REG] = 0x0C,
358 [DSIM_CLKCTRL_REG] = 0x10,
359 [DSIM_TIMEOUT_REG] = 0x14,
360 [DSIM_CONFIG_REG] = 0x18,
361 [DSIM_ESCMODE_REG] = 0x1C,
362 [DSIM_MDRESOL_REG] = 0x20,
363 [DSIM_MVPORCH_REG] = 0x24,
364 [DSIM_MHPORCH_REG] = 0x28,
365 [DSIM_MSYNC_REG] = 0x2C,
366 [DSIM_INTSRC_REG] = 0x34,
367 [DSIM_INTMSK_REG] = 0x38,
368 [DSIM_PKTHDR_REG] = 0x3C,
369 [DSIM_PAYLOAD_REG] = 0x40,
370 [DSIM_RXFIFO_REG] = 0x44,
371 [DSIM_FIFOCTRL_REG] = 0x4C,
372 [DSIM_PLLCTRL_REG] = 0x94,
373 [DSIM_PHYCTRL_REG] = 0xA4,
374 [DSIM_PHYTIMING_REG] = 0xB4,
375 [DSIM_PHYTIMING1_REG] = 0xB8,
376 [DSIM_PHYTIMING2_REG] = 0xBC,
377};
378
379enum reg_value_idx {
380 RESET_TYPE,
381 PLL_TIMER,
382 STOP_STATE_CNT,
383 PHYCTRL_ULPS_EXIT,
384 PHYCTRL_VREG_LP,
385 PHYCTRL_SLEW_UP,
386 PHYTIMING_LPX,
387 PHYTIMING_HS_EXIT,
388 PHYTIMING_CLK_PREPARE,
389 PHYTIMING_CLK_ZERO,
390 PHYTIMING_CLK_POST,
391 PHYTIMING_CLK_TRAIL,
392 PHYTIMING_HS_PREPARE,
393 PHYTIMING_HS_ZERO,
394 PHYTIMING_HS_TRAIL
395};
396
397static const unsigned int reg_values[] = {
398 [RESET_TYPE] = DSIM_SWRST,
399 [PLL_TIMER] = 500,
400 [STOP_STATE_CNT] = 0xf,
401 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
402 [PHYCTRL_VREG_LP] = 0,
403 [PHYCTRL_SLEW_UP] = 0,
404 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
405 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
406 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
407 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
408 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
409 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
410 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
411 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
412 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
413};
414
415static const unsigned int exynos5422_reg_values[] = {
416 [RESET_TYPE] = DSIM_SWRST,
417 [PLL_TIMER] = 500,
418 [STOP_STATE_CNT] = 0xf,
419 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
420 [PHYCTRL_VREG_LP] = 0,
421 [PHYCTRL_SLEW_UP] = 0,
422 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
423 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
424 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
425 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
426 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
427 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
428 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
429 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
430 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
431};
432
433static const unsigned int exynos5433_reg_values[] = {
434 [RESET_TYPE] = DSIM_FUNCRST,
435 [PLL_TIMER] = 22200,
436 [STOP_STATE_CNT] = 0xa,
437 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
438 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
439 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
440 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
441 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
442 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
443 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
444 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
445 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
446 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
447 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
448 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
449};
450
451static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
452 .reg_ofs = exynos_reg_ofs,
453 .plltmr_reg = 0x50,
454 .has_freqband = 1,
455 .has_clklane_stop = 1,
456 .num_clks = 2,
457 .max_freq = 1000,
458 .wait_for_reset = 1,
459 .num_bits_resol = 11,
460 .reg_values = reg_values,
461};
462
463static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
464 .reg_ofs = exynos_reg_ofs,
465 .plltmr_reg = 0x50,
466 .has_freqband = 1,
467 .has_clklane_stop = 1,
468 .num_clks = 2,
469 .max_freq = 1000,
470 .wait_for_reset = 1,
471 .num_bits_resol = 11,
472 .reg_values = reg_values,
473};
474
475static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
476 .reg_ofs = exynos_reg_ofs,
477 .plltmr_reg = 0x58,
478 .num_clks = 2,
479 .max_freq = 1000,
480 .wait_for_reset = 1,
481 .num_bits_resol = 11,
482 .reg_values = reg_values,
483};
484
485static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
486 .reg_ofs = exynos5433_reg_ofs,
487 .plltmr_reg = 0xa0,
488 .has_clklane_stop = 1,
489 .num_clks = 5,
490 .max_freq = 1500,
491 .wait_for_reset = 0,
492 .num_bits_resol = 12,
493 .reg_values = exynos5433_reg_values,
494};
495
496static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
497 .reg_ofs = exynos5433_reg_ofs,
498 .plltmr_reg = 0xa0,
499 .has_clklane_stop = 1,
500 .num_clks = 2,
501 .max_freq = 1500,
502 .wait_for_reset = 1,
503 .num_bits_resol = 12,
504 .reg_values = exynos5422_reg_values,
505};
506
507static const struct of_device_id exynos_dsi_of_match[] = {
508 { .compatible = "samsung,exynos3250-mipi-dsi",
509 .data = &exynos3_dsi_driver_data },
510 { .compatible = "samsung,exynos4210-mipi-dsi",
511 .data = &exynos4_dsi_driver_data },
512 { .compatible = "samsung,exynos5410-mipi-dsi",
513 .data = &exynos5_dsi_driver_data },
514 { .compatible = "samsung,exynos5422-mipi-dsi",
515 .data = &exynos5422_dsi_driver_data },
516 { .compatible = "samsung,exynos5433-mipi-dsi",
517 .data = &exynos5433_dsi_driver_data },
518 { }
519};
520
521static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
522{
523 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
524 return;
525
526 dev_err(dsi->dev, "timeout waiting for reset\n");
527}
528
529static void exynos_dsi_reset(struct exynos_dsi *dsi)
530{
531 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
532
533 reinit_completion(&dsi->completed);
534 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
535}
536
537#ifndef MHZ
538#define MHZ (1000*1000)
539#endif
540
541static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
542 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
543{
544 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
545 unsigned long best_freq = 0;
546 u32 min_delta = 0xffffffff;
547 u8 p_min, p_max;
548 u8 _p, uninitialized_var(best_p);
549 u16 _m, uninitialized_var(best_m);
550 u8 _s, uninitialized_var(best_s);
551
552 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
553 p_max = fin / (6 * MHZ);
554
555 for (_p = p_min; _p <= p_max; ++_p) {
556 for (_s = 0; _s <= 5; ++_s) {
557 u64 tmp;
558 u32 delta;
559
560 tmp = (u64)fout * (_p << _s);
561 do_div(tmp, fin);
562 _m = tmp;
563 if (_m < 41 || _m > 125)
564 continue;
565
566 tmp = (u64)_m * fin;
567 do_div(tmp, _p);
568 if (tmp < 500 * MHZ ||
569 tmp > driver_data->max_freq * MHZ)
570 continue;
571
572 tmp = (u64)_m * fin;
573 do_div(tmp, _p << _s);
574
575 delta = abs(fout - tmp);
576 if (delta < min_delta) {
577 best_p = _p;
578 best_m = _m;
579 best_s = _s;
580 min_delta = delta;
581 best_freq = tmp;
582 }
583 }
584 }
585
586 if (best_freq) {
587 *p = best_p;
588 *m = best_m;
589 *s = best_s;
590 }
591
592 return best_freq;
593}
594
595static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
596 unsigned long freq)
597{
598 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
599 unsigned long fin, fout;
600 int timeout;
601 u8 p, s;
602 u16 m;
603 u32 reg;
604
605 fin = dsi->pll_clk_rate;
606 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
607 if (!fout) {
608 dev_err(dsi->dev,
609 "failed to find PLL PMS for requested frequency\n");
610 return 0;
611 }
612 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
613
614 writel(driver_data->reg_values[PLL_TIMER],
615 dsi->reg_base + driver_data->plltmr_reg);
616
617 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
618
619 if (driver_data->has_freqband) {
620 static const unsigned long freq_bands[] = {
621 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
622 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
623 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
624 770 * MHZ, 870 * MHZ, 950 * MHZ,
625 };
626 int band;
627
628 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
629 if (fout < freq_bands[band])
630 break;
631
632 dev_dbg(dsi->dev, "band %d\n", band);
633
634 reg |= DSIM_FREQ_BAND(band);
635 }
636
637 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
638
639 timeout = 1000;
640 do {
641 if (timeout-- == 0) {
642 dev_err(dsi->dev, "PLL failed to stabilize\n");
643 return 0;
644 }
645 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
646 } while ((reg & DSIM_PLL_STABLE) == 0);
647
648 return fout;
649}
650
651static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
652{
653 unsigned long hs_clk, byte_clk, esc_clk;
654 unsigned long esc_div;
655 u32 reg;
656
657 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
658 if (!hs_clk) {
659 dev_err(dsi->dev, "failed to configure DSI PLL\n");
660 return -EFAULT;
661 }
662
663 byte_clk = hs_clk / 8;
664 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
665 esc_clk = byte_clk / esc_div;
666
667 if (esc_clk > 20 * MHZ) {
668 ++esc_div;
669 esc_clk = byte_clk / esc_div;
670 }
671
672 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
673 hs_clk, byte_clk, esc_clk);
674
675 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
676 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
677 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
678 | DSIM_BYTE_CLK_SRC_MASK);
679 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
680 | DSIM_ESC_PRESCALER(esc_div)
681 | DSIM_LANE_ESC_CLK_EN_CLK
682 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
683 | DSIM_BYTE_CLK_SRC(0)
684 | DSIM_TX_REQUEST_HSCLK;
685 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
686
687 return 0;
688}
689
690static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
691{
692 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
693 const unsigned int *reg_values = driver_data->reg_values;
694 u32 reg;
695
696 if (driver_data->has_freqband)
697 return;
698
699
700 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
701 reg_values[PHYCTRL_SLEW_UP];
702 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
703
704
705
706
707
708
709 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
710 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725 reg = reg_values[PHYTIMING_CLK_PREPARE] |
726 reg_values[PHYTIMING_CLK_ZERO] |
727 reg_values[PHYTIMING_CLK_POST] |
728 reg_values[PHYTIMING_CLK_TRAIL];
729
730 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
731
732
733
734
735
736
737
738
739
740
741 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
742 reg_values[PHYTIMING_HS_TRAIL];
743 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
744}
745
746static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
747{
748 u32 reg;
749
750 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
751 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
752 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
753 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
754
755 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
756 reg &= ~DSIM_PLL_EN;
757 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
758}
759
760static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
761{
762 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
763 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
764 DSIM_LANE_EN(lane));
765 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
766}
767
768static int exynos_dsi_init_link(struct exynos_dsi *dsi)
769{
770 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
771 int timeout;
772 u32 reg;
773 u32 lanes_mask;
774
775
776 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
777 reg &= ~0x1f;
778 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
779
780 usleep_range(9000, 11000);
781
782 reg |= 0x1f;
783 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
784 usleep_range(9000, 11000);
785
786
787 reg = 0;
788
789
790
791
792
793
794 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
795 reg |= DSIM_VIDEO_MODE;
796
797
798
799
800
801 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
802 reg |= DSIM_MFLUSH_VS;
803 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
804 reg |= DSIM_SYNC_INFORM;
805 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
806 reg |= DSIM_BURST_MODE;
807 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
808 reg |= DSIM_AUTO_MODE;
809 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
810 reg |= DSIM_HSE_MODE;
811 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
812 reg |= DSIM_HFP_MODE;
813 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
814 reg |= DSIM_HBP_MODE;
815 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
816 reg |= DSIM_HSA_MODE;
817 }
818
819 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
820 reg |= DSIM_EOT_DISABLE;
821
822 switch (dsi->format) {
823 case MIPI_DSI_FMT_RGB888:
824 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
825 break;
826 case MIPI_DSI_FMT_RGB666:
827 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
828 break;
829 case MIPI_DSI_FMT_RGB666_PACKED:
830 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
831 break;
832 case MIPI_DSI_FMT_RGB565:
833 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
834 break;
835 default:
836 dev_err(dsi->dev, "invalid pixel format\n");
837 return -EINVAL;
838 }
839
840
841
842
843
844
845
846
847
848 if (driver_data->has_clklane_stop &&
849 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
850 reg |= DSIM_CLKLANE_STOP;
851 }
852 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
853
854 lanes_mask = BIT(dsi->lanes) - 1;
855 exynos_dsi_enable_lane(dsi, lanes_mask);
856
857
858 timeout = 100;
859 do {
860 if (timeout-- == 0) {
861 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
862 return -EFAULT;
863 }
864
865 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
866 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
867 != DSIM_STOP_STATE_DAT(lanes_mask))
868 continue;
869 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
870
871 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
872 reg &= ~DSIM_STOP_STATE_CNT_MASK;
873 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
874 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
875
876 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
877 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
878
879 return 0;
880}
881
882static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
883{
884 struct videomode *vm = &dsi->vm;
885 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
886 u32 reg;
887
888 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
889 reg = DSIM_CMD_ALLOW(0xf)
890 | DSIM_STABLE_VFP(vm->vfront_porch)
891 | DSIM_MAIN_VBP(vm->vback_porch);
892 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
893
894 reg = DSIM_MAIN_HFP(vm->hfront_porch)
895 | DSIM_MAIN_HBP(vm->hback_porch);
896 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
897
898 reg = DSIM_MAIN_VSA(vm->vsync_len)
899 | DSIM_MAIN_HSA(vm->hsync_len);
900 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
901 }
902 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
903 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
904
905 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
906
907 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
908}
909
910static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
911{
912 u32 reg;
913
914 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
915 if (enable)
916 reg |= DSIM_MAIN_STAND_BY;
917 else
918 reg &= ~DSIM_MAIN_STAND_BY;
919 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
920}
921
922static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
923{
924 int timeout = 2000;
925
926 do {
927 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
928
929 if (!(reg & DSIM_SFR_HEADER_FULL))
930 return 0;
931
932 if (!cond_resched())
933 usleep_range(950, 1050);
934 } while (--timeout);
935
936 return -ETIMEDOUT;
937}
938
939static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
940{
941 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
942
943 if (lpm)
944 v |= DSIM_CMD_LPDT_LP;
945 else
946 v &= ~DSIM_CMD_LPDT_LP;
947
948 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
949}
950
951static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
952{
953 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
954 v |= DSIM_FORCE_BTA;
955 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
956}
957
958static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
959 struct exynos_dsi_transfer *xfer)
960{
961 struct device *dev = dsi->dev;
962 struct mipi_dsi_packet *pkt = &xfer->packet;
963 const u8 *payload = pkt->payload + xfer->tx_done;
964 u16 length = pkt->payload_length - xfer->tx_done;
965 bool first = !xfer->tx_done;
966 u32 reg;
967
968 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
969 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
970
971 if (length > DSI_TX_FIFO_SIZE)
972 length = DSI_TX_FIFO_SIZE;
973
974 xfer->tx_done += length;
975
976
977 while (length >= 4) {
978 reg = get_unaligned_le32(payload);
979 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
980 payload += 4;
981 length -= 4;
982 }
983
984 reg = 0;
985 switch (length) {
986 case 3:
987 reg |= payload[2] << 16;
988
989 case 2:
990 reg |= payload[1] << 8;
991
992 case 1:
993 reg |= payload[0];
994 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
995 break;
996 }
997
998
999 if (!first)
1000 return;
1001
1002 reg = get_unaligned_le32(pkt->header);
1003 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1004 dev_err(dev, "waiting for header FIFO timed out\n");
1005 return;
1006 }
1007
1008 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1009 dsi->state & DSIM_STATE_CMD_LPM)) {
1010 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1011 dsi->state ^= DSIM_STATE_CMD_LPM;
1012 }
1013
1014 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1015
1016 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1017 exynos_dsi_force_bta(dsi);
1018}
1019
1020static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1021 struct exynos_dsi_transfer *xfer)
1022{
1023 u8 *payload = xfer->rx_payload + xfer->rx_done;
1024 bool first = !xfer->rx_done;
1025 struct device *dev = dsi->dev;
1026 u16 length;
1027 u32 reg;
1028
1029 if (first) {
1030 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1031
1032 switch (reg & 0x3f) {
1033 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1034 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1035 if (xfer->rx_len >= 2) {
1036 payload[1] = reg >> 16;
1037 ++xfer->rx_done;
1038 }
1039
1040 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1041 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1042 payload[0] = reg >> 8;
1043 ++xfer->rx_done;
1044 xfer->rx_len = xfer->rx_done;
1045 xfer->result = 0;
1046 goto clear_fifo;
1047 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1048 dev_err(dev, "DSI Error Report: 0x%04x\n",
1049 (reg >> 8) & 0xffff);
1050 xfer->result = 0;
1051 goto clear_fifo;
1052 }
1053
1054 length = (reg >> 8) & 0xffff;
1055 if (length > xfer->rx_len) {
1056 dev_err(dev,
1057 "response too long (%u > %u bytes), stripping\n",
1058 xfer->rx_len, length);
1059 length = xfer->rx_len;
1060 } else if (length < xfer->rx_len)
1061 xfer->rx_len = length;
1062 }
1063
1064 length = xfer->rx_len - xfer->rx_done;
1065 xfer->rx_done += length;
1066
1067
1068 while (length >= 4) {
1069 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1070 payload[0] = (reg >> 0) & 0xff;
1071 payload[1] = (reg >> 8) & 0xff;
1072 payload[2] = (reg >> 16) & 0xff;
1073 payload[3] = (reg >> 24) & 0xff;
1074 payload += 4;
1075 length -= 4;
1076 }
1077
1078 if (length) {
1079 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1080 switch (length) {
1081 case 3:
1082 payload[2] = (reg >> 16) & 0xff;
1083
1084 case 2:
1085 payload[1] = (reg >> 8) & 0xff;
1086
1087 case 1:
1088 payload[0] = reg & 0xff;
1089 }
1090 }
1091
1092 if (xfer->rx_done == xfer->rx_len)
1093 xfer->result = 0;
1094
1095clear_fifo:
1096 length = DSI_RX_FIFO_SIZE / 4;
1097 do {
1098 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1099 if (reg == DSI_RX_FIFO_EMPTY)
1100 break;
1101 } while (--length);
1102}
1103
1104static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1105{
1106 unsigned long flags;
1107 struct exynos_dsi_transfer *xfer;
1108 bool start = false;
1109
1110again:
1111 spin_lock_irqsave(&dsi->transfer_lock, flags);
1112
1113 if (list_empty(&dsi->transfer_list)) {
1114 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1115 return;
1116 }
1117
1118 xfer = list_first_entry(&dsi->transfer_list,
1119 struct exynos_dsi_transfer, list);
1120
1121 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1122
1123 if (xfer->packet.payload_length &&
1124 xfer->tx_done == xfer->packet.payload_length)
1125
1126 return;
1127
1128 exynos_dsi_send_to_fifo(dsi, xfer);
1129
1130 if (xfer->packet.payload_length || xfer->rx_len)
1131 return;
1132
1133 xfer->result = 0;
1134 complete(&xfer->completed);
1135
1136 spin_lock_irqsave(&dsi->transfer_lock, flags);
1137
1138 list_del_init(&xfer->list);
1139 start = !list_empty(&dsi->transfer_list);
1140
1141 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1142
1143 if (start)
1144 goto again;
1145}
1146
1147static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1148{
1149 struct exynos_dsi_transfer *xfer;
1150 unsigned long flags;
1151 bool start = true;
1152
1153 spin_lock_irqsave(&dsi->transfer_lock, flags);
1154
1155 if (list_empty(&dsi->transfer_list)) {
1156 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1157 return false;
1158 }
1159
1160 xfer = list_first_entry(&dsi->transfer_list,
1161 struct exynos_dsi_transfer, list);
1162
1163 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1164
1165 dev_dbg(dsi->dev,
1166 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1167 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1168 xfer->rx_done);
1169
1170 if (xfer->tx_done != xfer->packet.payload_length)
1171 return true;
1172
1173 if (xfer->rx_done != xfer->rx_len)
1174 exynos_dsi_read_from_fifo(dsi, xfer);
1175
1176 if (xfer->rx_done != xfer->rx_len)
1177 return true;
1178
1179 spin_lock_irqsave(&dsi->transfer_lock, flags);
1180
1181 list_del_init(&xfer->list);
1182 start = !list_empty(&dsi->transfer_list);
1183
1184 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1185
1186 if (!xfer->rx_len)
1187 xfer->result = 0;
1188 complete(&xfer->completed);
1189
1190 return start;
1191}
1192
1193static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1194 struct exynos_dsi_transfer *xfer)
1195{
1196 unsigned long flags;
1197 bool start;
1198
1199 spin_lock_irqsave(&dsi->transfer_lock, flags);
1200
1201 if (!list_empty(&dsi->transfer_list) &&
1202 xfer == list_first_entry(&dsi->transfer_list,
1203 struct exynos_dsi_transfer, list)) {
1204 list_del_init(&xfer->list);
1205 start = !list_empty(&dsi->transfer_list);
1206 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1207 if (start)
1208 exynos_dsi_transfer_start(dsi);
1209 return;
1210 }
1211
1212 list_del_init(&xfer->list);
1213
1214 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1215}
1216
1217static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1218 struct exynos_dsi_transfer *xfer)
1219{
1220 unsigned long flags;
1221 bool stopped;
1222
1223 xfer->tx_done = 0;
1224 xfer->rx_done = 0;
1225 xfer->result = -ETIMEDOUT;
1226 init_completion(&xfer->completed);
1227
1228 spin_lock_irqsave(&dsi->transfer_lock, flags);
1229
1230 stopped = list_empty(&dsi->transfer_list);
1231 list_add_tail(&xfer->list, &dsi->transfer_list);
1232
1233 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1234
1235 if (stopped)
1236 exynos_dsi_transfer_start(dsi);
1237
1238 wait_for_completion_timeout(&xfer->completed,
1239 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1240 if (xfer->result == -ETIMEDOUT) {
1241 struct mipi_dsi_packet *pkt = &xfer->packet;
1242 exynos_dsi_remove_transfer(dsi, xfer);
1243 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1244 (int)pkt->payload_length, pkt->payload);
1245 return -ETIMEDOUT;
1246 }
1247
1248
1249 return xfer->result;
1250}
1251
1252static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1253{
1254 struct exynos_dsi *dsi = dev_id;
1255 u32 status;
1256
1257 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1258 if (!status) {
1259 static unsigned long int j;
1260 if (printk_timed_ratelimit(&j, 500))
1261 dev_warn(dsi->dev, "spurious interrupt\n");
1262 return IRQ_HANDLED;
1263 }
1264 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1265
1266 if (status & DSIM_INT_SW_RST_RELEASE) {
1267 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1268 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |
1269 DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);
1270 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1271 complete(&dsi->completed);
1272 return IRQ_HANDLED;
1273 }
1274
1275 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1276 DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))
1277 return IRQ_HANDLED;
1278
1279 if (exynos_dsi_transfer_finish(dsi))
1280 exynos_dsi_transfer_start(dsi);
1281
1282 return IRQ_HANDLED;
1283}
1284
1285static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1286{
1287 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1288 struct drm_encoder *encoder = &dsi->encoder;
1289
1290 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1291 exynos_drm_crtc_te_handler(encoder->crtc);
1292
1293 return IRQ_HANDLED;
1294}
1295
1296static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1297{
1298 enable_irq(dsi->irq);
1299
1300 if (gpio_is_valid(dsi->te_gpio))
1301 enable_irq(gpio_to_irq(dsi->te_gpio));
1302}
1303
1304static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1305{
1306 if (gpio_is_valid(dsi->te_gpio))
1307 disable_irq(gpio_to_irq(dsi->te_gpio));
1308
1309 disable_irq(dsi->irq);
1310}
1311
1312static int exynos_dsi_init(struct exynos_dsi *dsi)
1313{
1314 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1315
1316 exynos_dsi_reset(dsi);
1317 exynos_dsi_enable_irq(dsi);
1318
1319 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1320 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1321
1322 exynos_dsi_enable_clock(dsi);
1323 if (driver_data->wait_for_reset)
1324 exynos_dsi_wait_for_reset(dsi);
1325 exynos_dsi_set_phy_ctrl(dsi);
1326 exynos_dsi_init_link(dsi);
1327
1328 return 0;
1329}
1330
1331static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1332 struct device *panel)
1333{
1334 int ret;
1335 int te_gpio_irq;
1336
1337 dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
1338 if (dsi->te_gpio == -ENOENT)
1339 return 0;
1340
1341 if (!gpio_is_valid(dsi->te_gpio)) {
1342 ret = dsi->te_gpio;
1343 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1344 goto out;
1345 }
1346
1347 ret = gpio_request(dsi->te_gpio, "te_gpio");
1348 if (ret) {
1349 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1350 goto out;
1351 }
1352
1353 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1354 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1355
1356 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1357 IRQF_TRIGGER_RISING, "TE", dsi);
1358 if (ret) {
1359 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1360 gpio_free(dsi->te_gpio);
1361 goto out;
1362 }
1363
1364out:
1365 return ret;
1366}
1367
1368static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1369{
1370 if (gpio_is_valid(dsi->te_gpio)) {
1371 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1372 gpio_free(dsi->te_gpio);
1373 dsi->te_gpio = -ENOENT;
1374 }
1375}
1376
1377static void exynos_dsi_enable(struct drm_encoder *encoder)
1378{
1379 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1380 int ret;
1381
1382 if (dsi->state & DSIM_STATE_ENABLED)
1383 return;
1384
1385 pm_runtime_get_sync(dsi->dev);
1386
1387 dsi->state |= DSIM_STATE_ENABLED;
1388
1389 ret = drm_panel_prepare(dsi->panel);
1390 if (ret < 0) {
1391 dsi->state &= ~DSIM_STATE_ENABLED;
1392 pm_runtime_put_sync(dsi->dev);
1393 return;
1394 }
1395
1396 exynos_dsi_set_display_mode(dsi);
1397 exynos_dsi_set_display_enable(dsi, true);
1398
1399 ret = drm_panel_enable(dsi->panel);
1400 if (ret < 0) {
1401 dsi->state &= ~DSIM_STATE_ENABLED;
1402 exynos_dsi_set_display_enable(dsi, false);
1403 drm_panel_unprepare(dsi->panel);
1404 pm_runtime_put_sync(dsi->dev);
1405 return;
1406 }
1407
1408 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1409}
1410
1411static void exynos_dsi_disable(struct drm_encoder *encoder)
1412{
1413 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1414
1415 if (!(dsi->state & DSIM_STATE_ENABLED))
1416 return;
1417
1418 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1419
1420 drm_panel_disable(dsi->panel);
1421 exynos_dsi_set_display_enable(dsi, false);
1422 drm_panel_unprepare(dsi->panel);
1423
1424 dsi->state &= ~DSIM_STATE_ENABLED;
1425
1426 pm_runtime_put_sync(dsi->dev);
1427}
1428
1429static enum drm_connector_status
1430exynos_dsi_detect(struct drm_connector *connector, bool force)
1431{
1432 return connector->status;
1433}
1434
1435static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1436{
1437 drm_connector_unregister(connector);
1438 drm_connector_cleanup(connector);
1439 connector->dev = NULL;
1440}
1441
1442static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1443 .detect = exynos_dsi_detect,
1444 .fill_modes = drm_helper_probe_single_connector_modes,
1445 .destroy = exynos_dsi_connector_destroy,
1446 .reset = drm_atomic_helper_connector_reset,
1447 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1448 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1449};
1450
1451static int exynos_dsi_get_modes(struct drm_connector *connector)
1452{
1453 struct exynos_dsi *dsi = connector_to_dsi(connector);
1454
1455 if (dsi->panel)
1456 return dsi->panel->funcs->get_modes(dsi->panel);
1457
1458 return 0;
1459}
1460
1461static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1462 .get_modes = exynos_dsi_get_modes,
1463};
1464
1465static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1466{
1467 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1468 struct drm_connector *connector = &dsi->connector;
1469 int ret;
1470
1471 connector->polled = DRM_CONNECTOR_POLL_HPD;
1472
1473 ret = drm_connector_init(encoder->dev, connector,
1474 &exynos_dsi_connector_funcs,
1475 DRM_MODE_CONNECTOR_DSI);
1476 if (ret) {
1477 DRM_ERROR("Failed to initialize connector with drm\n");
1478 return ret;
1479 }
1480
1481 connector->status = connector_status_disconnected;
1482 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1483 drm_mode_connector_attach_encoder(connector, encoder);
1484
1485 return 0;
1486}
1487
1488static void exynos_dsi_mode_set(struct drm_encoder *encoder,
1489 struct drm_display_mode *mode,
1490 struct drm_display_mode *adjusted_mode)
1491{
1492 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1493 struct videomode *vm = &dsi->vm;
1494 struct drm_display_mode *m = adjusted_mode;
1495
1496 vm->hactive = m->hdisplay;
1497 vm->vactive = m->vdisplay;
1498 vm->vfront_porch = m->vsync_start - m->vdisplay;
1499 vm->vback_porch = m->vtotal - m->vsync_end;
1500 vm->vsync_len = m->vsync_end - m->vsync_start;
1501 vm->hfront_porch = m->hsync_start - m->hdisplay;
1502 vm->hback_porch = m->htotal - m->hsync_end;
1503 vm->hsync_len = m->hsync_end - m->hsync_start;
1504}
1505
1506static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1507 .mode_set = exynos_dsi_mode_set,
1508 .enable = exynos_dsi_enable,
1509 .disable = exynos_dsi_disable,
1510};
1511
1512static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = {
1513 .destroy = drm_encoder_cleanup,
1514};
1515
1516MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1517
1518static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1519 struct mipi_dsi_device *device)
1520{
1521 struct exynos_dsi *dsi = host_to_dsi(host);
1522 struct drm_device *drm = dsi->connector.dev;
1523
1524
1525
1526
1527
1528
1529
1530 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1531 int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1532 if (ret)
1533 return ret;
1534 }
1535
1536 mutex_lock(&drm->mode_config.mutex);
1537
1538 dsi->lanes = device->lanes;
1539 dsi->format = device->format;
1540 dsi->mode_flags = device->mode_flags;
1541 dsi->panel = of_drm_find_panel(device->dev.of_node);
1542 if (dsi->panel) {
1543 drm_panel_attach(dsi->panel, &dsi->connector);
1544 dsi->connector.status = connector_status_connected;
1545 }
1546 exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1547 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1548
1549 mutex_unlock(&drm->mode_config.mutex);
1550
1551 if (drm->mode_config.poll_enabled)
1552 drm_kms_helper_hotplug_event(drm);
1553
1554 return 0;
1555}
1556
1557static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1558 struct mipi_dsi_device *device)
1559{
1560 struct exynos_dsi *dsi = host_to_dsi(host);
1561 struct drm_device *drm = dsi->connector.dev;
1562
1563 mutex_lock(&drm->mode_config.mutex);
1564
1565 if (dsi->panel) {
1566 exynos_dsi_disable(&dsi->encoder);
1567 drm_panel_detach(dsi->panel);
1568 dsi->panel = NULL;
1569 dsi->connector.status = connector_status_disconnected;
1570 }
1571
1572 mutex_unlock(&drm->mode_config.mutex);
1573
1574 if (drm->mode_config.poll_enabled)
1575 drm_kms_helper_hotplug_event(drm);
1576
1577 exynos_dsi_unregister_te_irq(dsi);
1578
1579 return 0;
1580}
1581
1582static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1583 const struct mipi_dsi_msg *msg)
1584{
1585 struct exynos_dsi *dsi = host_to_dsi(host);
1586 struct exynos_dsi_transfer xfer;
1587 int ret;
1588
1589 if (!(dsi->state & DSIM_STATE_ENABLED))
1590 return -EINVAL;
1591
1592 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1593 ret = exynos_dsi_init(dsi);
1594 if (ret)
1595 return ret;
1596 dsi->state |= DSIM_STATE_INITIALIZED;
1597 }
1598
1599 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1600 if (ret < 0)
1601 return ret;
1602
1603 xfer.rx_len = msg->rx_len;
1604 xfer.rx_payload = msg->rx_buf;
1605 xfer.flags = msg->flags;
1606
1607 ret = exynos_dsi_transfer(dsi, &xfer);
1608 return (ret < 0) ? ret : xfer.rx_done;
1609}
1610
1611static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1612 .attach = exynos_dsi_host_attach,
1613 .detach = exynos_dsi_host_detach,
1614 .transfer = exynos_dsi_host_transfer,
1615};
1616
1617static int exynos_dsi_of_read_u32(const struct device_node *np,
1618 const char *propname, u32 *out_value)
1619{
1620 int ret = of_property_read_u32(np, propname, out_value);
1621
1622 if (ret < 0)
1623 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1624
1625 return ret;
1626}
1627
1628enum {
1629 DSI_PORT_IN,
1630 DSI_PORT_OUT
1631};
1632
1633static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1634{
1635 struct device *dev = dsi->dev;
1636 struct device_node *node = dev->of_node;
1637 int ret;
1638
1639 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1640 &dsi->pll_clk_rate);
1641 if (ret < 0)
1642 return ret;
1643
1644 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
1645 &dsi->burst_clk_rate);
1646 if (ret < 0)
1647 return ret;
1648
1649 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
1650 &dsi->esc_clk_rate);
1651 if (ret < 0)
1652 return ret;
1653
1654 dsi->bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
1655
1656 return 0;
1657}
1658
1659static int exynos_dsi_bind(struct device *dev, struct device *master,
1660 void *data)
1661{
1662 struct drm_encoder *encoder = dev_get_drvdata(dev);
1663 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1664 struct drm_device *drm_dev = data;
1665 struct drm_bridge *bridge;
1666 int ret;
1667
1668 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs,
1669 DRM_MODE_ENCODER_TMDS, NULL);
1670
1671 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1672
1673 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
1674 if (ret < 0)
1675 return ret;
1676
1677 ret = exynos_dsi_create_connector(encoder);
1678 if (ret) {
1679 DRM_ERROR("failed to create connector ret = %d\n", ret);
1680 drm_encoder_cleanup(encoder);
1681 return ret;
1682 }
1683
1684 if (dsi->bridge_node) {
1685 bridge = of_drm_find_bridge(dsi->bridge_node);
1686 if (bridge)
1687 drm_bridge_attach(encoder, bridge, NULL);
1688 }
1689
1690 return mipi_dsi_host_register(&dsi->dsi_host);
1691}
1692
1693static void exynos_dsi_unbind(struct device *dev, struct device *master,
1694 void *data)
1695{
1696 struct drm_encoder *encoder = dev_get_drvdata(dev);
1697 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1698
1699 exynos_dsi_disable(encoder);
1700
1701 mipi_dsi_host_unregister(&dsi->dsi_host);
1702}
1703
1704static const struct component_ops exynos_dsi_component_ops = {
1705 .bind = exynos_dsi_bind,
1706 .unbind = exynos_dsi_unbind,
1707};
1708
1709static int exynos_dsi_probe(struct platform_device *pdev)
1710{
1711 struct device *dev = &pdev->dev;
1712 struct resource *res;
1713 struct exynos_dsi *dsi;
1714 int ret, i;
1715
1716 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1717 if (!dsi)
1718 return -ENOMEM;
1719
1720
1721 dsi->te_gpio = -ENOENT;
1722
1723 init_completion(&dsi->completed);
1724 spin_lock_init(&dsi->transfer_lock);
1725 INIT_LIST_HEAD(&dsi->transfer_list);
1726
1727 dsi->dsi_host.ops = &exynos_dsi_ops;
1728 dsi->dsi_host.dev = dev;
1729
1730 dsi->dev = dev;
1731 dsi->driver_data = of_device_get_match_data(dev);
1732
1733 ret = exynos_dsi_parse_dt(dsi);
1734 if (ret)
1735 return ret;
1736
1737 dsi->supplies[0].supply = "vddcore";
1738 dsi->supplies[1].supply = "vddio";
1739 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1740 dsi->supplies);
1741 if (ret) {
1742 dev_info(dev, "failed to get regulators: %d\n", ret);
1743 return -EPROBE_DEFER;
1744 }
1745
1746 dsi->clks = devm_kzalloc(dev,
1747 sizeof(*dsi->clks) * dsi->driver_data->num_clks,
1748 GFP_KERNEL);
1749 if (!dsi->clks)
1750 return -ENOMEM;
1751
1752 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1753 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1754 if (IS_ERR(dsi->clks[i])) {
1755 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1756 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1757 i--;
1758 continue;
1759 }
1760
1761 dev_info(dev, "failed to get the clock: %s\n",
1762 clk_names[i]);
1763 return PTR_ERR(dsi->clks[i]);
1764 }
1765 }
1766
1767 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1768 dsi->reg_base = devm_ioremap_resource(dev, res);
1769 if (IS_ERR(dsi->reg_base)) {
1770 dev_err(dev, "failed to remap io region\n");
1771 return PTR_ERR(dsi->reg_base);
1772 }
1773
1774 dsi->phy = devm_phy_get(dev, "dsim");
1775 if (IS_ERR(dsi->phy)) {
1776 dev_info(dev, "failed to get dsim phy\n");
1777 return PTR_ERR(dsi->phy);
1778 }
1779
1780 dsi->irq = platform_get_irq(pdev, 0);
1781 if (dsi->irq < 0) {
1782 dev_err(dev, "failed to request dsi irq resource\n");
1783 return dsi->irq;
1784 }
1785
1786 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1787 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1788 exynos_dsi_irq, IRQF_ONESHOT,
1789 dev_name(dev), dsi);
1790 if (ret) {
1791 dev_err(dev, "failed to request dsi irq\n");
1792 return ret;
1793 }
1794
1795 platform_set_drvdata(pdev, &dsi->encoder);
1796
1797 pm_runtime_enable(dev);
1798
1799 return component_add(dev, &exynos_dsi_component_ops);
1800}
1801
1802static int exynos_dsi_remove(struct platform_device *pdev)
1803{
1804 struct exynos_dsi *dsi = platform_get_drvdata(pdev);
1805
1806 of_node_put(dsi->bridge_node);
1807
1808 pm_runtime_disable(&pdev->dev);
1809
1810 component_del(&pdev->dev, &exynos_dsi_component_ops);
1811
1812 return 0;
1813}
1814
1815static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1816{
1817 struct drm_encoder *encoder = dev_get_drvdata(dev);
1818 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1819 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1820 int ret, i;
1821
1822 usleep_range(10000, 20000);
1823
1824 if (dsi->state & DSIM_STATE_INITIALIZED) {
1825 dsi->state &= ~DSIM_STATE_INITIALIZED;
1826
1827 exynos_dsi_disable_clock(dsi);
1828
1829 exynos_dsi_disable_irq(dsi);
1830 }
1831
1832 dsi->state &= ~DSIM_STATE_CMD_LPM;
1833
1834 phy_power_off(dsi->phy);
1835
1836 for (i = driver_data->num_clks - 1; i > -1; i--)
1837 clk_disable_unprepare(dsi->clks[i]);
1838
1839 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1840 if (ret < 0)
1841 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1842
1843 return 0;
1844}
1845
1846static int __maybe_unused exynos_dsi_resume(struct device *dev)
1847{
1848 struct drm_encoder *encoder = dev_get_drvdata(dev);
1849 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1850 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1851 int ret, i;
1852
1853 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1854 if (ret < 0) {
1855 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1856 return ret;
1857 }
1858
1859 for (i = 0; i < driver_data->num_clks; i++) {
1860 ret = clk_prepare_enable(dsi->clks[i]);
1861 if (ret < 0)
1862 goto err_clk;
1863 }
1864
1865 ret = phy_power_on(dsi->phy);
1866 if (ret < 0) {
1867 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1868 goto err_clk;
1869 }
1870
1871 return 0;
1872
1873err_clk:
1874 while (--i > -1)
1875 clk_disable_unprepare(dsi->clks[i]);
1876 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1877
1878 return ret;
1879}
1880
1881static const struct dev_pm_ops exynos_dsi_pm_ops = {
1882 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1883};
1884
1885struct platform_driver dsi_driver = {
1886 .probe = exynos_dsi_probe,
1887 .remove = exynos_dsi_remove,
1888 .driver = {
1889 .name = "exynos-dsi",
1890 .owner = THIS_MODULE,
1891 .pm = &exynos_dsi_pm_ops,
1892 .of_match_table = exynos_dsi_of_match,
1893 },
1894};
1895
1896MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1897MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1898MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1899MODULE_LICENSE("GPL v2");
1900
