LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

   1/*
   2 * Copyright 2016 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs <bskeggs@redhat.com>
  23 */
  24#include "nv50.h"
  25#include "head.h"
  26#include "ior.h"
  27#include "channv50.h"
  28#include "rootnv50.h"
  29
  30static void
  31gp102_disp_intr_error(struct nv50_disp *disp, int chid)
  32{
  33        struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  34        struct nvkm_device *device = subdev->device;
  35        u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
  36        u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
  37        u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
  38
  39        nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
  40                   chid, (mthd & 0x0000ffc), data, mthd, unkn);
  41
  42        if (chid < ARRAY_SIZE(disp->chan)) {
  43                switch (mthd & 0xffc) {
  44                case 0x0080:
  45                        nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
  46                        break;
  47                default:
  48                        break;
  49                }
  50        }
  51
  52        nvkm_wr32(device, 0x61009c, (1 << chid));
  53        nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000);
  54}
  55
  56static const struct nv50_disp_func
  57gp102_disp = {
  58        .init = gf119_disp_init,
  59        .fini = gf119_disp_fini,
  60        .intr = gf119_disp_intr,
  61        .intr_error = gp102_disp_intr_error,
  62        .uevent = &gf119_disp_chan_uevent,
  63        .super = gf119_disp_super,
  64        .root = &gp102_disp_root_oclass,
  65        .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
  66        .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
  67};
  68
  69int
  70gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
  71{
  72        return nv50_disp_new_(&gp102_disp, device, index, pdisp);
  73}
  74