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32#include <drm/ttm/ttm_bo_api.h>
33#include <drm/ttm/ttm_bo_driver.h>
34#include <drm/ttm/ttm_placement.h>
35#include <drm/ttm/ttm_module.h>
36#include <drm/ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/radeon_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "radeon_reg.h"
46#include "radeon.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
51static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
52
53static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
54{
55 struct radeon_mman *mman;
56 struct radeon_device *rdev;
57
58 mman = container_of(bdev, struct radeon_mman, bdev);
59 rdev = container_of(mman, struct radeon_device, mman);
60 return rdev;
61}
62
63static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
64{
65 return 0;
66}
67
68static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
69 struct ttm_mem_type_manager *man)
70{
71 struct radeon_device *rdev;
72
73 rdev = radeon_get_rdev(bdev);
74
75 switch (type) {
76 case TTM_PL_SYSTEM:
77
78 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
79 man->available_caching = TTM_PL_MASK_CACHING;
80 man->default_caching = TTM_PL_FLAG_CACHED;
81 break;
82 case TTM_PL_TT:
83 man->func = &ttm_bo_manager_func;
84 man->gpu_offset = rdev->mc.gtt_start;
85 man->available_caching = TTM_PL_MASK_CACHING;
86 man->default_caching = TTM_PL_FLAG_CACHED;
87 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
88#if IS_ENABLED(CONFIG_AGP)
89 if (rdev->flags & RADEON_IS_AGP) {
90 if (!rdev->ddev->agp) {
91 DRM_ERROR("AGP is not enabled for memory type %u\n",
92 (unsigned)type);
93 return -EINVAL;
94 }
95 if (!rdev->ddev->agp->cant_use_aperture)
96 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
97 man->available_caching = TTM_PL_FLAG_UNCACHED |
98 TTM_PL_FLAG_WC;
99 man->default_caching = TTM_PL_FLAG_WC;
100 }
101#endif
102 break;
103 case TTM_PL_VRAM:
104
105 man->func = &ttm_bo_manager_func;
106 man->gpu_offset = rdev->mc.vram_start;
107 man->flags = TTM_MEMTYPE_FLAG_FIXED |
108 TTM_MEMTYPE_FLAG_MAPPABLE;
109 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
110 man->default_caching = TTM_PL_FLAG_WC;
111 break;
112 default:
113 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
114 return -EINVAL;
115 }
116 return 0;
117}
118
119static void radeon_evict_flags(struct ttm_buffer_object *bo,
120 struct ttm_placement *placement)
121{
122 static const struct ttm_place placements = {
123 .fpfn = 0,
124 .lpfn = 0,
125 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
126 };
127
128 struct radeon_bo *rbo;
129
130 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
131 placement->placement = &placements;
132 placement->busy_placement = &placements;
133 placement->num_placement = 1;
134 placement->num_busy_placement = 1;
135 return;
136 }
137 rbo = container_of(bo, struct radeon_bo, tbo);
138 switch (bo->mem.mem_type) {
139 case TTM_PL_VRAM:
140 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
141 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
142 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
143 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
144 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
145 int i;
146
147
148
149
150
151
152 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
153 RADEON_GEM_DOMAIN_GTT);
154 rbo->placement.num_busy_placement = 0;
155 for (i = 0; i < rbo->placement.num_placement; i++) {
156 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
157 if (rbo->placements[i].fpfn < fpfn)
158 rbo->placements[i].fpfn = fpfn;
159 } else {
160 rbo->placement.busy_placement =
161 &rbo->placements[i];
162 rbo->placement.num_busy_placement = 1;
163 }
164 }
165 } else
166 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
167 break;
168 case TTM_PL_TT:
169 default:
170 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
171 }
172 *placement = rbo->placement;
173}
174
175static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
176{
177 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
178
179 if (radeon_ttm_tt_has_userptr(bo->ttm))
180 return -EPERM;
181 return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
182 filp->private_data);
183}
184
185static void radeon_move_null(struct ttm_buffer_object *bo,
186 struct ttm_mem_reg *new_mem)
187{
188 struct ttm_mem_reg *old_mem = &bo->mem;
189
190 BUG_ON(old_mem->mm_node != NULL);
191 *old_mem = *new_mem;
192 new_mem->mm_node = NULL;
193}
194
195static int radeon_move_blit(struct ttm_buffer_object *bo,
196 bool evict, bool no_wait_gpu,
197 struct ttm_mem_reg *new_mem,
198 struct ttm_mem_reg *old_mem)
199{
200 struct radeon_device *rdev;
201 uint64_t old_start, new_start;
202 struct radeon_fence *fence;
203 unsigned num_pages;
204 int r, ridx;
205
206 rdev = radeon_get_rdev(bo->bdev);
207 ridx = radeon_copy_ring_index(rdev);
208 old_start = (u64)old_mem->start << PAGE_SHIFT;
209 new_start = (u64)new_mem->start << PAGE_SHIFT;
210
211 switch (old_mem->mem_type) {
212 case TTM_PL_VRAM:
213 old_start += rdev->mc.vram_start;
214 break;
215 case TTM_PL_TT:
216 old_start += rdev->mc.gtt_start;
217 break;
218 default:
219 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
220 return -EINVAL;
221 }
222 switch (new_mem->mem_type) {
223 case TTM_PL_VRAM:
224 new_start += rdev->mc.vram_start;
225 break;
226 case TTM_PL_TT:
227 new_start += rdev->mc.gtt_start;
228 break;
229 default:
230 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
231 return -EINVAL;
232 }
233 if (!rdev->ring[ridx].ready) {
234 DRM_ERROR("Trying to move memory with ring turned off.\n");
235 return -EINVAL;
236 }
237
238 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
239
240 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
241 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
242 if (IS_ERR(fence))
243 return PTR_ERR(fence);
244
245 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
246 radeon_fence_unref(&fence);
247 return r;
248}
249
250static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
251 bool evict, bool interruptible,
252 bool no_wait_gpu,
253 struct ttm_mem_reg *new_mem)
254{
255 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
256 struct radeon_device *rdev;
257 struct ttm_mem_reg *old_mem = &bo->mem;
258 struct ttm_mem_reg tmp_mem;
259 struct ttm_place placements;
260 struct ttm_placement placement;
261 int r;
262
263 rdev = radeon_get_rdev(bo->bdev);
264 tmp_mem = *new_mem;
265 tmp_mem.mm_node = NULL;
266 placement.num_placement = 1;
267 placement.placement = &placements;
268 placement.num_busy_placement = 1;
269 placement.busy_placement = &placements;
270 placements.fpfn = 0;
271 placements.lpfn = 0;
272 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
273 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
274 if (unlikely(r)) {
275 return r;
276 }
277
278 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
279 if (unlikely(r)) {
280 goto out_cleanup;
281 }
282
283 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx);
284 if (unlikely(r)) {
285 goto out_cleanup;
286 }
287 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
288 if (unlikely(r)) {
289 goto out_cleanup;
290 }
291 r = ttm_bo_move_ttm(bo, &ctx, new_mem);
292out_cleanup:
293 ttm_bo_mem_put(bo, &tmp_mem);
294 return r;
295}
296
297static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
298 bool evict, bool interruptible,
299 bool no_wait_gpu,
300 struct ttm_mem_reg *new_mem)
301{
302 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
303 struct radeon_device *rdev;
304 struct ttm_mem_reg *old_mem = &bo->mem;
305 struct ttm_mem_reg tmp_mem;
306 struct ttm_placement placement;
307 struct ttm_place placements;
308 int r;
309
310 rdev = radeon_get_rdev(bo->bdev);
311 tmp_mem = *new_mem;
312 tmp_mem.mm_node = NULL;
313 placement.num_placement = 1;
314 placement.placement = &placements;
315 placement.num_busy_placement = 1;
316 placement.busy_placement = &placements;
317 placements.fpfn = 0;
318 placements.lpfn = 0;
319 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
320 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
321 if (unlikely(r)) {
322 return r;
323 }
324 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
325 if (unlikely(r)) {
326 goto out_cleanup;
327 }
328 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
329 if (unlikely(r)) {
330 goto out_cleanup;
331 }
332out_cleanup:
333 ttm_bo_mem_put(bo, &tmp_mem);
334 return r;
335}
336
337static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
338 struct ttm_operation_ctx *ctx,
339 struct ttm_mem_reg *new_mem)
340{
341 struct radeon_device *rdev;
342 struct radeon_bo *rbo;
343 struct ttm_mem_reg *old_mem = &bo->mem;
344 int r;
345
346 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
347 if (r)
348 return r;
349
350
351 rbo = container_of(bo, struct radeon_bo, tbo);
352 if (WARN_ON_ONCE(rbo->pin_count > 0))
353 return -EINVAL;
354
355 rdev = radeon_get_rdev(bo->bdev);
356 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
357 radeon_move_null(bo, new_mem);
358 return 0;
359 }
360 if ((old_mem->mem_type == TTM_PL_TT &&
361 new_mem->mem_type == TTM_PL_SYSTEM) ||
362 (old_mem->mem_type == TTM_PL_SYSTEM &&
363 new_mem->mem_type == TTM_PL_TT)) {
364
365 radeon_move_null(bo, new_mem);
366 return 0;
367 }
368 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
369 rdev->asic->copy.copy == NULL) {
370
371 goto memcpy;
372 }
373
374 if (old_mem->mem_type == TTM_PL_VRAM &&
375 new_mem->mem_type == TTM_PL_SYSTEM) {
376 r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
377 ctx->no_wait_gpu, new_mem);
378 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
379 new_mem->mem_type == TTM_PL_VRAM) {
380 r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
381 ctx->no_wait_gpu, new_mem);
382 } else {
383 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
384 new_mem, old_mem);
385 }
386
387 if (r) {
388memcpy:
389 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
390 if (r) {
391 return r;
392 }
393 }
394
395
396 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
397 return 0;
398}
399
400static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
401{
402 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
403 struct radeon_device *rdev = radeon_get_rdev(bdev);
404
405 mem->bus.addr = NULL;
406 mem->bus.offset = 0;
407 mem->bus.size = mem->num_pages << PAGE_SHIFT;
408 mem->bus.base = 0;
409 mem->bus.is_iomem = false;
410 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
411 return -EINVAL;
412 switch (mem->mem_type) {
413 case TTM_PL_SYSTEM:
414
415 return 0;
416 case TTM_PL_TT:
417#if IS_ENABLED(CONFIG_AGP)
418 if (rdev->flags & RADEON_IS_AGP) {
419
420 mem->bus.offset = mem->start << PAGE_SHIFT;
421 mem->bus.base = rdev->mc.agp_base;
422 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
423 }
424#endif
425 break;
426 case TTM_PL_VRAM:
427 mem->bus.offset = mem->start << PAGE_SHIFT;
428
429 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
430 return -EINVAL;
431 mem->bus.base = rdev->mc.aper_base;
432 mem->bus.is_iomem = true;
433#ifdef __alpha__
434
435
436
437
438 if (mem->placement & TTM_PL_FLAG_WC)
439 mem->bus.addr =
440 ioremap_wc(mem->bus.base + mem->bus.offset,
441 mem->bus.size);
442 else
443 mem->bus.addr =
444 ioremap_nocache(mem->bus.base + mem->bus.offset,
445 mem->bus.size);
446 if (!mem->bus.addr)
447 return -ENOMEM;
448
449
450
451
452
453
454
455 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
456 rdev->ddev->hose->dense_mem_base;
457#endif
458 break;
459 default:
460 return -EINVAL;
461 }
462 return 0;
463}
464
465static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
466{
467}
468
469
470
471
472struct radeon_ttm_tt {
473 struct ttm_dma_tt ttm;
474 struct radeon_device *rdev;
475 u64 offset;
476
477 uint64_t userptr;
478 struct mm_struct *usermm;
479 uint32_t userflags;
480};
481
482
483static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
484{
485 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
486 struct radeon_ttm_tt *gtt = (void *)ttm;
487 unsigned pinned = 0, nents;
488 int r;
489
490 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
491 enum dma_data_direction direction = write ?
492 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
493
494 if (current->mm != gtt->usermm)
495 return -EPERM;
496
497 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
498
499
500 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
501 struct vm_area_struct *vma;
502 vma = find_vma(gtt->usermm, gtt->userptr);
503 if (!vma || vma->vm_file || vma->vm_end < end)
504 return -EPERM;
505 }
506
507 do {
508 unsigned num_pages = ttm->num_pages - pinned;
509 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
510 struct page **pages = ttm->pages + pinned;
511
512 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
513 pages, NULL);
514 if (r < 0)
515 goto release_pages;
516
517 pinned += r;
518
519 } while (pinned < ttm->num_pages);
520
521 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
522 ttm->num_pages << PAGE_SHIFT,
523 GFP_KERNEL);
524 if (r)
525 goto release_sg;
526
527 r = -ENOMEM;
528 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
529 if (nents != ttm->sg->nents)
530 goto release_sg;
531
532 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
533 gtt->ttm.dma_address, ttm->num_pages);
534
535 return 0;
536
537release_sg:
538 kfree(ttm->sg);
539
540release_pages:
541 release_pages(ttm->pages, pinned, 0);
542 return r;
543}
544
545static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
546{
547 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
548 struct radeon_ttm_tt *gtt = (void *)ttm;
549 struct sg_page_iter sg_iter;
550
551 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
552 enum dma_data_direction direction = write ?
553 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
554
555
556 if (!ttm->sg->sgl)
557 return;
558
559
560 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
561
562 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
563 struct page *page = sg_page_iter_page(&sg_iter);
564 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
565 set_page_dirty(page);
566
567 mark_page_accessed(page);
568 put_page(page);
569 }
570
571 sg_free_table(ttm->sg);
572}
573
574static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
575 struct ttm_mem_reg *bo_mem)
576{
577 struct radeon_ttm_tt *gtt = (void*)ttm;
578 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
579 RADEON_GART_PAGE_WRITE;
580 int r;
581
582 if (gtt->userptr) {
583 radeon_ttm_tt_pin_userptr(ttm);
584 flags &= ~RADEON_GART_PAGE_WRITE;
585 }
586
587 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
588 if (!ttm->num_pages) {
589 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
590 ttm->num_pages, bo_mem, ttm);
591 }
592 if (ttm->caching_state == tt_cached)
593 flags |= RADEON_GART_PAGE_SNOOP;
594 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
595 ttm->pages, gtt->ttm.dma_address, flags);
596 if (r) {
597 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
598 ttm->num_pages, (unsigned)gtt->offset);
599 return r;
600 }
601 return 0;
602}
603
604static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
605{
606 struct radeon_ttm_tt *gtt = (void *)ttm;
607
608 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
609
610 if (gtt->userptr)
611 radeon_ttm_tt_unpin_userptr(ttm);
612
613 return 0;
614}
615
616static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
617{
618 struct radeon_ttm_tt *gtt = (void *)ttm;
619
620 ttm_dma_tt_fini(>t->ttm);
621 kfree(gtt);
622}
623
624static struct ttm_backend_func radeon_backend_func = {
625 .bind = &radeon_ttm_backend_bind,
626 .unbind = &radeon_ttm_backend_unbind,
627 .destroy = &radeon_ttm_backend_destroy,
628};
629
630static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
631 uint32_t page_flags)
632{
633 struct radeon_device *rdev;
634 struct radeon_ttm_tt *gtt;
635
636 rdev = radeon_get_rdev(bo->bdev);
637#if IS_ENABLED(CONFIG_AGP)
638 if (rdev->flags & RADEON_IS_AGP) {
639 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge,
640 page_flags);
641 }
642#endif
643
644 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
645 if (gtt == NULL) {
646 return NULL;
647 }
648 gtt->ttm.ttm.func = &radeon_backend_func;
649 gtt->rdev = rdev;
650 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) {
651 kfree(gtt);
652 return NULL;
653 }
654 return >t->ttm.ttm;
655}
656
657static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
658{
659 if (!ttm || ttm->func != &radeon_backend_func)
660 return NULL;
661 return (struct radeon_ttm_tt *)ttm;
662}
663
664static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
665 struct ttm_operation_ctx *ctx)
666{
667 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
668 struct radeon_device *rdev;
669 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
670
671 if (gtt && gtt->userptr) {
672 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
673 if (!ttm->sg)
674 return -ENOMEM;
675
676 ttm->page_flags |= TTM_PAGE_FLAG_SG;
677 ttm->state = tt_unbound;
678 return 0;
679 }
680
681 if (slave && ttm->sg) {
682 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
683 gtt->ttm.dma_address, ttm->num_pages);
684 ttm->state = tt_unbound;
685 return 0;
686 }
687
688 rdev = radeon_get_rdev(ttm->bdev);
689#if IS_ENABLED(CONFIG_AGP)
690 if (rdev->flags & RADEON_IS_AGP) {
691 return ttm_agp_tt_populate(ttm, ctx);
692 }
693#endif
694
695#ifdef CONFIG_SWIOTLB
696 if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
697 return ttm_dma_populate(>t->ttm, rdev->dev, ctx);
698 }
699#endif
700
701 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx);
702}
703
704static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
705{
706 struct radeon_device *rdev;
707 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
708 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
709
710 if (gtt && gtt->userptr) {
711 kfree(ttm->sg);
712 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
713 return;
714 }
715
716 if (slave)
717 return;
718
719 rdev = radeon_get_rdev(ttm->bdev);
720#if IS_ENABLED(CONFIG_AGP)
721 if (rdev->flags & RADEON_IS_AGP) {
722 ttm_agp_tt_unpopulate(ttm);
723 return;
724 }
725#endif
726
727#ifdef CONFIG_SWIOTLB
728 if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
729 ttm_dma_unpopulate(>t->ttm, rdev->dev);
730 return;
731 }
732#endif
733
734 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm);
735}
736
737int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
738 uint32_t flags)
739{
740 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
741
742 if (gtt == NULL)
743 return -EINVAL;
744
745 gtt->userptr = addr;
746 gtt->usermm = current->mm;
747 gtt->userflags = flags;
748 return 0;
749}
750
751bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
752{
753 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
754
755 if (gtt == NULL)
756 return false;
757
758 return !!gtt->userptr;
759}
760
761bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
762{
763 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
764
765 if (gtt == NULL)
766 return false;
767
768 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
769}
770
771static struct ttm_bo_driver radeon_bo_driver = {
772 .ttm_tt_create = &radeon_ttm_tt_create,
773 .ttm_tt_populate = &radeon_ttm_tt_populate,
774 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
775 .invalidate_caches = &radeon_invalidate_caches,
776 .init_mem_type = &radeon_init_mem_type,
777 .eviction_valuable = ttm_bo_eviction_valuable,
778 .evict_flags = &radeon_evict_flags,
779 .move = &radeon_bo_move,
780 .verify_access = &radeon_verify_access,
781 .move_notify = &radeon_bo_move_notify,
782 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
783 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
784 .io_mem_free = &radeon_ttm_io_mem_free,
785};
786
787int radeon_ttm_init(struct radeon_device *rdev)
788{
789 int r;
790
791
792 r = ttm_bo_device_init(&rdev->mman.bdev,
793 &radeon_bo_driver,
794 rdev->ddev->anon_inode->i_mapping,
795 DRM_FILE_PAGE_OFFSET,
796 rdev->need_dma32);
797 if (r) {
798 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
799 return r;
800 }
801 rdev->mman.initialized = true;
802 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
803 rdev->mc.real_vram_size >> PAGE_SHIFT);
804 if (r) {
805 DRM_ERROR("Failed initializing VRAM heap.\n");
806 return r;
807 }
808
809 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
810
811 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
812 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
813 NULL, &rdev->stolen_vga_memory);
814 if (r) {
815 return r;
816 }
817 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
818 if (r)
819 return r;
820 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
821 radeon_bo_unreserve(rdev->stolen_vga_memory);
822 if (r) {
823 radeon_bo_unref(&rdev->stolen_vga_memory);
824 return r;
825 }
826 DRM_INFO("radeon: %uM of VRAM memory ready\n",
827 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
828 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
829 rdev->mc.gtt_size >> PAGE_SHIFT);
830 if (r) {
831 DRM_ERROR("Failed initializing GTT heap.\n");
832 return r;
833 }
834 DRM_INFO("radeon: %uM of GTT memory ready.\n",
835 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
836
837 r = radeon_ttm_debugfs_init(rdev);
838 if (r) {
839 DRM_ERROR("Failed to init debugfs\n");
840 return r;
841 }
842 return 0;
843}
844
845void radeon_ttm_fini(struct radeon_device *rdev)
846{
847 int r;
848
849 if (!rdev->mman.initialized)
850 return;
851 radeon_ttm_debugfs_fini(rdev);
852 if (rdev->stolen_vga_memory) {
853 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
854 if (r == 0) {
855 radeon_bo_unpin(rdev->stolen_vga_memory);
856 radeon_bo_unreserve(rdev->stolen_vga_memory);
857 }
858 radeon_bo_unref(&rdev->stolen_vga_memory);
859 }
860 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
861 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
862 ttm_bo_device_release(&rdev->mman.bdev);
863 radeon_gart_fini(rdev);
864 rdev->mman.initialized = false;
865 DRM_INFO("radeon: ttm finalized\n");
866}
867
868
869
870void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
871{
872 struct ttm_mem_type_manager *man;
873
874 if (!rdev->mman.initialized)
875 return;
876
877 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
878
879 man->size = size >> PAGE_SHIFT;
880}
881
882static struct vm_operations_struct radeon_ttm_vm_ops;
883static const struct vm_operations_struct *ttm_vm_ops = NULL;
884
885static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
886{
887 struct ttm_buffer_object *bo;
888 struct radeon_device *rdev;
889 int r;
890
891 bo = (struct ttm_buffer_object *)vma->vm_private_data;
892 if (bo == NULL) {
893 return VM_FAULT_NOPAGE;
894 }
895 rdev = radeon_get_rdev(bo->bdev);
896 down_read(&rdev->pm.mclk_lock);
897 r = ttm_vm_ops->fault(vma, vmf);
898 up_read(&rdev->pm.mclk_lock);
899 return r;
900}
901
902int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
903{
904 struct drm_file *file_priv;
905 struct radeon_device *rdev;
906 int r;
907
908 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
909 return -EINVAL;
910 }
911
912 file_priv = filp->private_data;
913 rdev = file_priv->minor->dev->dev_private;
914 if (rdev == NULL) {
915 return -EINVAL;
916 }
917 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
918 if (unlikely(r != 0)) {
919 return r;
920 }
921 if (unlikely(ttm_vm_ops == NULL)) {
922 ttm_vm_ops = vma->vm_ops;
923 radeon_ttm_vm_ops = *ttm_vm_ops;
924 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
925 }
926 vma->vm_ops = &radeon_ttm_vm_ops;
927 return 0;
928}
929
930#if defined(CONFIG_DEBUG_FS)
931
932static int radeon_mm_dump_table(struct seq_file *m, void *data)
933{
934 struct drm_info_node *node = (struct drm_info_node *)m->private;
935 unsigned ttm_pl = *(int*)node->info_ent->data;
936 struct drm_device *dev = node->minor->dev;
937 struct radeon_device *rdev = dev->dev_private;
938 struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl];
939 struct drm_printer p = drm_seq_file_printer(m);
940
941 man->func->debug(man, &p);
942 return 0;
943}
944
945
946static int ttm_pl_vram = TTM_PL_VRAM;
947static int ttm_pl_tt = TTM_PL_TT;
948
949static struct drm_info_list radeon_ttm_debugfs_list[] = {
950 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
951 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
952 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
953#ifdef CONFIG_SWIOTLB
954 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
955#endif
956};
957
958static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
959{
960 struct radeon_device *rdev = inode->i_private;
961 i_size_write(inode, rdev->mc.mc_vram_size);
962 filep->private_data = inode->i_private;
963 return 0;
964}
965
966static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
967 size_t size, loff_t *pos)
968{
969 struct radeon_device *rdev = f->private_data;
970 ssize_t result = 0;
971 int r;
972
973 if (size & 0x3 || *pos & 0x3)
974 return -EINVAL;
975
976 while (size) {
977 unsigned long flags;
978 uint32_t value;
979
980 if (*pos >= rdev->mc.mc_vram_size)
981 return result;
982
983 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
984 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
985 if (rdev->family >= CHIP_CEDAR)
986 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
987 value = RREG32(RADEON_MM_DATA);
988 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
989
990 r = put_user(value, (uint32_t *)buf);
991 if (r)
992 return r;
993
994 result += 4;
995 buf += 4;
996 *pos += 4;
997 size -= 4;
998 }
999
1000 return result;
1001}
1002
1003static const struct file_operations radeon_ttm_vram_fops = {
1004 .owner = THIS_MODULE,
1005 .open = radeon_ttm_vram_open,
1006 .read = radeon_ttm_vram_read,
1007 .llseek = default_llseek
1008};
1009
1010static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1011{
1012 struct radeon_device *rdev = inode->i_private;
1013 i_size_write(inode, rdev->mc.gtt_size);
1014 filep->private_data = inode->i_private;
1015 return 0;
1016}
1017
1018static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1019 size_t size, loff_t *pos)
1020{
1021 struct radeon_device *rdev = f->private_data;
1022 ssize_t result = 0;
1023 int r;
1024
1025 while (size) {
1026 loff_t p = *pos / PAGE_SIZE;
1027 unsigned off = *pos & ~PAGE_MASK;
1028 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1029 struct page *page;
1030 void *ptr;
1031
1032 if (p >= rdev->gart.num_cpu_pages)
1033 return result;
1034
1035 page = rdev->gart.pages[p];
1036 if (page) {
1037 ptr = kmap(page);
1038 ptr += off;
1039
1040 r = copy_to_user(buf, ptr, cur_size);
1041 kunmap(rdev->gart.pages[p]);
1042 } else
1043 r = clear_user(buf, cur_size);
1044
1045 if (r)
1046 return -EFAULT;
1047
1048 result += cur_size;
1049 buf += cur_size;
1050 *pos += cur_size;
1051 size -= cur_size;
1052 }
1053
1054 return result;
1055}
1056
1057static const struct file_operations radeon_ttm_gtt_fops = {
1058 .owner = THIS_MODULE,
1059 .open = radeon_ttm_gtt_open,
1060 .read = radeon_ttm_gtt_read,
1061 .llseek = default_llseek
1062};
1063
1064#endif
1065
1066static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1067{
1068#if defined(CONFIG_DEBUG_FS)
1069 unsigned count;
1070
1071 struct drm_minor *minor = rdev->ddev->primary;
1072 struct dentry *ent, *root = minor->debugfs_root;
1073
1074 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1075 rdev, &radeon_ttm_vram_fops);
1076 if (IS_ERR(ent))
1077 return PTR_ERR(ent);
1078 rdev->mman.vram = ent;
1079
1080 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1081 rdev, &radeon_ttm_gtt_fops);
1082 if (IS_ERR(ent))
1083 return PTR_ERR(ent);
1084 rdev->mman.gtt = ent;
1085
1086 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1087
1088#ifdef CONFIG_SWIOTLB
1089 if (!(rdev->need_swiotlb && swiotlb_nr_tbl()))
1090 --count;
1091#endif
1092
1093 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1094#else
1095
1096 return 0;
1097#endif
1098}
1099
1100static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1101{
1102#if defined(CONFIG_DEBUG_FS)
1103
1104 debugfs_remove(rdev->mman.vram);
1105 rdev->mman.vram = NULL;
1106
1107 debugfs_remove(rdev->mman.gtt);
1108 rdev->mman.gtt = NULL;
1109#endif
1110}
1111
