1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
31#include <asm/div64.h>
32
33#include "dvb_frontend.h"
34#include "drxd.h"
35#include "drxd_firm.h"
36
37#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
39
40#define CHUNK_SIZE 48
41
42#define DRX_I2C_RMW 0x10
43#define DRX_I2C_BROADCAST 0x20
44#define DRX_I2C_CLEARCRC 0x80
45#define DRX_I2C_SINGLE_MASTER 0xC0
46#define DRX_I2C_MODEFLAGS 0xC0
47#define DRX_I2C_FLAGS 0xF0
48
49#ifndef SIZEOF_ARRAY
50#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
51#endif
52
53#define DEFAULT_LOCK_TIMEOUT 1100
54
55#define DRX_CHANNEL_AUTO 0
56#define DRX_CHANNEL_HIGH 1
57#define DRX_CHANNEL_LOW 2
58
59#define DRX_LOCK_MPEG 1
60#define DRX_LOCK_FEC 2
61#define DRX_LOCK_DEMOD 4
62
63
64
65enum CSCDState {
66 CSCD_INIT = 0,
67 CSCD_SET,
68 CSCD_SAVED
69};
70
71enum CDrxdState {
72 DRXD_UNINITIALIZED = 0,
73 DRXD_STOPPED,
74 DRXD_STARTED
75};
76
77enum AGC_CTRL_MODE {
78 AGC_CTRL_AUTO = 0,
79 AGC_CTRL_USER,
80 AGC_CTRL_OFF
81};
82
83enum OperationMode {
84 OM_Default,
85 OM_DVBT_Diversity_Front,
86 OM_DVBT_Diversity_End
87};
88
89struct SCfgAgc {
90 enum AGC_CTRL_MODE ctrlMode;
91 u16 outputLevel;
92 u16 settleLevel;
93 u16 minOutputLevel;
94 u16 maxOutputLevel;
95 u16 speed;
96
97 u16 R1;
98 u16 R2;
99 u16 R3;
100};
101
102struct SNoiseCal {
103 int cpOpt;
104 short cpNexpOfs;
105 short tdCal2k;
106 short tdCal8k;
107};
108
109enum app_env {
110 APPENV_STATIC = 0,
111 APPENV_PORTABLE = 1,
112 APPENV_MOBILE = 2
113};
114
115enum EIFFilter {
116 IFFILTER_SAW = 0,
117 IFFILTER_DISCRETE = 1
118};
119
120struct drxd_state {
121 struct dvb_frontend frontend;
122 struct dvb_frontend_ops ops;
123 struct dtv_frontend_properties props;
124
125 const struct firmware *fw;
126 struct device *dev;
127
128 struct i2c_adapter *i2c;
129 void *priv;
130 struct drxd_config config;
131
132 int i2c_access;
133 int init_done;
134 struct mutex mutex;
135
136 u8 chip_adr;
137 u16 hi_cfg_timing_div;
138 u16 hi_cfg_bridge_delay;
139 u16 hi_cfg_wakeup_key;
140 u16 hi_cfg_ctrl;
141
142 u16 intermediate_freq;
143 u16 osc_clock_freq;
144
145 enum CSCDState cscd_state;
146 enum CDrxdState drxd_state;
147
148 u16 sys_clock_freq;
149 s16 osc_clock_deviation;
150 u16 expected_sys_clock_freq;
151
152 u16 insert_rs_byte;
153 u16 enable_parallel;
154
155 int operation_mode;
156
157 struct SCfgAgc if_agc_cfg;
158 struct SCfgAgc rf_agc_cfg;
159
160 struct SNoiseCal noise_cal;
161
162 u32 fe_fs_add_incr;
163 u32 org_fe_fs_add_incr;
164 u16 current_fe_if_incr;
165
166 u16 m_FeAgRegAgPwd;
167 u16 m_FeAgRegAgAgcSio;
168
169 u16 m_EcOcRegOcModeLop;
170 u16 m_EcOcRegSncSncLvl;
171 u8 *m_InitAtomicRead;
172 u8 *m_HiI2cPatch;
173
174 u8 *m_ResetCEFR;
175 u8 *m_InitFE_1;
176 u8 *m_InitFE_2;
177 u8 *m_InitCP;
178 u8 *m_InitCE;
179 u8 *m_InitEQ;
180 u8 *m_InitSC;
181 u8 *m_InitEC;
182 u8 *m_ResetECRAM;
183 u8 *m_InitDiversityFront;
184 u8 *m_InitDiversityEnd;
185 u8 *m_DisableDiversity;
186 u8 *m_StartDiversityFront;
187 u8 *m_StartDiversityEnd;
188
189 u8 *m_DiversityDelay8MHZ;
190 u8 *m_DiversityDelay6MHZ;
191
192 u8 *microcode;
193 u32 microcode_length;
194
195 int type_A;
196 int PGA;
197 int diversity;
198 int tuner_mirrors;
199
200 enum app_env app_env_default;
201 enum app_env app_env_diversity;
202
203};
204
205
206
207
208
209static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
210{
211 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
212
213 if (i2c_transfer(adap, &msg, 1) != 1)
214 return -1;
215 return 0;
216}
217
218static int i2c_read(struct i2c_adapter *adap,
219 u8 adr, u8 *msg, int len, u8 *answ, int alen)
220{
221 struct i2c_msg msgs[2] = {
222 {
223 .addr = adr, .flags = 0,
224 .buf = msg, .len = len
225 }, {
226 .addr = adr, .flags = I2C_M_RD,
227 .buf = answ, .len = alen
228 }
229 };
230 if (i2c_transfer(adap, msgs, 2) != 2)
231 return -1;
232 return 0;
233}
234
235static inline u32 MulDiv32(u32 a, u32 b, u32 c)
236{
237 u64 tmp64;
238
239 tmp64 = (u64)a * (u64)b;
240 do_div(tmp64, c);
241
242 return (u32) tmp64;
243}
244
245static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
246{
247 u8 adr = state->config.demod_address;
248 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
249 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
250 };
251 u8 mm2[2];
252 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
253 return -1;
254 if (data)
255 *data = mm2[0] | (mm2[1] << 8);
256 return mm2[0] | (mm2[1] << 8);
257}
258
259static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
260{
261 u8 adr = state->config.demod_address;
262 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
263 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
264 };
265 u8 mm2[4];
266
267 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
268 return -1;
269 if (data)
270 *data =
271 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
272 return 0;
273}
274
275static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
276{
277 u8 adr = state->config.demod_address;
278 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
279 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
280 data & 0xff, (data >> 8) & 0xff
281 };
282
283 if (i2c_write(state->i2c, adr, mm, 6) < 0)
284 return -1;
285 return 0;
286}
287
288static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
289{
290 u8 adr = state->config.demod_address;
291 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
292 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
293 data & 0xff, (data >> 8) & 0xff,
294 (data >> 16) & 0xff, (data >> 24) & 0xff
295 };
296
297 if (i2c_write(state->i2c, adr, mm, 8) < 0)
298 return -1;
299 return 0;
300}
301
302static int write_chunk(struct drxd_state *state,
303 u32 reg, u8 *data, u32 len, u8 flags)
304{
305 u8 adr = state->config.demod_address;
306 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
307 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
308 };
309 int i;
310
311 for (i = 0; i < len; i++)
312 mm[4 + i] = data[i];
313 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
314 printk(KERN_ERR "error in write_chunk\n");
315 return -1;
316 }
317 return 0;
318}
319
320static int WriteBlock(struct drxd_state *state,
321 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
322{
323 while (BlockSize > 0) {
324 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
325
326 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
327 return -1;
328 pBlock += Chunk;
329 Address += (Chunk >> 1);
330 BlockSize -= Chunk;
331 }
332 return 0;
333}
334
335static int WriteTable(struct drxd_state *state, u8 * pTable)
336{
337 int status = 0;
338
339 if (pTable == NULL)
340 return 0;
341
342 while (!status) {
343 u16 Length;
344 u32 Address = pTable[0] | (pTable[1] << 8) |
345 (pTable[2] << 16) | (pTable[3] << 24);
346
347 if (Address == 0xFFFFFFFF)
348 break;
349 pTable += sizeof(u32);
350
351 Length = pTable[0] | (pTable[1] << 8);
352 pTable += sizeof(u16);
353 if (!Length)
354 break;
355 status = WriteBlock(state, Address, Length * 2, pTable, 0);
356 pTable += (Length * 2);
357 }
358 return status;
359}
360
361
362
363
364
365static int ResetCEFR(struct drxd_state *state)
366{
367 return WriteTable(state, state->m_ResetCEFR);
368}
369
370static int InitCP(struct drxd_state *state)
371{
372 return WriteTable(state, state->m_InitCP);
373}
374
375static int InitCE(struct drxd_state *state)
376{
377 int status;
378 enum app_env AppEnv = state->app_env_default;
379
380 do {
381 status = WriteTable(state, state->m_InitCE);
382 if (status < 0)
383 break;
384
385 if (state->operation_mode == OM_DVBT_Diversity_Front ||
386 state->operation_mode == OM_DVBT_Diversity_End) {
387 AppEnv = state->app_env_diversity;
388 }
389 if (AppEnv == APPENV_STATIC) {
390 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
391 if (status < 0)
392 break;
393 } else if (AppEnv == APPENV_PORTABLE) {
394 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
395 if (status < 0)
396 break;
397 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
398 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
399 if (status < 0)
400 break;
401 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
402 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
403 if (status < 0)
404 break;
405 }
406
407
408 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
409 if (status < 0)
410 break;
411 } while (0);
412 return status;
413}
414
415static int StopOC(struct drxd_state *state)
416{
417 int status = 0;
418 u16 ocSyncLvl = 0;
419 u16 ocModeLop = state->m_EcOcRegOcModeLop;
420 u16 dtoIncLop = 0;
421 u16 dtoIncHip = 0;
422
423 do {
424
425 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
426 if (status < 0)
427 break;
428
429 state->m_EcOcRegSncSncLvl = ocSyncLvl;
430
431
432
433 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
434 if (status < 0)
435 break;
436 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
437 if (status < 0)
438 break;
439 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
440 if (status < 0)
441 break;
442 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
443 if (status < 0)
444 break;
445 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
446 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
447 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
448 if (status < 0)
449 break;
450 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
451 if (status < 0)
452 break;
453
454 msleep(1);
455
456 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
457 if (status < 0)
458 break;
459
460
461 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
462 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
463 if (status < 0)
464 break;
465 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
466 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
467 ocModeLop |= 0x2;
468 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
469 if (status < 0)
470 break;
471 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
472 if (status < 0)
473 break;
474 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
475 if (status < 0)
476 break;
477 } while (0);
478
479 return status;
480}
481
482static int StartOC(struct drxd_state *state)
483{
484 int status = 0;
485
486 do {
487
488 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
489 if (status < 0)
490 break;
491
492
493 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
494 if (status < 0)
495 break;
496 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
497 if (status < 0)
498 break;
499
500
501 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
502 if (status < 0)
503 break;
504
505
506 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
507 if (status < 0)
508 break;
509 } while (0);
510 return status;
511}
512
513static int InitEQ(struct drxd_state *state)
514{
515 return WriteTable(state, state->m_InitEQ);
516}
517
518static int InitEC(struct drxd_state *state)
519{
520 return WriteTable(state, state->m_InitEC);
521}
522
523static int InitSC(struct drxd_state *state)
524{
525 return WriteTable(state, state->m_InitSC);
526}
527
528static int InitAtomicRead(struct drxd_state *state)
529{
530 return WriteTable(state, state->m_InitAtomicRead);
531}
532
533static int CorrectSysClockDeviation(struct drxd_state *state);
534
535static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
536{
537 u16 ScRaRamLock = 0;
538 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
539 SC_RA_RAM_LOCK_FEC__M |
540 SC_RA_RAM_LOCK_DEMOD__M);
541 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
542 SC_RA_RAM_LOCK_DEMOD__M);
543 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
544
545 int status;
546
547 *pLockStatus = 0;
548
549 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
550 if (status < 0) {
551 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
552 return status;
553 }
554
555 if (state->drxd_state != DRXD_STARTED)
556 return 0;
557
558 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
559 *pLockStatus |= DRX_LOCK_MPEG;
560 CorrectSysClockDeviation(state);
561 }
562
563 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
564 *pLockStatus |= DRX_LOCK_FEC;
565
566 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
567 *pLockStatus |= DRX_LOCK_DEMOD;
568 return 0;
569}
570
571
572
573static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
574{
575 int status;
576
577 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
578 return -1;
579
580 if (cfg->ctrlMode == AGC_CTRL_USER) {
581 do {
582 u16 FeAgRegPm1AgcWri;
583 u16 FeAgRegAgModeLop;
584
585 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
586 if (status < 0)
587 break;
588 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
589 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
590 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
591 if (status < 0)
592 break;
593
594 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
595 FE_AG_REG_PM1_AGC_WRI__M);
596 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
597 if (status < 0)
598 break;
599 } while (0);
600 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
601 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
602 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
603 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
604 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
605 )
606 return -1;
607 do {
608 u16 FeAgRegAgModeLop;
609 u16 FeAgRegEgcSetLvl;
610 u16 slope, offset;
611
612
613
614 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
615 if (status < 0)
616 break;
617 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
618 FeAgRegAgModeLop |=
619 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
620 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
621 if (status < 0)
622 break;
623
624
625
626 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
627 FE_AG_REG_EGC_SET_LVL__M);
628 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
629 if (status < 0)
630 break;
631
632
633
634 slope = (u16) ((cfg->maxOutputLevel -
635 cfg->minOutputLevel) / 2);
636 offset = (u16) ((cfg->maxOutputLevel +
637 cfg->minOutputLevel) / 2 - 511);
638
639 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
640 if (status < 0)
641 break;
642 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
643 if (status < 0)
644 break;
645
646
647 {
648 const u16 maxRur = 8;
649 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
650 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
651 17, 18, 18, 19,
652 20, 21, 22, 23,
653 24, 26, 27, 28,
654 29, 31
655 };
656
657 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
658 (maxRur + 1);
659 u16 fineSpeed = (u16) (cfg->speed -
660 ((cfg->speed /
661 fineSteps) *
662 fineSteps));
663 u16 invRurCount = (u16) (cfg->speed /
664 fineSteps);
665 u16 rurCount;
666 if (invRurCount > maxRur) {
667 rurCount = 0;
668 fineSpeed += fineSteps;
669 } else {
670 rurCount = maxRur - invRurCount;
671 }
672
673
674
675
676
677
678
679
680 {
681 u16 fastIncrDec =
682 fastIncrDecLUT[fineSpeed /
683 ((fineSteps /
684 (14 + 1)) + 1)];
685 u16 slowIncrDec =
686 slowIncrDecLUT[fineSpeed /
687 (fineSteps /
688 (3 + 1))];
689
690 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
691 if (status < 0)
692 break;
693 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
694 if (status < 0)
695 break;
696 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
697 if (status < 0)
698 break;
699 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
700 if (status < 0)
701 break;
702 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
703 if (status < 0)
704 break;
705 }
706 }
707 } while (0);
708
709 } else {
710
711 return -1;
712 }
713 return status;
714}
715
716static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
717{
718 int status = 0;
719
720 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
721 return -1;
722
723 if (cfg->ctrlMode == AGC_CTRL_USER) {
724 do {
725 u16 AgModeLop = 0;
726 u16 level = (cfg->outputLevel);
727
728 if (level == DRXD_FE_CTRL_MAX)
729 level++;
730
731 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
732 if (status < 0)
733 break;
734
735
736
737
738 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
739 state->m_FeAgRegAgPwd |=
740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
741 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
742 if (status < 0)
743 break;
744
745 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
746 if (status < 0)
747 break;
748 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
749 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
750 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
751 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
752 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
753 if (status < 0)
754 break;
755
756
757 {
758 u16 FeAgRegAgAgcSio = 0;
759 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
760 if (status < 0)
761 break;
762 FeAgRegAgAgcSio &=
763 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
764 FeAgRegAgAgcSio |=
765 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
766 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
767 if (status < 0)
768 break;
769 }
770
771 } while (0);
772 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
773 u16 AgModeLop = 0;
774
775 do {
776 u16 level;
777
778
779 (state->m_FeAgRegAgPwd) &=
780 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
781 (state->m_FeAgRegAgPwd) |=
782 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
783 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
784 if (status < 0)
785 break;
786
787 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
788 if (status < 0)
789 break;
790 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
791 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
792 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
793 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
794 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
795 if (status < 0)
796 break;
797
798 level = (((cfg->settleLevel) >> 4) &
799 FE_AG_REG_TGC_SET_LVL__M);
800 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
801 if (status < 0)
802 break;
803
804
805
806
807
808
809 {
810 u16 FeAgRegAgAgcSio = 0;
811 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
812 if (status < 0)
813 break;
814 FeAgRegAgAgcSio &=
815 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
816 FeAgRegAgAgcSio |=
817 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
818 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
819 if (status < 0)
820 break;
821 }
822
823 } while (0);
824 } else {
825 u16 AgModeLop = 0;
826
827 do {
828
829
830 (state->m_FeAgRegAgPwd) &=
831 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
832 (state->m_FeAgRegAgPwd) |=
833 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
834 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
835 if (status < 0)
836 break;
837
838 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
839 if (status < 0)
840 break;
841 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
842 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
843 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
844 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
845 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
846 if (status < 0)
847 break;
848
849
850 {
851 u16 FeAgRegAgAgcSio = 0;
852 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
853 if (status < 0)
854 break;
855 FeAgRegAgAgcSio &=
856 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
857 FeAgRegAgAgcSio |=
858 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
859 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
860 if (status < 0)
861 break;
862 }
863 } while (0);
864 }
865 return status;
866}
867
868static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
869{
870 int status = 0;
871
872 *pValue = 0;
873 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
874 u16 Value;
875 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
876 Value &= FE_AG_REG_GC1_AGC_DAT__M;
877 if (status >= 0) {
878
879
880
881
882
883
884
885
886
887
888 u32 R1 = state->if_agc_cfg.R1;
889 u32 R2 = state->if_agc_cfg.R2;
890 u32 R3 = state->if_agc_cfg.R3;
891
892 u32 Vmax, Rpar, Vmin, Vout;
893
894 if (R2 == 0 && (R1 == 0 || R3 == 0))
895 return 0;
896
897 Vmax = (3300 * R2) / (R1 + R2);
898 Rpar = (R2 * R3) / (R3 + R2);
899 Vmin = (3300 * Rpar) / (R1 + Rpar);
900 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
901
902 *pValue = Vout;
903 }
904 }
905 return status;
906}
907
908static int load_firmware(struct drxd_state *state, const char *fw_name)
909{
910 const struct firmware *fw;
911
912 if (request_firmware(&fw, fw_name, state->dev) < 0) {
913 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
914 return -EIO;
915 }
916
917 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
918 if (state->microcode == NULL) {
919 release_firmware(fw);
920 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
921 return -ENOMEM;
922 }
923
924 state->microcode_length = fw->size;
925 release_firmware(fw);
926 return 0;
927}
928
929static int DownloadMicrocode(struct drxd_state *state,
930 const u8 *pMCImage, u32 Length)
931{
932 u8 *pSrc;
933 u32 Address;
934 u16 nBlocks;
935 u16 BlockSize;
936 u32 offset = 0;
937 int i, status = 0;
938
939 pSrc = (u8 *) pMCImage;
940
941
942 pSrc += sizeof(u16);
943 offset += sizeof(u16);
944 nBlocks = (pSrc[0] << 8) | pSrc[1];
945 pSrc += sizeof(u16);
946 offset += sizeof(u16);
947
948 for (i = 0; i < nBlocks; i++) {
949 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
950 (pSrc[2] << 8) | pSrc[3];
951 pSrc += sizeof(u32);
952 offset += sizeof(u32);
953
954 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
955 pSrc += sizeof(u16);
956 offset += sizeof(u16);
957
958
959
960 pSrc += sizeof(u16);
961 offset += sizeof(u16);
962
963
964
965 pSrc += sizeof(u16);
966 offset += sizeof(u16);
967
968 status = WriteBlock(state, Address, BlockSize,
969 pSrc, DRX_I2C_CLEARCRC);
970 if (status < 0)
971 break;
972 pSrc += BlockSize;
973 offset += BlockSize;
974 }
975
976 return status;
977}
978
979static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
980{
981 u32 nrRetries = 0;
982 u16 waitCmd;
983 int status;
984
985 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
986 if (status < 0)
987 return status;
988
989 do {
990 nrRetries += 1;
991 if (nrRetries > DRXD_MAX_RETRIES) {
992 status = -1;
993 break;
994 }
995 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
996 } while (waitCmd != 0);
997
998 if (status >= 0)
999 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
1000 return status;
1001}
1002
1003static int HI_CfgCommand(struct drxd_state *state)
1004{
1005 int status = 0;
1006
1007 mutex_lock(&state->mutex);
1008 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1009 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1010 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1011 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1012 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1013
1014 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1015
1016 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1017 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1018 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1019 HI_RA_RAM_SRV_CMD_CONFIG, 0);
1020 else
1021 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1022 mutex_unlock(&state->mutex);
1023 return status;
1024}
1025
1026static int InitHI(struct drxd_state *state)
1027{
1028 state->hi_cfg_wakeup_key = (state->chip_adr);
1029
1030 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1031 return HI_CfgCommand(state);
1032}
1033
1034static int HI_ResetCommand(struct drxd_state *state)
1035{
1036 int status;
1037
1038 mutex_lock(&state->mutex);
1039 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1040 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1041 if (status == 0)
1042 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1043 mutex_unlock(&state->mutex);
1044 msleep(1);
1045 return status;
1046}
1047
1048static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1049{
1050 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1051 if (bEnableBridge)
1052 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1053 else
1054 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1055
1056 return HI_CfgCommand(state);
1057}
1058
1059#define HI_TR_WRITE 0x9
1060#define HI_TR_READ 0xA
1061#define HI_TR_READ_WRITE 0xB
1062#define HI_TR_BROADCAST 0x4
1063
1064#if 0
1065static int AtomicReadBlock(struct drxd_state *state,
1066 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1067{
1068 int status;
1069 int i = 0;
1070
1071
1072 if ((!pData) || ((DataSize & 1) != 0))
1073 return -1;
1074
1075 mutex_lock(&state->mutex);
1076
1077 do {
1078
1079
1080 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1081 if (status < 0)
1082 break;
1083 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1084 if (status < 0)
1085 break;
1086 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1087 if (status < 0)
1088 break;
1089 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1090 if (status < 0)
1091 break;
1092 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1093 if (status < 0)
1094 break;
1095
1096 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1097 if (status < 0)
1098 break;
1099
1100 } while (0);
1101
1102 if (status >= 0) {
1103 for (i = 0; i < (DataSize / 2); i += 1) {
1104 u16 word;
1105
1106 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1107 &word, 0);
1108 if (status < 0)
1109 break;
1110 pData[2 * i] = (u8) (word & 0xFF);
1111 pData[(2 * i) + 1] = (u8) (word >> 8);
1112 }
1113 }
1114 mutex_unlock(&state->mutex);
1115 return status;
1116}
1117
1118static int AtomicReadReg32(struct drxd_state *state,
1119 u32 Addr, u32 *pData, u8 Flags)
1120{
1121 u8 buf[sizeof(u32)];
1122 int status;
1123
1124 if (!pData)
1125 return -1;
1126 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1127 *pData = (((u32) buf[0]) << 0) +
1128 (((u32) buf[1]) << 8) +
1129 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1130 return status;
1131}
1132#endif
1133
1134static int StopAllProcessors(struct drxd_state *state)
1135{
1136 return Write16(state, HI_COMM_EXEC__A,
1137 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1138}
1139
1140static int EnableAndResetMB(struct drxd_state *state)
1141{
1142 if (state->type_A) {
1143
1144 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1145 }
1146
1147
1148 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1149 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1150 return 0;
1151}
1152
1153static int InitCC(struct drxd_state *state)
1154{
1155 if (state->osc_clock_freq == 0 ||
1156 state->osc_clock_freq > 20000 ||
1157 (state->osc_clock_freq % 4000) != 0) {
1158 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1159 return -1;
1160 }
1161
1162 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1163 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1164 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1165 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1166 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1167 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1168
1169 return 0;
1170}
1171
1172static int ResetECOD(struct drxd_state *state)
1173{
1174 int status = 0;
1175
1176 if (state->type_A)
1177 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1178 else
1179 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1180
1181 if (!(status < 0))
1182 status = WriteTable(state, state->m_ResetECRAM);
1183 if (!(status < 0))
1184 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1185 return status;
1186}
1187
1188
1189
1190static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1191{
1192 int status;
1193 u16 AgModeLop = 0;
1194 u16 AgModeHip = 0;
1195 do {
1196 if (pgaSwitch) {
1197
1198
1199 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1200 if (status < 0)
1201 break;
1202 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1203 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1204 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1205 if (status < 0)
1206 break;
1207
1208
1209 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1210 if (status < 0)
1211 break;
1212 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1213 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1214 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1215 if (status < 0)
1216 break;
1217
1218
1219
1220 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1221 if (status < 0)
1222 break;
1223 } else {
1224
1225
1226
1227 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1228 if (status < 0)
1229 break;
1230 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1231 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1232 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1233 if (status < 0)
1234 break;
1235
1236
1237 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1238 if (status < 0)
1239 break;
1240 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1241 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1242 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1243 if (status < 0)
1244 break;
1245
1246
1247
1248 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1249 if (status < 0)
1250 break;
1251 }
1252 } while (0);
1253 return status;
1254}
1255
1256static int InitFE(struct drxd_state *state)
1257{
1258 int status;
1259
1260 do {
1261 status = WriteTable(state, state->m_InitFE_1);
1262 if (status < 0)
1263 break;
1264
1265 if (state->type_A) {
1266 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1267 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1268 0);
1269 } else {
1270 if (state->PGA)
1271 status = SetCfgPga(state, 0);
1272 else
1273 status =
1274 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1275 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1276 0);
1277 }
1278
1279 if (status < 0)
1280 break;
1281 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1282 if (status < 0)
1283 break;
1284 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1285 if (status < 0)
1286 break;
1287
1288 status = WriteTable(state, state->m_InitFE_2);
1289 if (status < 0)
1290 break;
1291
1292 } while (0);
1293
1294 return status;
1295}
1296
1297static int InitFT(struct drxd_state *state)
1298{
1299
1300
1301
1302
1303 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1304}
1305
1306static int SC_WaitForReady(struct drxd_state *state)
1307{
1308 u16 curCmd;
1309 int i;
1310
1311 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1312 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1313 if (status == 0 || curCmd == 0)
1314 return status;
1315 }
1316 return -1;
1317}
1318
1319static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1320{
1321 int status = 0;
1322 u16 errCode;
1323
1324 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1325 SC_WaitForReady(state);
1326
1327 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1328
1329 if (errCode == 0xFFFF) {
1330 printk(KERN_ERR "Command Error\n");
1331 status = -1;
1332 }
1333
1334 return status;
1335}
1336
1337static int SC_ProcStartCommand(struct drxd_state *state,
1338 u16 subCmd, u16 param0, u16 param1)
1339{
1340 int status = 0;
1341 u16 scExec;
1342
1343 mutex_lock(&state->mutex);
1344 do {
1345 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1346 if (scExec != 1) {
1347 status = -1;
1348 break;
1349 }
1350 SC_WaitForReady(state);
1351 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1352 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1353 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1354
1355 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1356 } while (0);
1357 mutex_unlock(&state->mutex);
1358 return status;
1359}
1360
1361static int SC_SetPrefParamCommand(struct drxd_state *state,
1362 u16 subCmd, u16 param0, u16 param1)
1363{
1364 int status;
1365
1366 mutex_lock(&state->mutex);
1367 do {
1368 status = SC_WaitForReady(state);
1369 if (status < 0)
1370 break;
1371 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1372 if (status < 0)
1373 break;
1374 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1375 if (status < 0)
1376 break;
1377 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1378 if (status < 0)
1379 break;
1380
1381 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1382 if (status < 0)
1383 break;
1384 } while (0);
1385 mutex_unlock(&state->mutex);
1386 return status;
1387}
1388
1389#if 0
1390static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1391{
1392 int status = 0;
1393
1394 mutex_lock(&state->mutex);
1395 do {
1396 status = SC_WaitForReady(state);
1397 if (status < 0)
1398 break;
1399 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1400 if (status < 0)
1401 break;
1402 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1403 if (status < 0)
1404 break;
1405 } while (0);
1406 mutex_unlock(&state->mutex);
1407 return status;
1408}
1409#endif
1410
1411static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1412{
1413 int status;
1414
1415 do {
1416 u16 EcOcRegIprInvMpg = 0;
1417 u16 EcOcRegOcModeLop = 0;
1418 u16 EcOcRegOcModeHip = 0;
1419 u16 EcOcRegOcMpgSio = 0;
1420
1421
1422
1423 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1424 if (bEnableOutput) {
1425 EcOcRegOcModeHip |=
1426 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1427 } else
1428 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1429 EcOcRegOcModeLop |=
1430 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1431 } else {
1432 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1433
1434 if (bEnableOutput)
1435 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1436 else
1437 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1438
1439
1440 if (state->insert_rs_byte) {
1441 EcOcRegOcModeLop &=
1442 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1443 EcOcRegOcModeHip &=
1444 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1445 EcOcRegOcModeHip |=
1446 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1447 } else {
1448 EcOcRegOcModeLop |=
1449 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1450 EcOcRegOcModeHip &=
1451 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1452 EcOcRegOcModeHip |=
1453 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1454 }
1455
1456
1457 if (state->enable_parallel)
1458 EcOcRegOcModeLop &=
1459 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1460 else
1461 EcOcRegOcModeLop |=
1462 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1463 }
1464
1465
1466 EcOcRegIprInvMpg &= (~(0x00FF));
1467
1468
1469
1470 EcOcRegIprInvMpg &= (~(0x0100));
1471
1472
1473
1474 EcOcRegIprInvMpg &= (~(0x0200));
1475
1476
1477
1478 EcOcRegIprInvMpg &= (~(0x0400));
1479
1480
1481
1482 EcOcRegIprInvMpg &= (~(0x0800));
1483
1484
1485 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1486 if (status < 0)
1487 break;
1488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1489 if (status < 0)
1490 break;
1491 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1492 if (status < 0)
1493 break;
1494 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1495 if (status < 0)
1496 break;
1497 } while (0);
1498 return status;
1499}
1500
1501static int SetDeviceTypeId(struct drxd_state *state)
1502{
1503 int status = 0;
1504 u16 deviceId = 0;
1505
1506 do {
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1508 if (status < 0)
1509 break;
1510
1511 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1512 if (status < 0)
1513 break;
1514 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1515
1516 state->type_A = 0;
1517 state->PGA = 0;
1518 state->diversity = 0;
1519 if (deviceId == 0) {
1520 state->type_A = 1;
1521 printk(KERN_INFO "DRX3975D-A2\n");
1522 } else {
1523 deviceId >>= 12;
1524 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1525 switch (deviceId) {
1526 case 4:
1527 state->diversity = 1;
1528
1529 case 3:
1530 case 7:
1531 state->PGA = 1;
1532 break;
1533 case 6:
1534 state->diversity = 1;
1535
1536 case 5:
1537 case 8:
1538 break;
1539 default:
1540 status = -1;
1541 break;
1542 }
1543 }
1544 } while (0);
1545
1546 if (status < 0)
1547 return status;
1548
1549
1550 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1551 state->m_InitSC = DRXD_InitSC;
1552 state->m_ResetECRAM = DRXD_ResetECRAM;
1553 if (state->type_A) {
1554 state->m_ResetCEFR = DRXD_ResetCEFR;
1555 state->m_InitFE_1 = DRXD_InitFEA2_1;
1556 state->m_InitFE_2 = DRXD_InitFEA2_2;
1557 state->m_InitCP = DRXD_InitCPA2;
1558 state->m_InitCE = DRXD_InitCEA2;
1559 state->m_InitEQ = DRXD_InitEQA2;
1560 state->m_InitEC = DRXD_InitECA2;
1561 if (load_firmware(state, DRX_FW_FILENAME_A2))
1562 return -EIO;
1563 } else {
1564 state->m_ResetCEFR = NULL;
1565 state->m_InitFE_1 = DRXD_InitFEB1_1;
1566 state->m_InitFE_2 = DRXD_InitFEB1_2;
1567 state->m_InitCP = DRXD_InitCPB1;
1568 state->m_InitCE = DRXD_InitCEB1;
1569 state->m_InitEQ = DRXD_InitEQB1;
1570 state->m_InitEC = DRXD_InitECB1;
1571 if (load_firmware(state, DRX_FW_FILENAME_B1))
1572 return -EIO;
1573 }
1574 if (state->diversity) {
1575 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1576 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1577 state->m_DisableDiversity = DRXD_DisableDiversity;
1578 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1579 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1580 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1581 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1582 } else {
1583 state->m_InitDiversityFront = NULL;
1584 state->m_InitDiversityEnd = NULL;
1585 state->m_DisableDiversity = NULL;
1586 state->m_StartDiversityFront = NULL;
1587 state->m_StartDiversityEnd = NULL;
1588 state->m_DiversityDelay8MHZ = NULL;
1589 state->m_DiversityDelay6MHZ = NULL;
1590 }
1591
1592 return status;
1593}
1594
1595static int CorrectSysClockDeviation(struct drxd_state *state)
1596{
1597 int status;
1598 s32 incr = 0;
1599 s32 nomincr = 0;
1600 u32 bandwidth = 0;
1601 u32 sysClockInHz = 0;
1602 u32 sysClockFreq = 0;
1603 s16 oscClockDeviation;
1604 s16 Diff;
1605
1606 do {
1607
1608
1609
1610
1611 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1612 if (status < 0)
1613 break;
1614 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1615 if (status < 0)
1616 break;
1617
1618 if (state->type_A) {
1619 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1620 break;
1621 } else {
1622 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1623 break;
1624 }
1625
1626 switch (state->props.bandwidth_hz) {
1627 case 8000000:
1628 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1629 break;
1630 case 7000000:
1631 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1632 break;
1633 case 6000000:
1634 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1635 break;
1636 default:
1637 return -1;
1638 break;
1639 }
1640
1641
1642
1643 incr += (1 << 23);
1644 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1645 sysClockFreq = (u32) (sysClockInHz / 1000);
1646
1647 if ((sysClockInHz % 1000) > 500)
1648 sysClockFreq++;
1649
1650
1651 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1652 (s32)
1653 (state->expected_sys_clock_freq)) *
1654 1000000L) /
1655 (s32)
1656 (state->expected_sys_clock_freq));
1657
1658 Diff = oscClockDeviation - state->osc_clock_deviation;
1659
1660 if (Diff >= -200 && Diff <= 200) {
1661 state->sys_clock_freq = (u16) sysClockFreq;
1662 if (oscClockDeviation != state->osc_clock_deviation) {
1663 if (state->config.osc_deviation) {
1664 state->config.osc_deviation(state->priv,
1665 oscClockDeviation,
1666 1);
1667 state->osc_clock_deviation =
1668 oscClockDeviation;
1669 }
1670 }
1671
1672 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1673 if (status < 0)
1674 break;
1675
1676
1677 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1678 if (status < 0)
1679 break;
1680 state->cscd_state = CSCD_SAVED;
1681 }
1682 } while (0);
1683
1684 return status;
1685}
1686
1687static int DRX_Stop(struct drxd_state *state)
1688{
1689 int status;
1690
1691 if (state->drxd_state != DRXD_STARTED)
1692 return 0;
1693
1694 do {
1695 if (state->cscd_state != CSCD_SAVED) {
1696 u32 lock;
1697 status = DRX_GetLockStatus(state, &lock);
1698 if (status < 0)
1699 break;
1700 }
1701
1702 status = StopOC(state);
1703 if (status < 0)
1704 break;
1705
1706 state->drxd_state = DRXD_STOPPED;
1707
1708 status = ConfigureMPEGOutput(state, 0);
1709 if (status < 0)
1710 break;
1711
1712 if (state->type_A) {
1713
1714 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1715 if (status < 0)
1716 break;
1717
1718 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1719 if (status < 0)
1720 break;
1721 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1722 if (status < 0)
1723 break;
1724 } else {
1725
1726 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1727 if (status < 0)
1728 break;
1729 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1730 if (status < 0)
1731 break;
1732 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1733 if (status < 0)
1734 break;
1735 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1736 if (status < 0)
1737 break;
1738 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1739 if (status < 0)
1740 break;
1741 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1742 if (status < 0)
1743 break;
1744 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1745 if (status < 0)
1746 break;
1747 }
1748
1749 } while (0);
1750 return status;
1751}
1752
1753#if 0
1754static int SetOperationMode(struct drxd_state *state, int oMode)
1755{
1756 int status;
1757
1758 do {
1759 if (state->drxd_state != DRXD_STOPPED) {
1760 status = -1;
1761 break;
1762 }
1763
1764 if (oMode == state->operation_mode) {
1765 status = 0;
1766 break;
1767 }
1768
1769 if (oMode != OM_Default && !state->diversity) {
1770 status = -1;
1771 break;
1772 }
1773
1774 switch (oMode) {
1775 case OM_DVBT_Diversity_Front:
1776 status = WriteTable(state, state->m_InitDiversityFront);
1777 break;
1778 case OM_DVBT_Diversity_End:
1779 status = WriteTable(state, state->m_InitDiversityEnd);
1780 break;
1781 case OM_Default:
1782
1783
1784 default:
1785 status = WriteTable(state, state->m_DisableDiversity);
1786 break;
1787 }
1788 } while (0);
1789
1790 if (!status)
1791 state->operation_mode = oMode;
1792 return status;
1793}
1794#endif
1795
1796static int StartDiversity(struct drxd_state *state)
1797{
1798 int status = 0;
1799 u16 rcControl;
1800
1801 do {
1802 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1803 status = WriteTable(state, state->m_StartDiversityFront);
1804 if (status < 0)
1805 break;
1806 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1807 status = WriteTable(state, state->m_StartDiversityEnd);
1808 if (status < 0)
1809 break;
1810 if (state->props.bandwidth_hz == 8000000) {
1811 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1812 if (status < 0)
1813 break;
1814 } else {
1815 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1816 if (status < 0)
1817 break;
1818 }
1819
1820 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1821 if (status < 0)
1822 break;
1823 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1824 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1825
1826 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1827 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1828 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1829 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1830 if (status < 0)
1831 break;
1832 }
1833 } while (0);
1834 return status;
1835}
1836
1837static int SetFrequencyShift(struct drxd_state *state,
1838 u32 offsetFreq, int channelMirrored)
1839{
1840 int negativeShift = (state->tuner_mirrors == channelMirrored);
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1854 offsetFreq,
1855 1 << 28, state->sys_clock_freq);
1856
1857 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1858 if (negativeShift)
1859 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1860
1861
1862
1863 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1864 1 << 28, state->sys_clock_freq);
1865
1866 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1867 if (negativeShift)
1868 state->org_fe_fs_add_incr = ((1L << 28) -
1869 state->org_fe_fs_add_incr);
1870
1871 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1872 state->fe_fs_add_incr, 0);
1873}
1874
1875static int SetCfgNoiseCalibration(struct drxd_state *state,
1876 struct SNoiseCal *noiseCal)
1877{
1878 u16 beOptEna;
1879 int status = 0;
1880
1881 do {
1882 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1883 if (status < 0)
1884 break;
1885 if (noiseCal->cpOpt) {
1886 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1887 } else {
1888 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1889 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1890 if (status < 0)
1891 break;
1892 }
1893 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1894 if (status < 0)
1895 break;
1896
1897 if (!state->type_A) {
1898 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1899 if (status < 0)
1900 break;
1901 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1902 if (status < 0)
1903 break;
1904 }
1905 } while (0);
1906
1907 return status;
1908}
1909
1910static int DRX_Start(struct drxd_state *state, s32 off)
1911{
1912 struct dtv_frontend_properties *p = &state->props;
1913 int status;
1914
1915 u16 transmissionParams = 0;
1916 u16 operationMode = 0;
1917 u16 qpskTdTpsPwr = 0;
1918 u16 qam16TdTpsPwr = 0;
1919 u16 qam64TdTpsPwr = 0;
1920 u32 feIfIncr = 0;
1921 u32 bandwidth = 0;
1922 int mirrorFreqSpect;
1923
1924 u16 qpskSnCeGain = 0;
1925 u16 qam16SnCeGain = 0;
1926 u16 qam64SnCeGain = 0;
1927 u16 qpskIsGainMan = 0;
1928 u16 qam16IsGainMan = 0;
1929 u16 qam64IsGainMan = 0;
1930 u16 qpskIsGainExp = 0;
1931 u16 qam16IsGainExp = 0;
1932 u16 qam64IsGainExp = 0;
1933 u16 bandwidthParam = 0;
1934
1935 if (off < 0)
1936 off = (off - 500) / 1000;
1937 else
1938 off = (off + 500) / 1000;
1939
1940 do {
1941 if (state->drxd_state != DRXD_STOPPED)
1942 return -1;
1943 status = ResetECOD(state);
1944 if (status < 0)
1945 break;
1946 if (state->type_A) {
1947 status = InitSC(state);
1948 if (status < 0)
1949 break;
1950 } else {
1951 status = InitFT(state);
1952 if (status < 0)
1953 break;
1954 status = InitCP(state);
1955 if (status < 0)
1956 break;
1957 status = InitCE(state);
1958 if (status < 0)
1959 break;
1960 status = InitEQ(state);
1961 if (status < 0)
1962 break;
1963 status = InitSC(state);
1964 if (status < 0)
1965 break;
1966 }
1967
1968
1969
1970 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1971 if (status < 0)
1972 break;
1973 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1974 if (status < 0)
1975 break;
1976
1977 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1978
1979 switch (p->transmission_mode) {
1980 default:
1981 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1982
1983
1984 case TRANSMISSION_MODE_8K:
1985 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1986 if (state->type_A) {
1987 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1988 if (status < 0)
1989 break;
1990 qpskSnCeGain = 99;
1991 qam16SnCeGain = 83;
1992 qam64SnCeGain = 67;
1993 }
1994 break;
1995 case TRANSMISSION_MODE_2K:
1996 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1997 if (state->type_A) {
1998 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1999 if (status < 0)
2000 break;
2001 qpskSnCeGain = 97;
2002 qam16SnCeGain = 71;
2003 qam64SnCeGain = 65;
2004 }
2005 break;
2006 }
2007
2008 switch (p->guard_interval) {
2009 case GUARD_INTERVAL_1_4:
2010 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2011 break;
2012 case GUARD_INTERVAL_1_8:
2013 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2014 break;
2015 case GUARD_INTERVAL_1_16:
2016 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2017 break;
2018 case GUARD_INTERVAL_1_32:
2019 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2020 break;
2021 default:
2022 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2023
2024 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2025 break;
2026 }
2027
2028 switch (p->hierarchy) {
2029 case HIERARCHY_1:
2030 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2031 if (state->type_A) {
2032 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2033 if (status < 0)
2034 break;
2035 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2036 if (status < 0)
2037 break;
2038
2039 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2040 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2041 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2042
2043 qpskIsGainMan =
2044 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2045 qam16IsGainMan =
2046 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2047 qam64IsGainMan =
2048 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2049
2050 qpskIsGainExp =
2051 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2052 qam16IsGainExp =
2053 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2054 qam64IsGainExp =
2055 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2056 }
2057 break;
2058
2059 case HIERARCHY_2:
2060 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2061 if (state->type_A) {
2062 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2063 if (status < 0)
2064 break;
2065 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2066 if (status < 0)
2067 break;
2068
2069 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2070 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2071 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2072
2073 qpskIsGainMan =
2074 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2075 qam16IsGainMan =
2076 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2077 qam64IsGainMan =
2078 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2079
2080 qpskIsGainExp =
2081 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2082 qam16IsGainExp =
2083 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2084 qam64IsGainExp =
2085 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2086 }
2087 break;
2088 case HIERARCHY_4:
2089 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2090 if (state->type_A) {
2091 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2092 if (status < 0)
2093 break;
2094 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2095 if (status < 0)
2096 break;
2097
2098 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2099 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2100 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2101
2102 qpskIsGainMan =
2103 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2104 qam16IsGainMan =
2105 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2106 qam64IsGainMan =
2107 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2108
2109 qpskIsGainExp =
2110 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2111 qam16IsGainExp =
2112 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2113 qam64IsGainExp =
2114 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2115 }
2116 break;
2117 case HIERARCHY_AUTO:
2118 default:
2119
2120 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2121 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2122 if (state->type_A) {
2123 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2124 if (status < 0)
2125 break;
2126 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2127 if (status < 0)
2128 break;
2129
2130 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2131 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2132 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2133
2134 qpskIsGainMan =
2135 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2136 qam16IsGainMan =
2137 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2138 qam64IsGainMan =
2139 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2140
2141 qpskIsGainExp =
2142 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2143 qam16IsGainExp =
2144 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2145 qam64IsGainExp =
2146 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2147 }
2148 break;
2149 }
2150 status = status;
2151 if (status < 0)
2152 break;
2153
2154 switch (p->modulation) {
2155 default:
2156 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2157
2158
2159 case QAM_64:
2160 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2161 if (state->type_A) {
2162 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2163 if (status < 0)
2164 break;
2165 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2166 if (status < 0)
2167 break;
2168 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2169 if (status < 0)
2170 break;
2171 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2172 if (status < 0)
2173 break;
2174 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2175 if (status < 0)
2176 break;
2177
2178 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2179 if (status < 0)
2180 break;
2181 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2182 if (status < 0)
2183 break;
2184 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2185 if (status < 0)
2186 break;
2187 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2188 if (status < 0)
2189 break;
2190 }
2191 break;
2192 case QPSK:
2193 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2194 if (state->type_A) {
2195 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2196 if (status < 0)
2197 break;
2198 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2199 if (status < 0)
2200 break;
2201 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2202 if (status < 0)
2203 break;
2204 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2205 if (status < 0)
2206 break;
2207 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2208 if (status < 0)
2209 break;
2210
2211 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2212 if (status < 0)
2213 break;
2214 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2215 if (status < 0)
2216 break;
2217 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2218 if (status < 0)
2219 break;
2220 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2221 if (status < 0)
2222 break;
2223 }
2224 break;
2225
2226 case QAM_16:
2227 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2228 if (state->type_A) {
2229 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2230 if (status < 0)
2231 break;
2232 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2233 if (status < 0)
2234 break;
2235 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2236 if (status < 0)
2237 break;
2238 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2239 if (status < 0)
2240 break;
2241 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2242 if (status < 0)
2243 break;
2244
2245 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2246 if (status < 0)
2247 break;
2248 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2249 if (status < 0)
2250 break;
2251 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2252 if (status < 0)
2253 break;
2254 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2255 if (status < 0)
2256 break;
2257 }
2258 break;
2259
2260 }
2261 status = status;
2262 if (status < 0)
2263 break;
2264
2265 switch (DRX_CHANNEL_HIGH) {
2266 default:
2267 case DRX_CHANNEL_AUTO:
2268 case DRX_CHANNEL_LOW:
2269 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2270 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2271 if (status < 0)
2272 break;
2273 break;
2274 case DRX_CHANNEL_HIGH:
2275 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2276 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2277 if (status < 0)
2278 break;
2279 break;
2280
2281 }
2282
2283 switch (p->code_rate_HP) {
2284 case FEC_1_2:
2285 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2286 if (state->type_A) {
2287 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2288 if (status < 0)
2289 break;
2290 }
2291 break;
2292 default:
2293 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2294
2295 case FEC_2_3:
2296 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2297 if (state->type_A) {
2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2299 if (status < 0)
2300 break;
2301 }
2302 break;
2303 case FEC_3_4:
2304 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2305 if (state->type_A) {
2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2307 if (status < 0)
2308 break;
2309 }
2310 break;
2311 case FEC_5_6:
2312 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2313 if (state->type_A) {
2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2315 if (status < 0)
2316 break;
2317 }
2318 break;
2319 case FEC_7_8:
2320 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2321 if (state->type_A) {
2322 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2323 if (status < 0)
2324 break;
2325 }
2326 break;
2327 }
2328 status = status;
2329 if (status < 0)
2330 break;
2331
2332
2333
2334
2335
2336
2337
2338
2339 switch (p->bandwidth_hz) {
2340 case 0:
2341 p->bandwidth_hz = 8000000;
2342
2343 case 8000000:
2344
2345 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2346
2347 bandwidthParam = 0;
2348 status = Write16(state,
2349 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2350 break;
2351 case 7000000:
2352
2353 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2354 bandwidthParam = 0x4807;
2355 status = Write16(state,
2356 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2357 break;
2358 case 6000000:
2359
2360 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2361 bandwidthParam = 0x0F07;
2362 status = Write16(state,
2363 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2364 break;
2365 default:
2366 status = -EINVAL;
2367 }
2368 if (status < 0)
2369 break;
2370
2371 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2372 if (status < 0)
2373 break;
2374
2375 {
2376 u16 sc_config;
2377 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2378 if (status < 0)
2379 break;
2380
2381
2382
2383 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2384 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2385
2386 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2387 } else {
2388
2389 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2390 }
2391 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2392 if (status < 0)
2393 break;
2394 }
2395
2396 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2397 if (status < 0)
2398 break;
2399
2400 if (state->cscd_state == CSCD_INIT) {
2401
2402 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2403 if (status < 0)
2404 break;
2405
2406 state->cscd_state = CSCD_SET;
2407 }
2408
2409
2410
2411
2412 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2413 (1ULL << 21), bandwidth) - (1 << 23);
2414 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2415 if (status < 0)
2416 break;
2417 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2418 if (status < 0)
2419 break;
2420
2421
2422
2423 SetFrequencyShift(state, off, mirrorFreqSpect);
2424
2425
2426
2427
2428 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2429 if (status < 0)
2430 break;
2431 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2432 if (status < 0)
2433 break;
2434
2435
2436#if 1
2437 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2438 SC_RA_RAM_OP_AUTO_GUARD__M |
2439 SC_RA_RAM_OP_AUTO_CONST__M |
2440 SC_RA_RAM_OP_AUTO_HIER__M |
2441 SC_RA_RAM_OP_AUTO_RATE__M);
2442#endif
2443 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2444 if (status < 0)
2445 break;
2446
2447
2448 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2449 if (status < 0)
2450 break;
2451
2452 status = StartOC(state);
2453 if (status < 0)
2454 break;
2455
2456 if (state->operation_mode != OM_Default) {
2457 status = StartDiversity(state);
2458 if (status < 0)
2459 break;
2460 }
2461
2462 state->drxd_state = DRXD_STARTED;
2463 } while (0);
2464
2465 return status;
2466}
2467
2468static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2469{
2470 u32 ulRfAgcOutputLevel = 0xffffffff;
2471 u32 ulRfAgcSettleLevel = 528;
2472 u32 ulRfAgcMinLevel = 0;
2473 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX;
2474 u32 ulRfAgcSpeed = 0;
2475 u32 ulRfAgcMode = 0;
2476 u32 ulRfAgcR1 = 820;
2477 u32 ulRfAgcR2 = 2200;
2478 u32 ulRfAgcR3 = 150;
2479 u32 ulIfAgcMode = 0;
2480 u32 ulIfAgcOutputLevel = 0xffffffff;
2481 u32 ulIfAgcSettleLevel = 0xffffffff;
2482 u32 ulIfAgcMinLevel = 0xffffffff;
2483 u32 ulIfAgcMaxLevel = 0xffffffff;
2484 u32 ulIfAgcSpeed = 0xffffffff;
2485 u32 ulIfAgcR1 = 820;
2486 u32 ulIfAgcR2 = 2200;
2487 u32 ulIfAgcR3 = 150;
2488 u32 ulClock = state->config.clock;
2489 u32 ulSerialMode = 0;
2490 u32 ulEcOcRegOcModeLop = 4;
2491 u32 ulHiI2cDelay = HI_I2C_DELAY;
2492 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2493 u32 ulHiI2cPatch = 0;
2494 u32 ulEnvironment = APPENV_PORTABLE;
2495 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2496 u32 ulIFFilter = IFFILTER_SAW;
2497
2498 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2499 state->if_agc_cfg.outputLevel = 0;
2500 state->if_agc_cfg.settleLevel = 140;
2501 state->if_agc_cfg.minOutputLevel = 0;
2502 state->if_agc_cfg.maxOutputLevel = 1023;
2503 state->if_agc_cfg.speed = 904;
2504
2505 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2506 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2507 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2508 }
2509
2510 if (ulIfAgcMode == 0 &&
2511 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2512 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2513 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2514 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2515 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2516 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2517 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2518 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2519 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2520 }
2521
2522 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2523 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2524 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2525
2526 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2527 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2528 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2529
2530 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2531
2532 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2533 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2534 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2535 }
2536
2537 if (ulRfAgcMode == 0 &&
2538 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2539 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2540 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2541 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2542 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2543 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2544 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2545 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2546 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2547 }
2548
2549 if (ulRfAgcMode == 2)
2550 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2551
2552 if (ulEnvironment <= 2)
2553 state->app_env_default = (enum app_env)
2554 (ulEnvironment);
2555 if (ulEnvironmentDiversity <= 2)
2556 state->app_env_diversity = (enum app_env)
2557 (ulEnvironmentDiversity);
2558
2559 if (ulIFFilter == IFFILTER_DISCRETE) {
2560
2561 state->noise_cal.cpOpt = 0;
2562 state->noise_cal.cpNexpOfs = 40;
2563 state->noise_cal.tdCal2k = -40;
2564 state->noise_cal.tdCal8k = -24;
2565 } else {
2566
2567 state->noise_cal.cpOpt = 1;
2568 state->noise_cal.cpNexpOfs = 0;
2569 state->noise_cal.tdCal2k = -21;
2570 state->noise_cal.tdCal8k = -24;
2571 }
2572 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2573
2574 state->chip_adr = (state->config.demod_address << 1) | 1;
2575 switch (ulHiI2cPatch) {
2576 case 1:
2577 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2578 break;
2579 case 3:
2580 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2581 break;
2582 default:
2583 state->m_HiI2cPatch = NULL;
2584 }
2585
2586
2587 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2588
2589 state->expected_sys_clock_freq = 48000;
2590
2591 state->sys_clock_freq = 48000;
2592 state->osc_clock_freq = (u16) ulClock;
2593 state->osc_clock_deviation = 0;
2594 state->cscd_state = CSCD_INIT;
2595 state->drxd_state = DRXD_UNINITIALIZED;
2596
2597 state->PGA = 0;
2598 state->type_A = 0;
2599 state->tuner_mirrors = 0;
2600
2601
2602 state->insert_rs_byte = state->config.insert_rs_byte;
2603 state->enable_parallel = (ulSerialMode != 1);
2604
2605
2606
2607
2608 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2609 ulHiI2cDelay) / 1000;
2610
2611
2612 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2613 ulHiI2cBridgeDelay) / 1000;
2614
2615 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2616
2617 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2618 return 0;
2619}
2620
2621static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2622{
2623 int status = 0;
2624 u32 driverVersion;
2625
2626 if (state->init_done)
2627 return 0;
2628
2629 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2630
2631 do {
2632 state->operation_mode = OM_Default;
2633
2634 status = SetDeviceTypeId(state);
2635 if (status < 0)
2636 break;
2637
2638
2639 if (!state->type_A && state->m_HiI2cPatch != NULL)
2640 status = WriteTable(state, state->m_HiI2cPatch);
2641 if (status < 0)
2642 break;
2643
2644 if (state->type_A) {
2645
2646
2647 status = Write16(state, 0x43012D, 0x047f, 0);
2648 if (status < 0)
2649 break;
2650 }
2651
2652 status = HI_ResetCommand(state);
2653 if (status < 0)
2654 break;
2655
2656 status = StopAllProcessors(state);
2657 if (status < 0)
2658 break;
2659 status = InitCC(state);
2660 if (status < 0)
2661 break;
2662
2663 state->osc_clock_deviation = 0;
2664
2665 if (state->config.osc_deviation)
2666 state->osc_clock_deviation =
2667 state->config.osc_deviation(state->priv, 0, 0);
2668 {
2669
2670 s32 devB;
2671 s32 devA = (s32) (state->osc_clock_deviation) *
2672 (s32) (state->expected_sys_clock_freq);
2673
2674 s32 deviation = (devA / (1000000L));
2675
2676 if (devA > 0)
2677 devB = (2);
2678 else
2679 devB = (-2);
2680 if ((devB * (devA % 1000000L) > 1000000L)) {
2681
2682 deviation += (devB / 2);
2683 }
2684
2685 state->sys_clock_freq =
2686 (u16) ((state->expected_sys_clock_freq) +
2687 deviation);
2688 }
2689 status = InitHI(state);
2690 if (status < 0)
2691 break;
2692 status = InitAtomicRead(state);
2693 if (status < 0)
2694 break;
2695
2696 status = EnableAndResetMB(state);
2697 if (status < 0)
2698 break;
2699 if (state->type_A)
2700 status = ResetCEFR(state);
2701 if (status < 0)
2702 break;
2703
2704 if (fw) {
2705 status = DownloadMicrocode(state, fw, fw_size);
2706 if (status < 0)
2707 break;
2708 } else {
2709 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2710 if (status < 0)
2711 break;
2712 }
2713
2714 if (state->PGA) {
2715 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2716 SetCfgPga(state, 0);
2717 } else {
2718 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2719 }
2720
2721 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2722
2723 status = InitFE(state);
2724 if (status < 0)
2725 break;
2726 status = InitFT(state);
2727 if (status < 0)
2728 break;
2729 status = InitCP(state);
2730 if (status < 0)
2731 break;
2732 status = InitCE(state);
2733 if (status < 0)
2734 break;
2735 status = InitEQ(state);
2736 if (status < 0)
2737 break;
2738 status = InitEC(state);
2739 if (status < 0)
2740 break;
2741 status = InitSC(state);
2742 if (status < 0)
2743 break;
2744
2745 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2746 if (status < 0)
2747 break;
2748 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2749 if (status < 0)
2750 break;
2751
2752 state->cscd_state = CSCD_INIT;
2753 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2754 if (status < 0)
2755 break;
2756 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2757 if (status < 0)
2758 break;
2759
2760 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2761 (VERSION_MAJOR % 10)) << 24;
2762 driverVersion += (((VERSION_MINOR / 10) << 4) +
2763 (VERSION_MINOR % 10)) << 16;
2764 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2765 ((VERSION_PATCH / 100) << 8) +
2766 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2767
2768 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2769 if (status < 0)
2770 break;
2771
2772 status = StopOC(state);
2773 if (status < 0)
2774 break;
2775
2776 state->drxd_state = DRXD_STOPPED;
2777 state->init_done = 1;
2778 status = 0;
2779 } while (0);
2780 return status;
2781}
2782
2783static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2784{
2785 DRX_GetLockStatus(state, pLockStatus);
2786
2787
2788 if (*pLockStatus & DRX_LOCK_FEC) {
2789 ConfigureMPEGOutput(state, 1);
2790
2791
2792 }
2793
2794 return 0;
2795}
2796
2797
2798
2799
2800
2801static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2802{
2803 struct drxd_state *state = fe->demodulator_priv;
2804 u32 value;
2805 int res;
2806
2807 res = ReadIFAgc(state, &value);
2808 if (res < 0)
2809 *strength = 0;
2810 else
2811 *strength = 0xffff - (value << 4);
2812 return 0;
2813}
2814
2815static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2816{
2817 struct drxd_state *state = fe->demodulator_priv;
2818 u32 lock;
2819
2820 DRXD_status(state, &lock);
2821 *status = 0;
2822
2823#if 1
2824 if (lock & DRX_LOCK_MPEG)
2825 *status |= FE_HAS_LOCK;
2826#else
2827 if (lock & DRX_LOCK_FEC)
2828 *status |= FE_HAS_LOCK;
2829#endif
2830 if (lock & DRX_LOCK_FEC)
2831 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2832 if (lock & DRX_LOCK_DEMOD)
2833 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2834
2835 return 0;
2836}
2837
2838static int drxd_init(struct dvb_frontend *fe)
2839{
2840 struct drxd_state *state = fe->demodulator_priv;
2841 int err = 0;
2842
2843
2844 return DRXD_init(state, 0, 0);
2845
2846 err = DRXD_init(state, state->fw->data, state->fw->size);
2847 release_firmware(state->fw);
2848 return err;
2849}
2850
2851int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2852{
2853 struct drxd_state *state = fe->demodulator_priv;
2854
2855 if (state->config.disable_i2c_gate_ctrl == 1)
2856 return 0;
2857
2858 return DRX_ConfigureI2CBridge(state, onoff);
2859}
2860EXPORT_SYMBOL(drxd_config_i2c);
2861
2862static int drxd_get_tune_settings(struct dvb_frontend *fe,
2863 struct dvb_frontend_tune_settings *sets)
2864{
2865 sets->min_delay_ms = 10000;
2866 sets->max_drift = 0;
2867 sets->step_size = 0;
2868 return 0;
2869}
2870
2871static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2872{
2873 *ber = 0;
2874 return 0;
2875}
2876
2877static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2878{
2879 *snr = 0;
2880 return 0;
2881}
2882
2883static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2884{
2885 *ucblocks = 0;
2886 return 0;
2887}
2888
2889static int drxd_sleep(struct dvb_frontend *fe)
2890{
2891 struct drxd_state *state = fe->demodulator_priv;
2892
2893 ConfigureMPEGOutput(state, 0);
2894 return 0;
2895}
2896
2897static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2898{
2899 return drxd_config_i2c(fe, enable);
2900}
2901
2902static int drxd_set_frontend(struct dvb_frontend *fe)
2903{
2904 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2905 struct drxd_state *state = fe->demodulator_priv;
2906 s32 off = 0;
2907
2908 state->props = *p;
2909 DRX_Stop(state);
2910
2911 if (fe->ops.tuner_ops.set_params) {
2912 fe->ops.tuner_ops.set_params(fe);
2913 if (fe->ops.i2c_gate_ctrl)
2914 fe->ops.i2c_gate_ctrl(fe, 0);
2915 }
2916
2917 msleep(200);
2918
2919 return DRX_Start(state, off);
2920}
2921
2922static void drxd_release(struct dvb_frontend *fe)
2923{
2924 struct drxd_state *state = fe->demodulator_priv;
2925
2926 kfree(state);
2927}
2928
2929static struct dvb_frontend_ops drxd_ops = {
2930 .delsys = { SYS_DVBT},
2931 .info = {
2932 .name = "Micronas DRXD DVB-T",
2933 .frequency_min = 47125000,
2934 .frequency_max = 855250000,
2935 .frequency_stepsize = 166667,
2936 .frequency_tolerance = 0,
2937 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2938 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2939 FE_CAN_FEC_AUTO |
2940 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2941 FE_CAN_QAM_AUTO |
2942 FE_CAN_TRANSMISSION_MODE_AUTO |
2943 FE_CAN_GUARD_INTERVAL_AUTO |
2944 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2945
2946 .release = drxd_release,
2947 .init = drxd_init,
2948 .sleep = drxd_sleep,
2949 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2950
2951 .set_frontend = drxd_set_frontend,
2952 .get_tune_settings = drxd_get_tune_settings,
2953
2954 .read_status = drxd_read_status,
2955 .read_ber = drxd_read_ber,
2956 .read_signal_strength = drxd_read_signal_strength,
2957 .read_snr = drxd_read_snr,
2958 .read_ucblocks = drxd_read_ucblocks,
2959};
2960
2961struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2962 void *priv, struct i2c_adapter *i2c,
2963 struct device *dev)
2964{
2965 struct drxd_state *state = NULL;
2966
2967 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2968 if (!state)
2969 return NULL;
2970 memset(state, 0, sizeof(*state));
2971
2972 state->ops = drxd_ops;
2973 state->dev = dev;
2974 state->config = *config;
2975 state->i2c = i2c;
2976 state->priv = priv;
2977
2978 mutex_init(&state->mutex);
2979
2980 if (Read16(state, 0, 0, 0) < 0)
2981 goto error;
2982
2983 state->frontend.ops = drxd_ops;
2984 state->frontend.demodulator_priv = state;
2985 ConfigureMPEGOutput(state, 0);
2986
2987 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2988 InitHI(state);
2989
2990 return &state->frontend;
2991
2992error:
2993 printk(KERN_ERR "drxd: not found\n");
2994 kfree(state);
2995 return NULL;
2996}
2997EXPORT_SYMBOL(drxd_attach);
2998
2999MODULE_DESCRIPTION("DRXD driver");
3000MODULE_AUTHOR("Micronas");
3001MODULE_LICENSE("GPL");
3002
