1/****************************************************************************/ 2 3/* 4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5 * processors. 6 * 7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9 */ 10 11/****************************************************************************/ 12#ifndef FEC_H 13#define FEC_H 14/****************************************************************************/ 15 16#include <linux/clocksource.h> 17#include <linux/net_tstamp.h> 18#include <linux/ptp_clock_kernel.h> 19#include <linux/timecounter.h> 20 21#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 22 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 23 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 24/* 25 * Just figures, Motorola would have to change the offsets for 26 * registers in the same peripheral device on different models 27 * of the ColdFire! 28 */ 29#define FEC_IEVENT 0x004 /* Interrupt event reg */ 30#define FEC_IMASK 0x008 /* Interrupt mask reg */ 31#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 32#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 33#define FEC_ECNTRL 0x024 /* Ethernet control reg */ 34#define FEC_MII_DATA 0x040 /* MII manage frame reg */ 35#define FEC_MII_SPEED 0x044 /* MII speed control reg */ 36#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 37#define FEC_R_CNTRL 0x084 /* Receive control reg */ 38#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 39#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 40#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 41#define FEC_OPD 0x0ec /* Opcode + Pause duration */ 42#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 43#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 44#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 45#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 46#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 47#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 48#define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 49#define FEC_R_DES_START 0x180 /* Receive descriptor ring */ 50#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ 51#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ 52#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 53#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 54#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 55#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 56#define FEC_RACC 0x1C4 /* Receive Accelerator function */ 57#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 58#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 59 60#define BM_MIIGSK_CFGR_MII 0x00 61#define BM_MIIGSK_CFGR_RMII 0x01 62#define BM_MIIGSK_CFGR_FRCONT_10M 0x40 63 64#else 65 66#define FEC_ECNTRL 0x000 /* Ethernet control reg */ 67#define FEC_IEVENT 0x004 /* Interrupt even reg */ 68#define FEC_IMASK 0x008 /* Interrupt mask reg */ 69#define FEC_IVEC 0x00c /* Interrupt vec status reg */ 70#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 71#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 72#define FEC_MII_DATA 0x040 /* MII manage frame reg */ 73#define FEC_MII_SPEED 0x044 /* MII speed control reg */ 74#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 75#define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 76#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 77#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 78#define FEC_R_CNTRL 0x104 /* Receive control reg */ 79#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 80#define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 81#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 82#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 83#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 84#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 85#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ 86#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ 87#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ 88#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 89 90#endif /* CONFIG_M5272 */ 91 92 93/* 94 * Define the buffer descriptor structure. 95 */ 96#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 97struct bufdesc { 98 unsigned short cbd_datlen; /* Data length */ 99 unsigned short cbd_sc; /* Control and status info */ 100 unsigned long cbd_bufaddr; /* Buffer address */ 101}; 102#else 103struct bufdesc { 104 unsigned short cbd_sc; /* Control and status info */ 105 unsigned short cbd_datlen; /* Data length */ 106 unsigned long cbd_bufaddr; /* Buffer address */ 107}; 108#endif 109 110struct bufdesc_ex { 111 struct bufdesc desc; 112 unsigned long cbd_esc; 113 unsigned long cbd_prot; 114 unsigned long cbd_bdu; 115 unsigned long ts; 116 unsigned short res0[4]; 117}; 118 119/* 120 * The following definitions courtesy of commproc.h, which where 121 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 122 */ 123#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 124#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 125#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 126#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 127#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 128#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 129#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 130#define BD_SC_BR ((ushort)0x0020) /* Break received */ 131#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 132#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 133#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 134#define BD_SC_CD ((ushort)0x0001) /* ?? */ 135 136/* Buffer descriptor control/status used by Ethernet receive. 137*/ 138#define BD_ENET_RX_EMPTY ((ushort)0x8000) 139#define BD_ENET_RX_WRAP ((ushort)0x2000) 140#define BD_ENET_RX_INTR ((ushort)0x1000) 141#define BD_ENET_RX_LAST ((ushort)0x0800) 142#define BD_ENET_RX_FIRST ((ushort)0x0400) 143#define BD_ENET_RX_MISS ((ushort)0x0100) 144#define BD_ENET_RX_LG ((ushort)0x0020) 145#define BD_ENET_RX_NO ((ushort)0x0010) 146#define BD_ENET_RX_SH ((ushort)0x0008) 147#define BD_ENET_RX_CR ((ushort)0x0004) 148#define BD_ENET_RX_OV ((ushort)0x0002) 149#define BD_ENET_RX_CL ((ushort)0x0001) 150#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 151 152/* Buffer descriptor control/status used by Ethernet transmit. 153*/ 154#define BD_ENET_TX_READY ((ushort)0x8000) 155#define BD_ENET_TX_PAD ((ushort)0x4000) 156#define BD_ENET_TX_WRAP ((ushort)0x2000) 157#define BD_ENET_TX_INTR ((ushort)0x1000) 158#define BD_ENET_TX_LAST ((ushort)0x0800) 159#define BD_ENET_TX_TC ((ushort)0x0400) 160#define BD_ENET_TX_DEF ((ushort)0x0200) 161#define BD_ENET_TX_HB ((ushort)0x0100) 162#define BD_ENET_TX_LC ((ushort)0x0080) 163#define BD_ENET_TX_RL ((ushort)0x0040) 164#define BD_ENET_TX_RCMASK ((ushort)0x003c) 165#define BD_ENET_TX_UN ((ushort)0x0002) 166#define BD_ENET_TX_CSL ((ushort)0x0001) 167#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 168 169/*enhanced buffer descriptor control/status used by Ethernet transmit*/ 170#define BD_ENET_TX_INT 0x40000000 171#define BD_ENET_TX_TS 0x20000000 172#define BD_ENET_TX_PINS 0x10000000 173#define BD_ENET_TX_IINS 0x08000000 174 175 176/* This device has up to three irqs on some platforms */ 177#define FEC_IRQ_NUM 3 178 179/* The number of Tx and Rx buffers. These are allocated from the page 180 * pool. The code may assume these are power of two, so it it best 181 * to keep them that size. 182 * We don't need to allocate pages for the transmitter. We just use 183 * the skbuffer directly. 184 */ 185 186#define FEC_ENET_RX_PAGES 8 187#define FEC_ENET_RX_FRSIZE 2048 188#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 189#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 190#define FEC_ENET_TX_FRSIZE 2048 191#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 192#define TX_RING_SIZE 16 /* Must be power of two */ 193#define TX_RING_MOD_MASK 15 /* for this to work */ 194 195#define BD_ENET_RX_INT 0x00800000 196#define BD_ENET_RX_PTP ((ushort)0x0400) 197#define BD_ENET_RX_ICE 0x00000020 198#define BD_ENET_RX_PCR 0x00000010 199#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 200#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 201 202struct fec_enet_delayed_work { 203 struct delayed_work delay_work; 204 bool timeout; 205}; 206 207/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 208 * tx_bd_base always point to the base of the buffer descriptors. The 209 * cur_rx and cur_tx point to the currently available buffer. 210 * The dirty_tx tracks the current buffer that is being sent by the 211 * controller. The cur_tx and dirty_tx are equal under both completely 212 * empty and completely full conditions. The empty/ready indicator in 213 * the buffer descriptor determines the actual condition. 214 */ 215struct fec_enet_private { 216 /* Hardware registers of the FEC device */ 217 void __iomem *hwp; 218 219 struct net_device *netdev; 220 221 struct clk *clk_ipg; 222 struct clk *clk_ahb; 223 struct clk *clk_enet_out; 224 struct clk *clk_ptp; 225 226 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 227 unsigned char *tx_bounce[TX_RING_SIZE]; 228 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 229 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 230 231 /* CPM dual port RAM relative addresses */ 232 dma_addr_t bd_dma; 233 /* Address of Rx and Tx buffers */ 234 struct bufdesc *rx_bd_base; 235 struct bufdesc *tx_bd_base; 236 /* The next free ring entry */ 237 struct bufdesc *cur_rx, *cur_tx; 238 /* The ring entries to be free()ed */ 239 struct bufdesc *dirty_tx; 240 241 struct platform_device *pdev; 242 243 int opened; 244 int dev_id; 245 246 /* Phylib and MDIO interface */ 247 struct mii_bus *mii_bus; 248 struct phy_device *phy_dev; 249 int mii_timeout; 250 uint phy_speed; 251 phy_interface_t phy_interface; 252 int link; 253 int full_duplex; 254 int speed; 255 struct completion mdio_done; 256 int irq[FEC_IRQ_NUM]; 257 int bufdesc_ex; 258 int pause_flag; 259 260 struct napi_struct napi; 261 int csum_flags; 262 263 struct ptp_clock *ptp_clock; 264 struct ptp_clock_info ptp_caps; 265 unsigned long last_overflow_check; 266 spinlock_t tmreg_lock; 267 struct cyclecounter cc; 268 struct timecounter tc; 269 int rx_hwtstamp_filter; 270 u32 base_incval; 271 u32 cycle_speed; 272 int hwts_rx_en; 273 int hwts_tx_en; 274 struct timer_list time_keep; 275 struct fec_enet_delayed_work delay_work; 276}; 277 278void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev); 279void fec_ptp_start_cyclecounter(struct net_device *ndev); 280int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd); 281 282/****************************************************************************/ 283#endif /* FEC_H */ 284