LXR linux/drivers/net/ethernet/intel/ice/ice

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4#ifndef _ICE_CONTROLQ_H_
   5#define _ICE_CONTROLQ_H_
   6
   7#include "ice_adminq_cmd.h"
   8
   9/* Maximum buffer lengths for all control queue types */
  10#define ICE_AQ_MAX_BUF_LEN 4096
  11#define ICE_MBXQ_MAX_BUF_LEN 4096
  12
  13#define ICE_CTL_Q_DESC(R, i) \
  14        (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
  15
  16#define ICE_CTL_Q_DESC_UNUSED(R) \
  17        (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  18              (R)->next_to_clean - (R)->next_to_use - 1)
  19
  20/* Defines that help manage the driver vs FW API checks.
  21 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
  22 */
  23#define EXP_FW_API_VER_BRANCH           0x00
  24#define EXP_FW_API_VER_MAJOR            0x01
  25#define EXP_FW_API_VER_MINOR            0x03
  26
  27/* Different control queue types: These are mainly for SW consumption. */
  28enum ice_ctl_q {
  29        ICE_CTL_Q_UNKNOWN = 0,
  30        ICE_CTL_Q_ADMIN,
  31        ICE_CTL_Q_MAILBOX,
  32};
  33
  34/* Control Queue default settings */
  35#define ICE_CTL_Q_SQ_CMD_TIMEOUT        250  /* msecs */
  36
  37struct ice_ctl_q_ring {
  38        void *dma_head;                 /* Virtual address to dma head */
  39        struct ice_dma_mem desc_buf;    /* descriptor ring memory */
  40        void *cmd_buf;                  /* command buffer memory */
  41
  42        union {
  43                struct ice_dma_mem *sq_bi;
  44                struct ice_dma_mem *rq_bi;
  45        } r;
  46
  47        u16 count;              /* Number of descriptors */
  48
  49        /* used for interrupt processing */
  50        u16 next_to_use;
  51        u16 next_to_clean;
  52
  53        /* used for queue tracking */
  54        u32 head;
  55        u32 tail;
  56        u32 len;
  57        u32 bah;
  58        u32 bal;
  59        u32 len_mask;
  60        u32 len_ena_mask;
  61        u32 head_mask;
  62};
  63
  64/* sq transaction details */
  65struct ice_sq_cd {
  66        struct ice_aq_desc *wb_desc;
  67};
  68
  69#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
  70
  71/* rq event information */
  72struct ice_rq_event_info {
  73        struct ice_aq_desc desc;
  74        u16 msg_len;
  75        u16 buf_len;
  76        u8 *msg_buf;
  77};
  78
  79/* Control Queue information */
  80struct ice_ctl_q_info {
  81        enum ice_ctl_q qtype;
  82        struct ice_ctl_q_ring rq;       /* receive queue */
  83        struct ice_ctl_q_ring sq;       /* send queue */
  84        u32 sq_cmd_timeout;             /* send queue cmd write back timeout */
  85        u16 num_rq_entries;             /* receive queue depth */
  86        u16 num_sq_entries;             /* send queue depth */
  87        u16 rq_buf_size;                /* receive queue buffer size */
  88        u16 sq_buf_size;                /* send queue buffer size */
  89        struct mutex sq_lock;           /* Send queue lock */
  90        struct mutex rq_lock;           /* Receive queue lock */
  91        enum ice_aq_err sq_last_status; /* last status on send queue */
  92        enum ice_aq_err rq_last_status; /* last status on receive queue */
  93};
  94
  95#endif /* _ICE_CONTROLQ_H_ */
  96