LXR linux/drivers/net/ethernet/ti/cpts.h

   1/*
   2 * TI Common Platform Time Sync
   3 *
   4 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19 */
  20#ifndef _TI_CPTS_H_
  21#define _TI_CPTS_H_
  22
  23#include <linux/clk.h>
  24#include <linux/clkdev.h>
  25#include <linux/clocksource.h>
  26#include <linux/device.h>
  27#include <linux/list.h>
  28#include <linux/ptp_clock_kernel.h>
  29#include <linux/skbuff.h>
  30#include <linux/timecounter.h>
  31
  32struct cpsw_cpts {
  33        u32 idver;                /* Identification and version */
  34        u32 control;              /* Time sync control */
  35        u32 res1;
  36        u32 ts_push;              /* Time stamp event push */
  37        u32 ts_load_val;          /* Time stamp load value */
  38        u32 ts_load_en;           /* Time stamp load enable */
  39        u32 res2[2];
  40        u32 intstat_raw;          /* Time sync interrupt status raw */
  41        u32 intstat_masked;       /* Time sync interrupt status masked */
  42        u32 int_enable;           /* Time sync interrupt enable */
  43        u32 res3;
  44        u32 event_pop;            /* Event interrupt pop */
  45        u32 event_low;            /* 32 Bit Event Time Stamp */
  46        u32 event_high;           /* Event Type Fields */
  47};
  48
  49/* Bit definitions for the IDVER register */
  50#define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
  51#define TX_IDENT_MASK        (0xffff)
  52#define RTL_VER_SHIFT        (11)    /* RTL Version Value */
  53#define RTL_VER_MASK         (0x1f)
  54#define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
  55#define MAJOR_VER_MASK       (0x7)
  56#define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
  57#define MINOR_VER_MASK       (0xff)
  58
  59/* Bit definitions for the CONTROL register */
  60#define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
  61#define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
  62#define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
  63#define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
  64#define INT_TEST             (1<<1)  /* Interrupt Test */
  65#define CPTS_EN              (1<<0)  /* Time Sync Enable */
  66
  67/*
  68 * Definitions for the single bit resisters:
  69 * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
  70 */
  71#define TS_PUSH             (1<<0)  /* Time stamp event push */
  72#define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
  73#define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
  74#define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
  75#define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
  76#define EVENT_POP           (1<<0)  /* writing discards one event */
  77
  78/* Bit definitions for the EVENT_HIGH register */
  79#define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
  80#define PORT_NUMBER_MASK     (0x1f)
  81#define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
  82#define EVENT_TYPE_MASK      (0xf)
  83#define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
  84#define MESSAGE_TYPE_MASK    (0xf)
  85#define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
  86#define SEQUENCE_ID_MASK     (0xffff)
  87
  88enum {
  89        CPTS_EV_PUSH, /* Time Stamp Push Event */
  90        CPTS_EV_ROLL, /* Time Stamp Rollover Event */
  91        CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
  92        CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
  93        CPTS_EV_RX,   /* Ethernet Receive Event */
  94        CPTS_EV_TX,   /* Ethernet Transmit Event */
  95};
  96
  97/* This covers any input clock up to about 500 MHz. */
  98#define CPTS_OVERFLOW_PERIOD (HZ * 8)
  99
 100#define CPTS_FIFO_DEPTH 16
 101#define CPTS_MAX_EVENTS 32
 102
 103struct cpts_event {
 104        struct list_head list;
 105        unsigned long tmo;
 106        u32 high;
 107        u32 low;
 108};
 109
 110struct cpts {
 111        struct cpsw_cpts __iomem *reg;
 112        int tx_enable;
 113        int rx_enable;
 114#ifdef CONFIG_TI_CPTS
 115        struct ptp_clock_info info;
 116        struct ptp_clock *clock;
 117        spinlock_t lock; /* protects time registers */
 118        u32 cc_mult; /* for the nominal frequency */
 119        struct cyclecounter cc;
 120        struct timecounter tc;
 121        struct delayed_work overflow_work;
 122        int phc_index;
 123        struct clk *refclk;
 124        struct list_head events;
 125        struct list_head pool;
 126        struct cpts_event pool_data[CPTS_MAX_EVENTS];
 127#endif
 128};
 129
 130#ifdef CONFIG_TI_CPTS
 131extern void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
 132extern void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
 133#else
 134static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
 135{
 136}
 137static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
 138{
 139}
 140#endif
 141
 142extern int cpts_register(struct device *dev, struct cpts *cpts,
 143                         u32 mult, u32 shift);
 144extern void cpts_unregister(struct cpts *cpts);
 145
 146#endif
 147