1
2
3
4
5#include "main.h"
6#include "fw.h"
7#include "tx.h"
8#include "rx.h"
9#include "phy.h"
10#include "rtw8822c.h"
11#include "rtw8822c_table.h"
12#include "mac.h"
13#include "reg.h"
14#include "debug.h"
15
16static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
17 u8 rx_path, bool is_tx2_path);
18
19static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
20 struct rtw8822c_efuse *map)
21{
22 ether_addr_copy(efuse->addr, map->e.mac_addr);
23}
24
25static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
26{
27 struct rtw_efuse *efuse = &rtwdev->efuse;
28 struct rtw8822c_efuse *map;
29 int i;
30
31 map = (struct rtw8822c_efuse *)log_map;
32
33 efuse->rfe_option = map->rfe_option;
34 efuse->crystal_cap = map->xtal_k;
35 efuse->channel_plan = map->channel_plan;
36 efuse->country_code[0] = map->country_code[0];
37 efuse->country_code[1] = map->country_code[1];
38 efuse->bt_setting = map->rf_bt_setting;
39 efuse->regd = map->rf_board_option & 0x7;
40
41 for (i = 0; i < 4; i++)
42 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
43
44 switch (rtw_hci_type(rtwdev)) {
45 case RTW_HCI_TYPE_PCIE:
46 rtw8822ce_efuse_parsing(efuse, map);
47 break;
48 default:
49
50 return -ENOTSUPP;
51 }
52
53 return 0;
54}
55
56static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
57{
58 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
59 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
60 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
61 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
62
63 if (pre)
64 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
65 else
66 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
67}
68
69static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
70 struct rtw_backup_info *backup,
71 struct rtw_backup_info *backup_rf)
72{
73 u32 path, i;
74 u32 val;
75 u32 reg;
76 u32 rf_addr[DACK_RF_8822C] = {0x8f};
77 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
78 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
79 0x1a00, 0x1a14, 0x1d58, 0x1c38,
80 0x1e24, 0x1e28, 0x1860, 0x4160};
81
82 for (i = 0; i < DACK_REG_8822C; i++) {
83 backup[i].len = 4;
84 backup[i].reg = addrs[i];
85 backup[i].val = rtw_read32(rtwdev, addrs[i]);
86 }
87
88 for (path = 0; path < DACK_PATH_8822C; path++) {
89 for (i = 0; i < DACK_RF_8822C; i++) {
90 reg = rf_addr[i];
91 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
92 backup_rf[path * i + i].reg = reg;
93 backup_rf[path * i + i].val = val;
94 }
95 }
96}
97
98static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
99 struct rtw_backup_info *backup,
100 struct rtw_backup_info *backup_rf)
101{
102 u32 path, i;
103 u32 val;
104 u32 reg;
105
106 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
107
108 for (path = 0; path < DACK_PATH_8822C; path++) {
109 for (i = 0; i < DACK_RF_8822C; i++) {
110 val = backup_rf[path * i + i].val;
111 reg = backup_rf[path * i + i].reg;
112 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
113 }
114 }
115}
116
117static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
118 u32 *min, u32 *max)
119{
120 if (value >= 0x200) {
121 if (*min >= 0x200) {
122 if (*min > value)
123 *min = value;
124 } else {
125 *min = value;
126 }
127 if (*max >= 0x200) {
128 if (*max < value)
129 *max = value;
130 }
131 } else {
132 if (*min < 0x200) {
133 if (*min > value)
134 *min = value;
135 }
136
137 if (*max >= 0x200) {
138 *max = value;
139 } else {
140 if (*max < value)
141 *max = value;
142 }
143 }
144}
145
146static void swap_u32(u32 *v1, u32 *v2)
147{
148 u32 tmp;
149
150 tmp = *v1;
151 *v1 = *v2;
152 *v2 = tmp;
153}
154
155static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
156{
157 if (*v1 >= 0x200 && *v2 >= 0x200) {
158 if (*v1 > *v2)
159 swap_u32(v1, v2);
160 } else if (*v1 < 0x200 && *v2 < 0x200) {
161 if (*v1 > *v2)
162 swap_u32(v1, v2);
163 } else if (*v1 < 0x200 && *v2 >= 0x200) {
164 swap_u32(v1, v2);
165 }
166}
167
168static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
169{
170 u32 i, j;
171
172 for (i = 0; i < DACK_SN_8822C - 1; i++) {
173 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
174 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
175 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
176 }
177 }
178}
179
180static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
181{
182 u32 p, m, t, i;
183
184 m = 0;
185 p = 0;
186 for (i = 10; i < DACK_SN_8822C - 10; i++) {
187 if (vec[i] > 0x200)
188 m = (0x400 - vec[i]) + m;
189 else
190 p = vec[i] + p;
191 }
192
193 if (p > m) {
194 t = p - m;
195 t = t / (DACK_SN_8822C - 20);
196 } else {
197 t = m - p;
198 t = t / (DACK_SN_8822C - 20);
199 if (t != 0x0)
200 t = 0x400 - t;
201 }
202
203 *val = t;
204}
205
206static u32 rtw8822c_get_path_base_addr(u8 path)
207{
208 u32 base_addr;
209
210 switch (path) {
211 case RF_PATH_A:
212 base_addr = 0x1800;
213 break;
214 case RF_PATH_B:
215 base_addr = 0x4100;
216 break;
217 default:
218 WARN_ON(1);
219 return -1;
220 }
221
222 return base_addr;
223}
224
225static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
226{
227 bool ret = true;
228
229 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
230 (value < 0x200 && value > 0x64)) {
231 ret = false;
232 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
233 }
234
235 return ret;
236}
237
238static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
239{
240 u32 temp;
241 int i = 0, cnt = 0;
242
243 while (i < DACK_SN_8822C && cnt < 10000) {
244 cnt++;
245 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
246 iv[i] = (temp & 0x3ff000) >> 12;
247 qv[i] = temp & 0x3ff;
248
249 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
250 rtw8822c_dac_iq_check(rtwdev, qv[i]))
251 i++;
252 }
253}
254
255static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
256 u32 *iv, u32 *qv,
257 u32 *i_value, u32 *q_value)
258{
259 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
260 u32 i_delta, q_delta;
261 u32 temp;
262 int i, cnt = 0;
263
264 do {
265 i_min = iv[0];
266 i_max = iv[0];
267 q_min = qv[0];
268 q_max = qv[0];
269 for (i = 0; i < DACK_SN_8822C; i++) {
270 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
271 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
272 }
273
274 if (i_max < 0x200 && i_min < 0x200)
275 i_delta = i_max - i_min;
276 else if (i_max >= 0x200 && i_min >= 0x200)
277 i_delta = i_max - i_min;
278 else
279 i_delta = i_max + (0x400 - i_min);
280
281 if (q_max < 0x200 && q_min < 0x200)
282 q_delta = q_max - q_min;
283 else if (q_max >= 0x200 && q_min >= 0x200)
284 q_delta = q_max - q_min;
285 else
286 q_delta = q_max + (0x400 - q_min);
287
288 rtw_dbg(rtwdev, RTW_DBG_RFK,
289 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
290 i_min, i_max, i_delta);
291 rtw_dbg(rtwdev, RTW_DBG_RFK,
292 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
293 q_min, q_max, q_delta);
294
295 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
296
297 if (i_delta > 5 || q_delta > 5) {
298 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
299 iv[0] = (temp & 0x3ff000) >> 12;
300 qv[0] = temp & 0x3ff;
301 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
302 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
303 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
304 } else {
305 break;
306 }
307 } while (cnt++ < 100);
308
309 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
310 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
311}
312
313static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
314 u32 *i_value, u32 *q_value)
315{
316 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
317 u32 rf_a, rf_b;
318
319 mdelay(10);
320
321 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
322 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
323
324 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
325 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
326
327 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
328 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
329}
330
331static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
332{
333 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
334 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
335 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
336 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
337 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
338 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
339 rtw_write32(rtwdev, 0x1b00, 0x00000008);
340 rtw_write8(rtwdev, 0x1bcc, 0x3f);
341 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
342 rtw_write8(rtwdev, 0x1bcc, 0x3f);
343 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
344 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
345}
346
347static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
348 u8 path, u32 *adc_ic, u32 *adc_qc)
349{
350 u32 ic = 0, qc = 0, temp = 0;
351 u32 base_addr;
352 u32 path_sel;
353 int i;
354
355 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
356
357 base_addr = rtw8822c_get_path_base_addr(path);
358 switch (path) {
359 case RF_PATH_A:
360 path_sel = 0xa0000;
361 break;
362 case RF_PATH_B:
363 path_sel = 0x80000;
364 break;
365 default:
366 WARN_ON(1);
367 return;
368 }
369
370
371 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
372 if (path == RF_PATH_B)
373 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
374 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
375 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
376 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
377 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
378 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
379 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
380 for (i = 0; i < 10; i++) {
381 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
382 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
383 rtw_write32(rtwdev, 0x1c24, 0x00010002);
384 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
385 rtw_dbg(rtwdev, RTW_DBG_RFK,
386 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
387
388
389 if (ic != 0x0) {
390 ic = 0x400 - ic;
391 *adc_ic = ic;
392 }
393 if (qc != 0x0) {
394 qc = 0x400 - qc;
395 *adc_qc = qc;
396 }
397 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
398 rtw_write32(rtwdev, base_addr + 0x68, temp);
399 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
400 base_addr + 0x68, temp);
401
402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
403 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
404 rtw_dbg(rtwdev, RTW_DBG_RFK,
405 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
406 if (ic >= 0x200)
407 ic = 0x400 - ic;
408 if (qc >= 0x200)
409 qc = 0x400 - qc;
410 if (ic < 5 && qc < 5)
411 break;
412 }
413
414
415 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
416 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
417 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
418
419
420 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
421}
422
423static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
424{
425 u32 base_addr;
426
427 base_addr = rtw8822c_get_path_base_addr(path);
428
429 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
430 if (path == RF_PATH_A) {
431 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
432 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
433 }
434 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
435 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
436 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
437 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
438 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
439 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
440 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
441 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
442 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
443 mdelay(2);
444 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
445 mdelay(2);
446 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
447 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
448 mdelay(1);
449 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
450 mdelay(20);
451 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
452 mdelay(20);
453 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
454 mdelay(20);
455 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
456 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
457 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
458 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
459 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
460}
461
462static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
463 u8 path, u32 *ic_out, u32 *qc_out)
464{
465 u32 base_addr;
466 u32 ic, qc, ic_in, qc_in;
467
468 base_addr = rtw8822c_get_path_base_addr(path);
469 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
470 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
471 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
472 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
473
474 rtw_write32(rtwdev, 0x1b00, 0x00000008);
475 rtw_write8(rtwdev, 0x1bcc, 0x03f);
476 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
477 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
478 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
479
480 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
481 ic = ic_in;
482 qc = qc_in;
483
484
485 if (ic != 0x0)
486 ic = 0x400 - ic;
487 if (qc != 0x0)
488 qc = 0x400 - qc;
489 if (ic < 0x300) {
490 ic = ic * 2 * 6 / 5;
491 ic = ic + 0x80;
492 } else {
493 ic = (0x400 - ic) * 2 * 6 / 5;
494 ic = 0x7f - ic;
495 }
496 if (qc < 0x300) {
497 qc = qc * 2 * 6 / 5;
498 qc = qc + 0x80;
499 } else {
500 qc = (0x400 - qc) * 2 * 6 / 5;
501 qc = 0x7f - qc;
502 }
503
504 *ic_out = ic;
505 *qc_out = qc;
506
507 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
508 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
509}
510
511static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
512 u32 adc_ic, u32 adc_qc,
513 u32 *ic_in, u32 *qc_in,
514 u32 *i_out, u32 *q_out)
515{
516 u32 base_addr;
517 u32 ic, qc;
518 u32 temp;
519
520 base_addr = rtw8822c_get_path_base_addr(path);
521 ic = *ic_in;
522 qc = *qc_in;
523
524 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
525 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
526 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
527 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
528 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
529 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
530 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
531 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
532 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
533 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
534 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
535 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
536 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
537 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
538 mdelay(2);
539 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
540 mdelay(2);
541 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
542 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
543 mdelay(1);
544 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
545 mdelay(20);
546 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
547 mdelay(20);
548 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
549 mdelay(20);
550 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
551 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
552
553
554 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
555 rtw_write32(rtwdev, base_addr + 0x68, temp);
556 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
557 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
558 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
559 if (ic >= 0x10)
560 ic = ic - 0x10;
561 else
562 ic = 0x400 - (0x10 - ic);
563
564 if (qc >= 0x10)
565 qc = qc - 0x10;
566 else
567 qc = 0x400 - (0x10 - qc);
568
569 *i_out = ic;
570 *q_out = qc;
571
572 if (ic >= 0x200)
573 ic = 0x400 - ic;
574 if (qc >= 0x200)
575 qc = 0x400 - qc;
576
577 *ic_in = ic;
578 *qc_in = qc;
579
580 rtw_dbg(rtwdev, RTW_DBG_RFK,
581 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
582}
583
584static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
585{
586 u32 base_addr = rtw8822c_get_path_base_addr(path);
587
588 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
589 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
590 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
591 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
592}
593
594static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
595{
596 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
597 struct rtw_backup_info backup[DACK_REG_8822C];
598 u32 ic = 0, qc = 0, i;
599 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
600 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
601 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
602
603 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
604
605 rtw8822c_dac_bb_setting(rtwdev);
606
607
608 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
609 for (i = 0; i < 10; i++) {
610 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
611 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
612 ic_a = ic;
613 qc_a = qc;
614
615 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
616 &ic, &qc, &i_a, &q_a);
617
618 if (ic < 5 && qc < 5)
619 break;
620 }
621 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
622
623
624 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
625 for (i = 0; i < 10; i++) {
626 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
627 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
628 ic_b = ic;
629 qc_b = qc;
630
631 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
632 &ic, &qc, &i_b, &q_b);
633
634 if (ic < 5 && qc < 5)
635 break;
636 }
637 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
638
639 rtw_write32(rtwdev, 0x1b00, 0x00000008);
640 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
641 rtw_write8(rtwdev, 0x1bcc, 0x0);
642 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
643 rtw_write8(rtwdev, 0x1bcc, 0x0);
644
645 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
646
647 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
648 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
649 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
650 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
651}
652
653static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
654{
655 u8 x2k_busy;
656
657 mdelay(1);
658 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
659 if (x2k_busy == 1) {
660 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
661 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
662 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
663 mdelay(1);
664 }
665}
666
667static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
668{
669 rtw8822c_rf_dac_cal(rtwdev);
670 rtw8822c_rf_x2_check(rtwdev);
671}
672
673static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
674{
675 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
676 struct rtw_hal *hal = &rtwdev->hal;
677 u8 crystal_cap;
678 u8 cck_gi_u_bnd_msb = 0;
679 u8 cck_gi_u_bnd_lsb = 0;
680 u8 cck_gi_l_bnd_msb = 0;
681 u8 cck_gi_l_bnd_lsb = 0;
682 bool is_tx2_path;
683
684
685 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
686 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
687 rtw_write8_set(rtwdev, REG_RF_CTRL,
688 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
689 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
690
691
692 rtw8822c_header_file_init(rtwdev, true);
693
694 rtw_phy_load_tables(rtwdev);
695
696 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
697 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
698 crystal_cap | (crystal_cap << 7));
699
700
701 rtw8822c_header_file_init(rtwdev, false);
702
703 is_tx2_path = false;
704 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
705 is_tx2_path);
706 rtw_phy_init(rtwdev);
707
708 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
709 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
710 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
711 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
712
713 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
714 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
715
716 rtw8822c_rf_init(rtwdev);
717
718 rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
719 rtw_write32_mask(rtwdev, 0x1704, 0xffffffff, 0x7700);
720 rtw_write32_mask(rtwdev, 0x1700, 0xffffffff, 0xc00f0038);
721 rtw_write32_mask(rtwdev, 0x6c0, 0xffffffff, 0xaaaaaaaa);
722 rtw_write32_mask(rtwdev, 0x6c4, 0xffffffff, 0xaaaaaaaa);
723}
724
725#define WLAN_TXQ_RPT_EN 0x1F
726#define WLAN_SLOT_TIME 0x09
727#define WLAN_PIFS_TIME 0x1C
728#define WLAN_SIFS_CCK_CONT_TX 0x0A
729#define WLAN_SIFS_OFDM_CONT_TX 0x0E
730#define WLAN_SIFS_CCK_TRX 0x0A
731#define WLAN_SIFS_OFDM_TRX 0x10
732#define WLAN_NAV_MAX 0xC8
733#define WLAN_RDG_NAV 0x05
734#define WLAN_TXOP_NAV 0x1B
735#define WLAN_CCK_RX_TSF 0x30
736#define WLAN_OFDM_RX_TSF 0x30
737#define WLAN_TBTT_PROHIBIT 0x04
738#define WLAN_TBTT_HOLD_TIME 0x064
739#define WLAN_DRV_EARLY_INT 0x04
740#define WLAN_BCN_CTRL_CLT0 0x10
741#define WLAN_BCN_DMA_TIME 0x02
742#define WLAN_BCN_MAX_ERR 0xFF
743#define WLAN_SIFS_CCK_DUR_TUNE 0x0A
744#define WLAN_SIFS_OFDM_DUR_TUNE 0x10
745#define WLAN_SIFS_CCK_CTX 0x0A
746#define WLAN_SIFS_CCK_IRX 0x0A
747#define WLAN_SIFS_OFDM_CTX 0x0E
748#define WLAN_SIFS_OFDM_IRX 0x0E
749#define WLAN_EIFS_DUR_TUNE 0x40
750#define WLAN_EDCA_VO_PARAM 0x002FA226
751#define WLAN_EDCA_VI_PARAM 0x005EA328
752#define WLAN_EDCA_BE_PARAM 0x005EA42B
753#define WLAN_EDCA_BK_PARAM 0x0000A44F
754
755#define WLAN_RX_FILTER0 0xFFFFFFFF
756#define WLAN_RX_FILTER2 0xFFFF
757#define WLAN_RCR_CFG 0xE400220E
758#define WLAN_RXPKT_MAX_SZ 12288
759#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
760
761#define WLAN_AMPDU_MAX_TIME 0x70
762#define WLAN_RTS_LEN_TH 0xFF
763#define WLAN_RTS_TX_TIME_TH 0x08
764#define WLAN_MAX_AGG_PKT_LIMIT 0x20
765#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
766#define WLAN_PRE_TXCNT_TIME_TH 0x1E0
767#define FAST_EDCA_VO_TH 0x06
768#define FAST_EDCA_VI_TH 0x06
769#define FAST_EDCA_BE_TH 0x06
770#define FAST_EDCA_BK_TH 0x06
771#define WLAN_BAR_RETRY_LIMIT 0x01
772#define WLAN_BAR_ACK_TYPE 0x05
773#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
774#define WLAN_RESP_TXRATE 0x84
775#define WLAN_ACK_TO 0x21
776#define WLAN_ACK_TO_CCK 0x6A
777#define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
778#define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
779#define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
780#define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
781#define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
782#define WLAN_RTS_RATE_FB_RATE1 0x003FF010
783#define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
784#define WLAN_RTS_RATE_FB_RATE4 0x0600F010
785#define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
786#define WLAN_RTS_RATE_FB_RATE5 0x0600F015
787#define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
788
789#define WLAN_TX_FUNC_CFG1 0x30
790#define WLAN_TX_FUNC_CFG2 0x30
791#define WLAN_MAC_OPT_NORM_FUNC1 0x98
792#define WLAN_MAC_OPT_LB_FUNC1 0x80
793#define WLAN_MAC_OPT_FUNC2 0x30810041
794
795#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
796 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
797 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
798 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
799
800#define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \
801 (WLAN_SIFS_OFDM_DUR_TUNE << 8))
802
803#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
804 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
805
806#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
807#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
808
809#define MAC_CLK_SPEED 80
810#define EFUSE_PCB_INFO_OFFSET 0xCA
811
812static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
813{
814 u8 value8;
815 u16 value16;
816 u32 value32;
817 u16 pre_txcnt;
818
819
820 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
821 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
822 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
823 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
824
825 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
826 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
827 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
828 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
829 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
830 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
831
832 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
833 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
834 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
835 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
836 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
837 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
838 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
839 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
840 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
841 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
842 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
843
844 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
845 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
846 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
847 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
848 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
849 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
850 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
851 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
852 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
853 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
854 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
855 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
856 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
857 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
858 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
859
860 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
861 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
862
863
864 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
865 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
866 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
867 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
868 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
869 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
870 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
871 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
872 BIT_DIS_STBC_CFE) >> 8);
873
874
875 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
876 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
877 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
878
879 rtw_write8_set(rtwdev, REG_MISC_CTRL,
880 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
881 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
882 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
883 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
884 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
885 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
886
887 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
888
889 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
890 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
891 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
892 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
893 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
894
895
896 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
897 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
898 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
899 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
900 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
901 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
902 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
903 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
904 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
905 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
906 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
907 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
908 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
909 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
910 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
911
912
913 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
914 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
915 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
916 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
917 value16 = 0;
918 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
919 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
920 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
921 | BIT_RXPSF_OFDMRST;
922 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
923 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
924
925 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
926 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
927 BIT_RXPSF_CONT_ERRCHKEN);
928 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
929 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
930
931 return 0;
932}
933
934static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
935{
936#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
937#define RF18_BAND_2G (0)
938#define RF18_BAND_5G (BIT(16) | BIT(8))
939#define RF18_CHANNEL_MASK (MASKBYTE0)
940#define RF18_RFSI_MASK (BIT(18) | BIT(17))
941#define RF18_RFSI_GE_CH80 (BIT(17))
942#define RF18_RFSI_GT_CH140 (BIT(18))
943#define RF18_BW_MASK (BIT(13) | BIT(12))
944#define RF18_BW_20M (BIT(13) | BIT(12))
945#define RF18_BW_40M (BIT(13))
946#define RF18_BW_80M (BIT(12))
947
948 u32 rf_reg18 = 0;
949 u32 rf_rxbb = 0;
950
951 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
952
953 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
954 RF18_BW_MASK);
955
956 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
957 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
958 if (channel > 144)
959 rf_reg18 |= RF18_RFSI_GT_CH140;
960 else if (channel >= 80)
961 rf_reg18 |= RF18_RFSI_GE_CH80;
962
963 switch (bw) {
964 case RTW_CHANNEL_WIDTH_5:
965 case RTW_CHANNEL_WIDTH_10:
966 case RTW_CHANNEL_WIDTH_20:
967 default:
968 rf_reg18 |= RF18_BW_20M;
969 rf_rxbb = 0x18;
970 break;
971 case RTW_CHANNEL_WIDTH_40:
972
973 rf_reg18 |= RF18_BW_40M;
974 rf_rxbb = 0x10;
975 break;
976 case RTW_CHANNEL_WIDTH_80:
977 rf_reg18 |= RF18_BW_80M;
978 rf_rxbb = 0x8;
979 break;
980 }
981
982 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
983 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
984 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
985 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
986
987 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
988 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
989 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
990 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
991
992 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
993 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
994}
995
996static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
997{
998 u32 igi;
999
1000 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1001 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1002 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1003 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1004 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1005}
1006
1007static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1008 u8 primary_ch_idx)
1009{
1010 if (channel <= 14) {
1011 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1012 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1013 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1014 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1015 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1016 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1017
1018 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x0);
1019 rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x0);
1020 if (channel == 13 || channel == 14)
1021 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1022 else if (channel == 11 || channel == 12)
1023 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1024 else
1025 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1026 if (channel == 14) {
1027 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1028 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1029 0x4962c931);
1030 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1031 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1032 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1033 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1034 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1035 0xff012455);
1036 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1037 } else {
1038 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1039 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1040 0x3e18fec8);
1041 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1042 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1043 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1044 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1045 0x00faf0de);
1046 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1047 0x00122344);
1048 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1049 0x0fffffff);
1050 }
1051 if (channel == 13)
1052 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1053 else
1054 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
1055 } else if (channel > 35) {
1056 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1057 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1058 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1059 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1060 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0);
1061 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1062 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1063 if (channel >= 36 && channel <= 64) {
1064 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x1);
1065 rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x1);
1066 } else if (channel >= 100 && channel <= 144) {
1067 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x2);
1068 rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x2);
1069 } else if (channel >= 149) {
1070 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x3);
1071 rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x3);
1072 }
1073
1074 if (channel >= 36 && channel <= 51)
1075 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1076 else if (channel >= 52 && channel <= 55)
1077 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1078 else if (channel >= 56 && channel <= 111)
1079 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1080 else if (channel >= 112 && channel <= 119)
1081 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1082 else if (channel >= 120 && channel <= 172)
1083 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1084 else if (channel >= 173 && channel <= 177)
1085 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1086 }
1087
1088 switch (bw) {
1089 case RTW_CHANNEL_WIDTH_20:
1090 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1091 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1092 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1093 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1094 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
1095 break;
1096 case RTW_CHANNEL_WIDTH_40:
1097 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1098 (primary_ch_idx == 1 ? 1 : 0));
1099 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1100 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1101 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1102 (primary_ch_idx | (primary_ch_idx << 4)));
1103 break;
1104 case RTW_CHANNEL_WIDTH_80:
1105 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1106 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1107 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1108 (primary_ch_idx | (primary_ch_idx << 4)));
1109 break;
1110 case RTW_CHANNEL_WIDTH_5:
1111 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1112 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1113 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1114 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1115 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
1116 break;
1117 case RTW_CHANNEL_WIDTH_10:
1118 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1119 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1120 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1121 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1122 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
1123 break;
1124 }
1125}
1126
1127static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1128 u8 primary_chan_idx)
1129{
1130 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1131 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1132 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1133 rtw8822c_toggle_igi(rtwdev);
1134}
1135
1136static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1137{
1138 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1139 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1140 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1141 } else if (rx_path == BB_PATH_AB) {
1142 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1143 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1144 }
1145
1146 if (rx_path == BB_PATH_A)
1147 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1148 else if (rx_path == BB_PATH_B)
1149 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1150 else if (rx_path == BB_PATH_AB)
1151 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1152}
1153
1154static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1155{
1156 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1157 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1158 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1159 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1160 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1161 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1162 } else if (rx_path == BB_PATH_AB) {
1163 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1164 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1165 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1166 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1167 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1168 }
1169
1170 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1171 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1172}
1173
1174static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1175{
1176 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1177 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1178}
1179
1180static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1181 bool is_tx2_path)
1182{
1183 if (tx_path == BB_PATH_A) {
1184 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1185 } else if (tx_path == BB_PATH_B) {
1186 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1187 } else {
1188 if (is_tx2_path)
1189 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1190 else
1191 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1192 }
1193}
1194
1195static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1196 bool is_tx2_path)
1197{
1198 if (tx_path == BB_PATH_A) {
1199 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1200 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1201 } else if (tx_path == BB_PATH_B) {
1202 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1203 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1204 } else {
1205 if (is_tx2_path) {
1206 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1207 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1208 } else {
1209 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1210 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1211 }
1212 }
1213}
1214
1215static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1216 bool is_tx2_path)
1217{
1218 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1219 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1220}
1221
1222static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1223 u8 rx_path, bool is_tx2_path)
1224{
1225 if ((tx_path | rx_path) & BB_PATH_A)
1226 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1227 else
1228 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1229 if ((tx_path | rx_path) & BB_PATH_B)
1230 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1231 else
1232 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1233
1234 rtw8822c_config_rx_path(rtwdev, rx_path);
1235 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1236
1237 rtw8822c_toggle_igi(rtwdev);
1238}
1239
1240static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1241 struct rtw_rx_pkt_stat *pkt_stat)
1242{
1243 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1244 u8 l_bnd, u_bnd;
1245 u8 gain_a, gain_b;
1246 s8 rx_power[RTW_RF_PATH_MAX];
1247 s8 min_rx_power = -120;
1248
1249 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
1250 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
1251 l_bnd = dm_info->cck_gi_l_bnd;
1252 u_bnd = dm_info->cck_gi_u_bnd;
1253 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
1254 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
1255 if (gain_a < l_bnd)
1256 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
1257 else if (gain_a > u_bnd)
1258 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
1259 if (gain_b < l_bnd)
1260 rx_power[RF_PATH_A] += (l_bnd - gain_b) << 1;
1261 else if (gain_b > u_bnd)
1262 rx_power[RF_PATH_A] -= (gain_b - u_bnd) << 1;
1263
1264 rx_power[RF_PATH_A] -= 110;
1265 rx_power[RF_PATH_B] -= 110;
1266
1267 pkt_stat->rx_power[RF_PATH_A] = max3(rx_power[RF_PATH_A],
1268 rx_power[RF_PATH_B],
1269 min_rx_power);
1270 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1271 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1272 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
1273 min_rx_power);
1274}
1275
1276static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1277 struct rtw_rx_pkt_stat *pkt_stat)
1278{
1279 u8 rxsc, bw;
1280 s8 min_rx_power = -120;
1281
1282 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
1283 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
1284 else
1285 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
1286
1287 if (rxsc >= 9 && rxsc <= 12)
1288 bw = RTW_CHANNEL_WIDTH_40;
1289 else if (rxsc >= 13)
1290 bw = RTW_CHANNEL_WIDTH_80;
1291 else
1292 bw = RTW_CHANNEL_WIDTH_20;
1293
1294 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
1295 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
1296 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
1297 pkt_stat->bw = bw;
1298 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
1299 pkt_stat->rx_power[RF_PATH_B],
1300 min_rx_power);
1301}
1302
1303static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1304 struct rtw_rx_pkt_stat *pkt_stat)
1305{
1306 u8 page;
1307
1308 page = *phy_status & 0xf;
1309
1310 switch (page) {
1311 case 0:
1312 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1313 break;
1314 case 1:
1315 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1316 break;
1317 default:
1318 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1319 return;
1320 }
1321}
1322
1323static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1324 struct rtw_rx_pkt_stat *pkt_stat,
1325 struct ieee80211_rx_status *rx_status)
1326{
1327 struct ieee80211_hdr *hdr;
1328 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1329 u8 *phy_status = NULL;
1330
1331 memset(pkt_stat, 0, sizeof(*pkt_stat));
1332
1333 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
1334 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
1335 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
1336 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
1337 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
1338 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
1339 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
1340 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
1341 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
1342 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
1343 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
1344 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
1345
1346
1347 pkt_stat->drv_info_sz *= 8;
1348
1349
1350 if (pkt_stat->is_c2h)
1351 return;
1352
1353 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
1354 pkt_stat->drv_info_sz);
1355 if (pkt_stat->phy_status) {
1356 phy_status = rx_desc + desc_sz + pkt_stat->shift;
1357 query_phy_status(rtwdev, phy_status, pkt_stat);
1358 }
1359
1360 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1361}
1362
1363static void
1364rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1365 u8 *tx_pwr_ref_ofdm)
1366{
1367 struct rtw_hal *hal = &rtwdev->hal;
1368 u32 txref_cck[2] = {0x18a0, 0x41a0};
1369 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
1370 u8 path;
1371
1372 for (path = 0; path < hal->rf_path_num; path++) {
1373 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1374 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1375 tx_pwr_ref_cck[path]);
1376 }
1377 for (path = 0; path < hal->rf_path_num; path++) {
1378 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1379 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1380 tx_pwr_ref_ofdm[path]);
1381 }
1382}
1383
1384static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1385 s8 *diff_idx)
1386{
1387 u32 offset_txagc = 0x3a00;
1388 u8 rate_idx = rate & 0xfc;
1389 u8 pwr_idx[4];
1390 u32 phy_pwr_idx;
1391 int i;
1392
1393 for (i = 0; i < 4; i++)
1394 pwr_idx[i] = diff_idx[i] & 0x7f;
1395
1396 phy_pwr_idx = pwr_idx[0] |
1397 (pwr_idx[1] << 8) |
1398 (pwr_idx[2] << 16) |
1399 (pwr_idx[3] << 24);
1400
1401 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1402 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1403 phy_pwr_idx);
1404}
1405
1406static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1407{
1408 struct rtw_hal *hal = &rtwdev->hal;
1409 u8 rs, rate, j;
1410 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
1411 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
1412 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
1413 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
1414 s8 diff_a, diff_b;
1415 u8 pwr_a, pwr_b;
1416 s8 diff_idx[4];
1417
1418 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1419 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
1420 for (j = 0; j < rtw_rate_size[rs]; j++) {
1421 rate = rtw_rate_section[rs][j];
1422 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
1423 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
1424 if (rs == 0) {
1425 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
1426 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
1427 } else {
1428 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
1429 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
1430 }
1431 diff_idx[rate % 4] = min(diff_a, diff_b);
1432 if (rate % 4 == 3)
1433 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1434 diff_idx);
1435 }
1436 }
1437}
1438
1439static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1440{
1441 u8 ldo_pwr;
1442
1443 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
1444 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
1445 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
1446}
1447
1448static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
1449{
1450 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1451 u32 cck_enable;
1452 u32 cck_fa_cnt;
1453 u32 ofdm_fa_cnt;
1454 u32 ofdm_tx_counter;
1455
1456 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
1457 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
1458 ofdm_fa_cnt = rtw_read16(rtwdev, REG_OFDM_FACNT);
1459 ofdm_tx_counter = rtw_read16(rtwdev, REG_OFDM_TXCNT);
1460 ofdm_fa_cnt -= ofdm_tx_counter;
1461
1462 dm_info->cck_fa_cnt = cck_fa_cnt;
1463 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1464 dm_info->total_fa_cnt = ofdm_fa_cnt;
1465 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1466
1467 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
1468 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
1469 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
1470 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
1471 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
1472 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
1473}
1474
1475static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
1476{
1477}
1478
1479static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
1480 {0x0086,
1481 RTW_PWR_CUT_ALL_MSK,
1482 RTW_PWR_INTF_SDIO_MSK,
1483 RTW_PWR_ADDR_SDIO,
1484 RTW_PWR_CMD_WRITE, BIT(0), 0},
1485 {0x0086,
1486 RTW_PWR_CUT_ALL_MSK,
1487 RTW_PWR_INTF_SDIO_MSK,
1488 RTW_PWR_ADDR_SDIO,
1489 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1490 {0x002E,
1491 RTW_PWR_CUT_ALL_MSK,
1492 RTW_PWR_INTF_ALL_MSK,
1493 RTW_PWR_ADDR_MAC,
1494 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1495 {0x002D,
1496 RTW_PWR_CUT_ALL_MSK,
1497 RTW_PWR_INTF_ALL_MSK,
1498 RTW_PWR_ADDR_MAC,
1499 RTW_PWR_CMD_WRITE, BIT(0), 0},
1500 {0x007F,
1501 RTW_PWR_CUT_ALL_MSK,
1502 RTW_PWR_INTF_ALL_MSK,
1503 RTW_PWR_ADDR_MAC,
1504 RTW_PWR_CMD_WRITE, BIT(7), 0},
1505 {0x004A,
1506 RTW_PWR_CUT_ALL_MSK,
1507 RTW_PWR_INTF_USB_MSK,
1508 RTW_PWR_ADDR_MAC,
1509 RTW_PWR_CMD_WRITE, BIT(0), 0},
1510 {0x0005,
1511 RTW_PWR_CUT_ALL_MSK,
1512 RTW_PWR_INTF_ALL_MSK,
1513 RTW_PWR_ADDR_MAC,
1514 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1515 {0xFFFF,
1516 RTW_PWR_CUT_ALL_MSK,
1517 RTW_PWR_INTF_ALL_MSK,
1518 0,
1519 RTW_PWR_CMD_END, 0, 0},
1520};
1521
1522static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = {
1523 {0x0000,
1524 RTW_PWR_CUT_ALL_MSK,
1525 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1526 RTW_PWR_ADDR_MAC,
1527 RTW_PWR_CMD_WRITE, BIT(5), 0},
1528 {0x0005,
1529 RTW_PWR_CUT_ALL_MSK,
1530 RTW_PWR_INTF_ALL_MSK,
1531 RTW_PWR_ADDR_MAC,
1532 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1533 {0x0075,
1534 RTW_PWR_CUT_ALL_MSK,
1535 RTW_PWR_INTF_PCI_MSK,
1536 RTW_PWR_ADDR_MAC,
1537 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1538 {0x0006,
1539 RTW_PWR_CUT_ALL_MSK,
1540 RTW_PWR_INTF_ALL_MSK,
1541 RTW_PWR_ADDR_MAC,
1542 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1543 {0x0075,
1544 RTW_PWR_CUT_ALL_MSK,
1545 RTW_PWR_INTF_PCI_MSK,
1546 RTW_PWR_ADDR_MAC,
1547 RTW_PWR_CMD_WRITE, BIT(0), 0},
1548 {0xFF1A,
1549 RTW_PWR_CUT_ALL_MSK,
1550 RTW_PWR_INTF_USB_MSK,
1551 RTW_PWR_ADDR_MAC,
1552 RTW_PWR_CMD_WRITE, 0xFF, 0},
1553 {0x002E,
1554 RTW_PWR_CUT_ALL_MSK,
1555 RTW_PWR_INTF_ALL_MSK,
1556 RTW_PWR_ADDR_MAC,
1557 RTW_PWR_CMD_WRITE, BIT(3), 0},
1558 {0x0006,
1559 RTW_PWR_CUT_ALL_MSK,
1560 RTW_PWR_INTF_ALL_MSK,
1561 RTW_PWR_ADDR_MAC,
1562 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1563 {0x0005,
1564 RTW_PWR_CUT_ALL_MSK,
1565 RTW_PWR_INTF_ALL_MSK,
1566 RTW_PWR_ADDR_MAC,
1567 RTW_PWR_CMD_WRITE, BIT(7), 0},
1568 {0x0005,
1569 RTW_PWR_CUT_ALL_MSK,
1570 RTW_PWR_INTF_ALL_MSK,
1571 RTW_PWR_ADDR_MAC,
1572 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1573 {0x0005,
1574 RTW_PWR_CUT_ALL_MSK,
1575 RTW_PWR_INTF_ALL_MSK,
1576 RTW_PWR_ADDR_MAC,
1577 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1578 {0x0005,
1579 RTW_PWR_CUT_ALL_MSK,
1580 RTW_PWR_INTF_ALL_MSK,
1581 RTW_PWR_ADDR_MAC,
1582 RTW_PWR_CMD_POLLING, BIT(0), 0},
1583 {0x0074,
1584 RTW_PWR_CUT_ALL_MSK,
1585 RTW_PWR_INTF_PCI_MSK,
1586 RTW_PWR_ADDR_MAC,
1587 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1588 {0x0071,
1589 RTW_PWR_CUT_ALL_MSK,
1590 RTW_PWR_INTF_PCI_MSK,
1591 RTW_PWR_ADDR_MAC,
1592 RTW_PWR_CMD_WRITE, BIT(4), 0},
1593 {0x0062,
1594 RTW_PWR_CUT_ALL_MSK,
1595 RTW_PWR_INTF_PCI_MSK,
1596 RTW_PWR_ADDR_MAC,
1597 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1598 (BIT(7) | BIT(6) | BIT(5))},
1599 {0x0061,
1600 RTW_PWR_CUT_ALL_MSK,
1601 RTW_PWR_INTF_PCI_MSK,
1602 RTW_PWR_ADDR_MAC,
1603 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1604 {0x001F,
1605 RTW_PWR_CUT_ALL_MSK,
1606 RTW_PWR_INTF_ALL_MSK,
1607 RTW_PWR_ADDR_MAC,
1608 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
1609 {0x00EF,
1610 RTW_PWR_CUT_ALL_MSK,
1611 RTW_PWR_INTF_ALL_MSK,
1612 RTW_PWR_ADDR_MAC,
1613 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
1614 {0x1045,
1615 RTW_PWR_CUT_ALL_MSK,
1616 RTW_PWR_INTF_ALL_MSK,
1617 RTW_PWR_ADDR_MAC,
1618 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1619 {0x0010,
1620 RTW_PWR_CUT_ALL_MSK,
1621 RTW_PWR_INTF_ALL_MSK,
1622 RTW_PWR_ADDR_MAC,
1623 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1624 {0xFFFF,
1625 RTW_PWR_CUT_ALL_MSK,
1626 RTW_PWR_INTF_ALL_MSK,
1627 0,
1628 RTW_PWR_CMD_END, 0, 0},
1629};
1630
1631static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = {
1632 {0x0093,
1633 RTW_PWR_CUT_ALL_MSK,
1634 RTW_PWR_INTF_ALL_MSK,
1635 RTW_PWR_ADDR_MAC,
1636 RTW_PWR_CMD_WRITE, BIT(3), 0},
1637 {0x001F,
1638 RTW_PWR_CUT_ALL_MSK,
1639 RTW_PWR_INTF_ALL_MSK,
1640 RTW_PWR_ADDR_MAC,
1641 RTW_PWR_CMD_WRITE, 0xFF, 0},
1642 {0x00EF,
1643 RTW_PWR_CUT_ALL_MSK,
1644 RTW_PWR_INTF_ALL_MSK,
1645 RTW_PWR_ADDR_MAC,
1646 RTW_PWR_CMD_WRITE, 0xFF, 0},
1647 {0x1045,
1648 RTW_PWR_CUT_ALL_MSK,
1649 RTW_PWR_INTF_ALL_MSK,
1650 RTW_PWR_ADDR_MAC,
1651 RTW_PWR_CMD_WRITE, BIT(4), 0},
1652 {0xFF1A,
1653 RTW_PWR_CUT_ALL_MSK,
1654 RTW_PWR_INTF_USB_MSK,
1655 RTW_PWR_ADDR_MAC,
1656 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1657 {0x0049,
1658 RTW_PWR_CUT_ALL_MSK,
1659 RTW_PWR_INTF_ALL_MSK,
1660 RTW_PWR_ADDR_MAC,
1661 RTW_PWR_CMD_WRITE, BIT(1), 0},
1662 {0x0006,
1663 RTW_PWR_CUT_ALL_MSK,
1664 RTW_PWR_INTF_ALL_MSK,
1665 RTW_PWR_ADDR_MAC,
1666 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1667 {0x0002,
1668 RTW_PWR_CUT_ALL_MSK,
1669 RTW_PWR_INTF_ALL_MSK,
1670 RTW_PWR_ADDR_MAC,
1671 RTW_PWR_CMD_WRITE, BIT(1), 0},
1672 {0x0005,
1673 RTW_PWR_CUT_ALL_MSK,
1674 RTW_PWR_INTF_ALL_MSK,
1675 RTW_PWR_ADDR_MAC,
1676 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1677 {0x0005,
1678 RTW_PWR_CUT_ALL_MSK,
1679 RTW_PWR_INTF_ALL_MSK,
1680 RTW_PWR_ADDR_MAC,
1681 RTW_PWR_CMD_POLLING, BIT(1), 0},
1682 {0x0000,
1683 RTW_PWR_CUT_ALL_MSK,
1684 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1685 RTW_PWR_ADDR_MAC,
1686 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1687 {0xFFFF,
1688 RTW_PWR_CUT_ALL_MSK,
1689 RTW_PWR_INTF_ALL_MSK,
1690 0,
1691 RTW_PWR_CMD_END, 0, 0},
1692};
1693
1694static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = {
1695 {0x0005,
1696 RTW_PWR_CUT_ALL_MSK,
1697 RTW_PWR_INTF_SDIO_MSK,
1698 RTW_PWR_ADDR_MAC,
1699 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1700 {0x0007,
1701 RTW_PWR_CUT_ALL_MSK,
1702 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1703 RTW_PWR_ADDR_MAC,
1704 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1705 {0x0067,
1706 RTW_PWR_CUT_ALL_MSK,
1707 RTW_PWR_INTF_ALL_MSK,
1708 RTW_PWR_ADDR_MAC,
1709 RTW_PWR_CMD_WRITE, BIT(5), 0},
1710 {0x004A,
1711 RTW_PWR_CUT_ALL_MSK,
1712 RTW_PWR_INTF_USB_MSK,
1713 RTW_PWR_ADDR_MAC,
1714 RTW_PWR_CMD_WRITE, BIT(0), 0},
1715 {0x0081,
1716 RTW_PWR_CUT_ALL_MSK,
1717 RTW_PWR_INTF_ALL_MSK,
1718 RTW_PWR_ADDR_MAC,
1719 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1720 {0x0090,
1721 RTW_PWR_CUT_ALL_MSK,
1722 RTW_PWR_INTF_ALL_MSK,
1723 RTW_PWR_ADDR_MAC,
1724 RTW_PWR_CMD_WRITE, BIT(1), 0},
1725 {0x0005,
1726 RTW_PWR_CUT_ALL_MSK,
1727 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1728 RTW_PWR_ADDR_MAC,
1729 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1730 {0x0005,
1731 RTW_PWR_CUT_ALL_MSK,
1732 RTW_PWR_INTF_PCI_MSK,
1733 RTW_PWR_ADDR_MAC,
1734 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1735 {0x0086,
1736 RTW_PWR_CUT_ALL_MSK,
1737 RTW_PWR_INTF_SDIO_MSK,
1738 RTW_PWR_ADDR_SDIO,
1739 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1740 {0xFFFF,
1741 RTW_PWR_CUT_ALL_MSK,
1742 RTW_PWR_INTF_ALL_MSK,
1743 0,
1744 RTW_PWR_CMD_END, 0, 0},
1745};
1746
1747static struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = {
1748 trans_carddis_to_cardemu_8822c,
1749 trans_cardemu_to_act_8822c,
1750 NULL
1751};
1752
1753static struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = {
1754 trans_act_to_cardemu_8822c,
1755 trans_cardemu_to_carddis_8822c,
1756 NULL
1757};
1758
1759static struct rtw_intf_phy_para usb2_param_8822c[] = {
1760 {0xFFFF, 0x00,
1761 RTW_IP_SEL_PHY,
1762 RTW_INTF_PHY_CUT_ALL,
1763 RTW_INTF_PHY_PLATFORM_ALL},
1764};
1765
1766static struct rtw_intf_phy_para usb3_param_8822c[] = {
1767 {0xFFFF, 0x0000,
1768 RTW_IP_SEL_PHY,
1769 RTW_INTF_PHY_CUT_ALL,
1770 RTW_INTF_PHY_PLATFORM_ALL},
1771};
1772
1773static struct rtw_intf_phy_para pcie_gen1_param_8822c[] = {
1774 {0xFFFF, 0x0000,
1775 RTW_IP_SEL_PHY,
1776 RTW_INTF_PHY_CUT_ALL,
1777 RTW_INTF_PHY_PLATFORM_ALL},
1778};
1779
1780static struct rtw_intf_phy_para pcie_gen2_param_8822c[] = {
1781 {0xFFFF, 0x0000,
1782 RTW_IP_SEL_PHY,
1783 RTW_INTF_PHY_CUT_ALL,
1784 RTW_INTF_PHY_PLATFORM_ALL},
1785};
1786
1787static struct rtw_intf_phy_para_table phy_para_table_8822c = {
1788 .usb2_para = usb2_param_8822c,
1789 .usb3_para = usb3_param_8822c,
1790 .gen1_para = pcie_gen1_param_8822c,
1791 .gen2_para = pcie_gen2_param_8822c,
1792 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c),
1793 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c),
1794 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c),
1795 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c),
1796};
1797
1798static const struct rtw_rfe_def rtw8822c_rfe_defs[] = {
1799 [0] = RTW_DEF_RFE(8822c, 0, 0),
1800 [1] = RTW_DEF_RFE(8822c, 0, 0),
1801 [2] = RTW_DEF_RFE(8822c, 0, 0),
1802};
1803
1804static struct rtw_hw_reg rtw8822c_dig[] = {
1805 [0] = { .addr = 0x1d70, .mask = 0x7f },
1806 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
1807};
1808
1809static struct rtw_page_table page_table_8822c[] = {
1810 {64, 64, 64, 64, 1},
1811 {64, 64, 64, 64, 1},
1812 {64, 64, 0, 0, 1},
1813 {64, 64, 64, 0, 1},
1814 {64, 64, 64, 64, 1},
1815};
1816
1817static struct rtw_rqpn rqpn_table_8822c[] = {
1818 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1819 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1820 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1821 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1822 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1823 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1824 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1825 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1826 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1827 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1828 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1829 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1830 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1831 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1832 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1833};
1834
1835static struct rtw_chip_ops rtw8822c_ops = {
1836 .phy_set_param = rtw8822c_phy_set_param,
1837 .read_efuse = rtw8822c_read_efuse,
1838 .query_rx_desc = rtw8822c_query_rx_desc,
1839 .set_channel = rtw8822c_set_channel,
1840 .mac_init = rtw8822c_mac_init,
1841 .read_rf = rtw_phy_read_rf,
1842 .write_rf = rtw_phy_write_rf_reg_mix,
1843 .set_tx_power_index = rtw8822c_set_tx_power_index,
1844 .cfg_ldo25 = rtw8822c_cfg_ldo25,
1845 .false_alarm_statistics = rtw8822c_false_alarm_statistics,
1846 .do_iqk = rtw8822c_do_iqk,
1847};
1848
1849struct rtw_chip_info rtw8822c_hw_spec = {
1850 .ops = &rtw8822c_ops,
1851 .id = RTW_CHIP_TYPE_8822C,
1852 .fw_name = "rtw88/rtw8822c_fw.bin",
1853 .tx_pkt_desc_sz = 48,
1854 .tx_buf_desc_sz = 16,
1855 .rx_pkt_desc_sz = 24,
1856 .rx_buf_desc_sz = 8,
1857 .phy_efuse_size = 512,
1858 .log_efuse_size = 768,
1859 .ptct_efuse_size = 124,
1860 .txff_size = 262144,
1861 .rxff_size = 24576,
1862 .txgi_factor = 2,
1863 .is_pwr_by_rate_dec = false,
1864 .max_power_index = 0x7f,
1865 .csi_buf_pg_num = 50,
1866 .band = RTW_BAND_2G | RTW_BAND_5G,
1867 .page_size = 128,
1868 .dig_min = 0x20,
1869 .ht_supported = true,
1870 .vht_supported = true,
1871 .sys_func_en = 0xD8,
1872 .pwr_on_seq = card_enable_flow_8822c,
1873 .pwr_off_seq = card_disable_flow_8822c,
1874 .page_table = page_table_8822c,
1875 .rqpn_table = rqpn_table_8822c,
1876 .intf_table = &phy_para_table_8822c,
1877 .dig = rtw8822c_dig,
1878 .rf_base_addr = {0x3c00, 0x4c00},
1879 .rf_sipi_addr = {0x1808, 0x4108},
1880 .mac_tbl = &rtw8822c_mac_tbl,
1881 .agc_tbl = &rtw8822c_agc_tbl,
1882 .bb_tbl = &rtw8822c_bb_tbl,
1883 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl,
1884 .rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl},
1885 .rfe_defs = rtw8822c_rfe_defs,
1886 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
1887};
1888EXPORT_SYMBOL(rtw8822c_hw_spec);
1889
1890MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin");
1891
