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23#ifndef _H_LPFC_DEBUG_FS
24#define _H_LPFC_DEBUG_FS
25
26#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
27
28
29#define LPFC_DEBUG_TRC_ENTRY_SIZE 100
30
31
32#define LPFC_NODELIST_SIZE 8192
33#define LPFC_NODELIST_ENTRY_SIZE 120
34
35
36#define LPFC_DUMPHBASLIM_SIZE 4096
37
38
39#define LPFC_DUMPHOSTSLIM_SIZE 4096
40
41
42#define LPFC_DUMPSLIQINFO_SIZE 4096
43
44
45#define LPFC_HBQINFO_SIZE 8192
46
47
48#define LPFC_NVMESTAT_SIZE 8192
49#define LPFC_NVMEKTIME_SIZE 8192
50#define LPFC_CPUCHECK_SIZE 8192
51#define LPFC_NVMEIO_TRC_SIZE 8192
52
53#define LPFC_DEBUG_OUT_LINE_SZ 80
54
55
56
57
58
59
60#define LPFC_PCI_CFG_BROWSE 0xffff
61#define LPFC_PCI_CFG_RD_CMD_ARG 2
62#define LPFC_PCI_CFG_WR_CMD_ARG 3
63#define LPFC_PCI_CFG_SIZE 4096
64#define LPFC_PCI_CFG_RD_SIZE (LPFC_PCI_CFG_SIZE/4)
65
66#define IDIAG_PCICFG_WHERE_INDX 0
67#define IDIAG_PCICFG_COUNT_INDX 1
68#define IDIAG_PCICFG_VALUE_INDX 2
69
70
71#define LPFC_PCI_BAR_BROWSE 0xffff
72#define LPFC_PCI_BAR_RD_CMD_ARG 3
73#define LPFC_PCI_BAR_WR_CMD_ARG 3
74
75#define LPFC_PCI_IF0_BAR0_SIZE (1024 * 16)
76#define LPFC_PCI_IF0_BAR1_SIZE (1024 * 128)
77#define LPFC_PCI_IF0_BAR2_SIZE (1024 * 128)
78#define LPFC_PCI_IF2_BAR0_SIZE (1024 * 32)
79
80#define LPFC_PCI_BAR_RD_BUF_SIZE 4096
81#define LPFC_PCI_BAR_RD_SIZE (LPFC_PCI_BAR_RD_BUF_SIZE/4)
82
83#define LPFC_PCI_IF0_BAR0_RD_SIZE (LPFC_PCI_IF0_BAR0_SIZE/4)
84#define LPFC_PCI_IF0_BAR1_RD_SIZE (LPFC_PCI_IF0_BAR1_SIZE/4)
85#define LPFC_PCI_IF0_BAR2_RD_SIZE (LPFC_PCI_IF0_BAR2_SIZE/4)
86#define LPFC_PCI_IF2_BAR0_RD_SIZE (LPFC_PCI_IF2_BAR0_SIZE/4)
87
88#define IDIAG_BARACC_BAR_NUM_INDX 0
89#define IDIAG_BARACC_OFF_SET_INDX 1
90#define IDIAG_BARACC_ACC_MOD_INDX 2
91#define IDIAG_BARACC_REG_VAL_INDX 2
92#define IDIAG_BARACC_BAR_SZE_INDX 3
93
94#define IDIAG_BARACC_BAR_0 0
95#define IDIAG_BARACC_BAR_1 1
96#define IDIAG_BARACC_BAR_2 2
97
98#define SINGLE_WORD 1
99
100
101#define LPFC_QUE_INFO_GET_BUF_SIZE 4096
102
103
104#define LPFC_QUE_ACC_BROWSE 0xffff
105#define LPFC_QUE_ACC_RD_CMD_ARG 4
106#define LPFC_QUE_ACC_WR_CMD_ARG 6
107#define LPFC_QUE_ACC_BUF_SIZE 4096
108#define LPFC_QUE_ACC_SIZE (LPFC_QUE_ACC_BUF_SIZE/2)
109
110#define LPFC_IDIAG_EQ 1
111#define LPFC_IDIAG_CQ 2
112#define LPFC_IDIAG_MQ 3
113#define LPFC_IDIAG_WQ 4
114#define LPFC_IDIAG_RQ 5
115
116#define IDIAG_QUEACC_QUETP_INDX 0
117#define IDIAG_QUEACC_QUEID_INDX 1
118#define IDIAG_QUEACC_INDEX_INDX 2
119#define IDIAG_QUEACC_COUNT_INDX 3
120#define IDIAG_QUEACC_OFFST_INDX 4
121#define IDIAG_QUEACC_VALUE_INDX 5
122
123
124#define LPFC_DRB_ACC_ALL 0xffff
125#define LPFC_DRB_ACC_RD_CMD_ARG 1
126#define LPFC_DRB_ACC_WR_CMD_ARG 2
127#define LPFC_DRB_ACC_BUF_SIZE 256
128
129#define LPFC_DRB_EQ 1
130#define LPFC_DRB_CQ 2
131#define LPFC_DRB_MQ 3
132#define LPFC_DRB_WQ 4
133#define LPFC_DRB_RQ 5
134
135#define LPFC_DRB_MAX 5
136
137#define IDIAG_DRBACC_REGID_INDX 0
138#define IDIAG_DRBACC_VALUE_INDX 1
139
140
141#define LPFC_CTL_ACC_ALL 0xffff
142#define LPFC_CTL_ACC_RD_CMD_ARG 1
143#define LPFC_CTL_ACC_WR_CMD_ARG 2
144#define LPFC_CTL_ACC_BUF_SIZE 256
145
146#define LPFC_CTL_PORT_SEM 1
147#define LPFC_CTL_PORT_STA 2
148#define LPFC_CTL_PORT_CTL 3
149#define LPFC_CTL_PORT_ER1 4
150#define LPFC_CTL_PORT_ER2 5
151#define LPFC_CTL_PDEV_CTL 6
152
153#define LPFC_CTL_MAX 6
154
155#define IDIAG_CTLACC_REGID_INDX 0
156#define IDIAG_CTLACC_VALUE_INDX 1
157
158
159#define LPFC_MBX_DMP_ARG 4
160
161#define LPFC_MBX_ACC_BUF_SIZE 512
162#define LPFC_MBX_ACC_LBUF_SZ 128
163
164#define LPFC_MBX_DMP_MBX_WORD 0x00000001
165#define LPFC_MBX_DMP_MBX_BYTE 0x00000002
166#define LPFC_MBX_DMP_MBX_ALL (LPFC_MBX_DMP_MBX_WORD | LPFC_MBX_DMP_MBX_BYTE)
167
168#define LPFC_BSG_DMP_MBX_RD_MBX 0x00000001
169#define LPFC_BSG_DMP_MBX_RD_BUF 0x00000002
170#define LPFC_BSG_DMP_MBX_WR_MBX 0x00000004
171#define LPFC_BSG_DMP_MBX_WR_BUF 0x00000008
172#define LPFC_BSG_DMP_MBX_ALL (LPFC_BSG_DMP_MBX_RD_MBX | \
173 LPFC_BSG_DMP_MBX_RD_BUF | \
174 LPFC_BSG_DMP_MBX_WR_MBX | \
175 LPFC_BSG_DMP_MBX_WR_BUF)
176
177#define LPFC_MBX_DMP_ALL 0xffff
178#define LPFC_MBX_ALL_CMD 0xff
179
180#define IDIAG_MBXACC_MBCMD_INDX 0
181#define IDIAG_MBXACC_DPMAP_INDX 1
182#define IDIAG_MBXACC_DPCNT_INDX 2
183#define IDIAG_MBXACC_WDCNT_INDX 3
184
185
186#define LPFC_EXT_ACC_CMD_ARG 1
187#define LPFC_EXT_ACC_BUF_SIZE 4096
188
189#define LPFC_EXT_ACC_AVAIL 0x1
190#define LPFC_EXT_ACC_ALLOC 0x2
191#define LPFC_EXT_ACC_DRIVR 0x4
192#define LPFC_EXT_ACC_ALL (LPFC_EXT_ACC_DRIVR | \
193 LPFC_EXT_ACC_AVAIL | \
194 LPFC_EXT_ACC_ALLOC)
195
196#define IDIAG_EXTACC_EXMAP_INDX 0
197
198#define SIZE_U8 sizeof(uint8_t)
199#define SIZE_U16 sizeof(uint16_t)
200#define SIZE_U32 sizeof(uint32_t)
201
202#define lpfc_nvmeio_data(phba, fmt, arg...) \
203 { \
204 if (phba->nvmeio_trc_on) \
205 lpfc_debugfs_nvme_trc(phba, fmt, ##arg); \
206 }
207
208struct lpfc_debug {
209 char *i_private;
210 char op;
211#define LPFC_IDIAG_OP_RD 1
212#define LPFC_IDIAG_OP_WR 2
213 char *buffer;
214 int len;
215};
216
217struct lpfc_debugfs_trc {
218 char *fmt;
219 uint32_t data1;
220 uint32_t data2;
221 uint32_t data3;
222 uint32_t seq_cnt;
223 unsigned long jif;
224};
225
226struct lpfc_debugfs_nvmeio_trc {
227 char *fmt;
228 uint16_t data1;
229 uint16_t data2;
230 uint32_t data3;
231};
232
233struct lpfc_idiag_offset {
234 uint32_t last_rd;
235};
236
237#define LPFC_IDIAG_CMD_DATA_SIZE 8
238struct lpfc_idiag_cmd {
239 uint32_t opcode;
240#define LPFC_IDIAG_CMD_PCICFG_RD 0x00000001
241#define LPFC_IDIAG_CMD_PCICFG_WR 0x00000002
242#define LPFC_IDIAG_CMD_PCICFG_ST 0x00000003
243#define LPFC_IDIAG_CMD_PCICFG_CL 0x00000004
244
245#define LPFC_IDIAG_CMD_BARACC_RD 0x00000008
246#define LPFC_IDIAG_CMD_BARACC_WR 0x00000009
247#define LPFC_IDIAG_CMD_BARACC_ST 0x0000000a
248#define LPFC_IDIAG_CMD_BARACC_CL 0x0000000b
249
250#define LPFC_IDIAG_CMD_QUEACC_RD 0x00000011
251#define LPFC_IDIAG_CMD_QUEACC_WR 0x00000012
252#define LPFC_IDIAG_CMD_QUEACC_ST 0x00000013
253#define LPFC_IDIAG_CMD_QUEACC_CL 0x00000014
254
255#define LPFC_IDIAG_CMD_DRBACC_RD 0x00000021
256#define LPFC_IDIAG_CMD_DRBACC_WR 0x00000022
257#define LPFC_IDIAG_CMD_DRBACC_ST 0x00000023
258#define LPFC_IDIAG_CMD_DRBACC_CL 0x00000024
259
260#define LPFC_IDIAG_CMD_CTLACC_RD 0x00000031
261#define LPFC_IDIAG_CMD_CTLACC_WR 0x00000032
262#define LPFC_IDIAG_CMD_CTLACC_ST 0x00000033
263#define LPFC_IDIAG_CMD_CTLACC_CL 0x00000034
264
265#define LPFC_IDIAG_CMD_MBXACC_DP 0x00000041
266#define LPFC_IDIAG_BSG_MBXACC_DP 0x00000042
267
268#define LPFC_IDIAG_CMD_EXTACC_RD 0x00000051
269
270 uint32_t data[LPFC_IDIAG_CMD_DATA_SIZE];
271};
272
273struct lpfc_idiag {
274 uint32_t active;
275 struct lpfc_idiag_cmd cmd;
276 struct lpfc_idiag_offset offset;
277 void *ptr_private;
278};
279
280#else
281
282#define lpfc_nvmeio_data(phba, fmt, arg...) \
283 no_printk(fmt, ##arg)
284
285#endif
286
287enum {
288 DUMP_FCP,
289 DUMP_NVME,
290 DUMP_MBX,
291 DUMP_ELS,
292 DUMP_NVMELS,
293};
294
295
296#define LPFC_DISC_TRC_ELS_CMD 0x1
297#define LPFC_DISC_TRC_ELS_RSP 0x2
298#define LPFC_DISC_TRC_ELS_UNSOL 0x4
299#define LPFC_DISC_TRC_ELS_ALL 0x7
300#define LPFC_DISC_TRC_MBOX_VPORT 0x8
301#define LPFC_DISC_TRC_MBOX 0x10
302#define LPFC_DISC_TRC_MBOX_ALL 0x18
303#define LPFC_DISC_TRC_CT 0x20
304#define LPFC_DISC_TRC_DSM 0x40
305#define LPFC_DISC_TRC_RPORT 0x80
306#define LPFC_DISC_TRC_NODE 0x100
307
308#define LPFC_DISC_TRC_DISCOVERY 0xef
309
310#endif
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325
326
327static inline void
328lpfc_debug_dump_qe(struct lpfc_queue *q, uint32_t idx)
329{
330 char line_buf[LPFC_LBUF_SZ];
331 int i, esize, qe_word_cnt, len;
332 uint32_t *pword;
333
334
335 if (!q)
336 return;
337 if (idx >= q->entry_count)
338 return;
339
340 esize = q->entry_size;
341 qe_word_cnt = esize / sizeof(uint32_t);
342 pword = q->qe[idx].address;
343
344 len = 0;
345 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len, "QE[%04d]: ", idx);
346 if (qe_word_cnt > 8)
347 printk(KERN_ERR "%s\n", line_buf);
348
349 for (i = 0; i < qe_word_cnt; i++) {
350 if (!(i % 8)) {
351 if (i != 0)
352 printk(KERN_ERR "%s\n", line_buf);
353 if (qe_word_cnt > 8) {
354 len = 0;
355 memset(line_buf, 0, LPFC_LBUF_SZ);
356 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len,
357 "%03d: ", i);
358 }
359 }
360 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len, "%08x ",
361 ((uint32_t)*pword) & 0xffffffff);
362 pword++;
363 }
364 if (qe_word_cnt <= 8 || (i - 1) % 8)
365 printk(KERN_ERR "%s\n", line_buf);
366}
367
368
369
370
371
372
373
374
375static inline void
376lpfc_debug_dump_q(struct lpfc_queue *q)
377{
378 int idx, entry_count;
379
380
381 if (!q)
382 return;
383
384 dev_printk(KERN_ERR, &(((q->phba))->pcidev)->dev,
385 "%d: [qid:%d, type:%d, subtype:%d, "
386 "qe_size:%d, qe_count:%d, "
387 "host_index:%d, port_index:%d]\n",
388 (q->phba)->brd_no,
389 q->queue_id, q->type, q->subtype,
390 q->entry_size, q->entry_count,
391 q->host_index, q->hba_index);
392 entry_count = q->entry_count;
393 for (idx = 0; idx < entry_count; idx++)
394 lpfc_debug_dump_qe(q, idx);
395 printk(KERN_ERR "\n");
396}
397
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404
405
406static inline void
407lpfc_debug_dump_wq(struct lpfc_hba *phba, int qtype, int wqidx)
408{
409 struct lpfc_queue *wq;
410 char *qtypestr;
411
412 if (qtype == DUMP_FCP) {
413 wq = phba->sli4_hba.fcp_wq[wqidx];
414 qtypestr = "FCP";
415 } else if (qtype == DUMP_NVME) {
416 wq = phba->sli4_hba.nvme_wq[wqidx];
417 qtypestr = "NVME";
418 } else if (qtype == DUMP_MBX) {
419 wq = phba->sli4_hba.mbx_wq;
420 qtypestr = "MBX";
421 } else if (qtype == DUMP_ELS) {
422 wq = phba->sli4_hba.els_wq;
423 qtypestr = "ELS";
424 } else if (qtype == DUMP_NVMELS) {
425 wq = phba->sli4_hba.nvmels_wq;
426 qtypestr = "NVMELS";
427 } else
428 return;
429
430 if (qtype == DUMP_FCP || qtype == DUMP_NVME)
431 pr_err("%s WQ: WQ[Idx:%d|Qid:%d]\n",
432 qtypestr, wqidx, wq->queue_id);
433 else
434 pr_err("%s WQ: WQ[Qid:%d]\n",
435 qtypestr, wq->queue_id);
436
437 lpfc_debug_dump_q(wq);
438}
439
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447
448
449static inline void
450lpfc_debug_dump_cq(struct lpfc_hba *phba, int qtype, int wqidx)
451{
452 struct lpfc_queue *wq, *cq, *eq;
453 char *qtypestr;
454 int eqidx;
455
456
457
458 if (qtype == DUMP_FCP) {
459 wq = phba->sli4_hba.fcp_wq[wqidx];
460 cq = phba->sli4_hba.fcp_cq[wqidx];
461 qtypestr = "FCP";
462 } else if (qtype == DUMP_NVME) {
463 wq = phba->sli4_hba.nvme_wq[wqidx];
464 cq = phba->sli4_hba.nvme_cq[wqidx];
465 qtypestr = "NVME";
466 } else if (qtype == DUMP_MBX) {
467 wq = phba->sli4_hba.mbx_wq;
468 cq = phba->sli4_hba.mbx_cq;
469 qtypestr = "MBX";
470 } else if (qtype == DUMP_ELS) {
471 wq = phba->sli4_hba.els_wq;
472 cq = phba->sli4_hba.els_cq;
473 qtypestr = "ELS";
474 } else if (qtype == DUMP_NVMELS) {
475 wq = phba->sli4_hba.nvmels_wq;
476 cq = phba->sli4_hba.nvmels_cq;
477 qtypestr = "NVMELS";
478 } else
479 return;
480
481 for (eqidx = 0; eqidx < phba->io_channel_irqs; eqidx++) {
482 if (cq->assoc_qid == phba->sli4_hba.hba_eq[eqidx]->queue_id)
483 break;
484 }
485 if (eqidx == phba->io_channel_irqs) {
486 pr_err("Couldn't find EQ for CQ. Using EQ[0]\n");
487 eqidx = 0;
488 }
489
490 eq = phba->sli4_hba.hba_eq[eqidx];
491
492 if (qtype == DUMP_FCP || qtype == DUMP_NVME)
493 pr_err("%s CQ: WQ[Idx:%d|Qid%d]->CQ[Idx%d|Qid%d]"
494 "->EQ[Idx:%d|Qid:%d]:\n",
495 qtypestr, wqidx, wq->queue_id, wqidx, cq->queue_id,
496 eqidx, eq->queue_id);
497 else
498 pr_err("%s CQ: WQ[Qid:%d]->CQ[Qid:%d]"
499 "->EQ[Idx:%d|Qid:%d]:\n",
500 qtypestr, wq->queue_id, cq->queue_id,
501 eqidx, eq->queue_id);
502
503 lpfc_debug_dump_q(cq);
504}
505
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512
513
514static inline void
515lpfc_debug_dump_hba_eq(struct lpfc_hba *phba, int qidx)
516{
517 struct lpfc_queue *qp;
518
519 qp = phba->sli4_hba.hba_eq[qidx];
520
521 pr_err("EQ[Idx:%d|Qid:%d]\n", qidx, qp->queue_id);
522
523 lpfc_debug_dump_q(qp);
524}
525
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530
531
532static inline void
533lpfc_debug_dump_dat_rq(struct lpfc_hba *phba)
534{
535 printk(KERN_ERR "DAT RQ: RQ[Qid:%d]\n",
536 phba->sli4_hba.dat_rq->queue_id);
537 lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
538}
539
540
541
542
543
544
545
546static inline void
547lpfc_debug_dump_hdr_rq(struct lpfc_hba *phba)
548{
549 printk(KERN_ERR "HDR RQ: RQ[Qid:%d]\n",
550 phba->sli4_hba.hdr_rq->queue_id);
551 lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
552}
553
554
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560
561
562static inline void
563lpfc_debug_dump_wq_by_id(struct lpfc_hba *phba, int qid)
564{
565 int wq_idx;
566
567 for (wq_idx = 0; wq_idx < phba->cfg_fcp_io_channel; wq_idx++)
568 if (phba->sli4_hba.fcp_wq[wq_idx]->queue_id == qid)
569 break;
570 if (wq_idx < phba->cfg_fcp_io_channel) {
571 pr_err("FCP WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);
572 lpfc_debug_dump_q(phba->sli4_hba.fcp_wq[wq_idx]);
573 return;
574 }
575
576 for (wq_idx = 0; wq_idx < phba->cfg_nvme_io_channel; wq_idx++)
577 if (phba->sli4_hba.nvme_wq[wq_idx]->queue_id == qid)
578 break;
579 if (wq_idx < phba->cfg_nvme_io_channel) {
580 pr_err("NVME WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);
581 lpfc_debug_dump_q(phba->sli4_hba.nvme_wq[wq_idx]);
582 return;
583 }
584
585 if (phba->sli4_hba.els_wq->queue_id == qid) {
586 pr_err("ELS WQ[Qid:%d]\n", qid);
587 lpfc_debug_dump_q(phba->sli4_hba.els_wq);
588 return;
589 }
590
591 if (phba->sli4_hba.nvmels_wq->queue_id == qid) {
592 pr_err("NVME LS WQ[Qid:%d]\n", qid);
593 lpfc_debug_dump_q(phba->sli4_hba.nvmels_wq);
594 }
595}
596
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599
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602
603
604
605static inline void
606lpfc_debug_dump_mq_by_id(struct lpfc_hba *phba, int qid)
607{
608 if (phba->sli4_hba.mbx_wq->queue_id == qid) {
609 printk(KERN_ERR "MBX WQ[Qid:%d]\n", qid);
610 lpfc_debug_dump_q(phba->sli4_hba.mbx_wq);
611 }
612}
613
614
615
616
617
618
619
620
621
622static inline void
623lpfc_debug_dump_rq_by_id(struct lpfc_hba *phba, int qid)
624{
625 if (phba->sli4_hba.hdr_rq->queue_id == qid) {
626 printk(KERN_ERR "HDR RQ[Qid:%d]\n", qid);
627 lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
628 return;
629 }
630 if (phba->sli4_hba.dat_rq->queue_id == qid) {
631 printk(KERN_ERR "DAT RQ[Qid:%d]\n", qid);
632 lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
633 }
634}
635
636
637
638
639
640
641
642
643
644static inline void
645lpfc_debug_dump_cq_by_id(struct lpfc_hba *phba, int qid)
646{
647 int cq_idx;
648
649 for (cq_idx = 0; cq_idx < phba->cfg_fcp_io_channel; cq_idx++)
650 if (phba->sli4_hba.fcp_cq[cq_idx]->queue_id == qid)
651 break;
652
653 if (cq_idx < phba->cfg_fcp_io_channel) {
654 pr_err("FCP CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);
655 lpfc_debug_dump_q(phba->sli4_hba.fcp_cq[cq_idx]);
656 return;
657 }
658
659 for (cq_idx = 0; cq_idx < phba->cfg_nvme_io_channel; cq_idx++)
660 if (phba->sli4_hba.nvme_cq[cq_idx]->queue_id == qid)
661 break;
662
663 if (cq_idx < phba->cfg_nvme_io_channel) {
664 pr_err("NVME CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);
665 lpfc_debug_dump_q(phba->sli4_hba.nvme_cq[cq_idx]);
666 return;
667 }
668
669 if (phba->sli4_hba.els_cq->queue_id == qid) {
670 pr_err("ELS CQ[Qid:%d]\n", qid);
671 lpfc_debug_dump_q(phba->sli4_hba.els_cq);
672 return;
673 }
674
675 if (phba->sli4_hba.nvmels_cq->queue_id == qid) {
676 pr_err("NVME LS CQ[Qid:%d]\n", qid);
677 lpfc_debug_dump_q(phba->sli4_hba.nvmels_cq);
678 return;
679 }
680
681 if (phba->sli4_hba.mbx_cq->queue_id == qid) {
682 pr_err("MBX CQ[Qid:%d]\n", qid);
683 lpfc_debug_dump_q(phba->sli4_hba.mbx_cq);
684 }
685}
686
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689
690
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693
694
695static inline void
696lpfc_debug_dump_eq_by_id(struct lpfc_hba *phba, int qid)
697{
698 int eq_idx;
699
700 for (eq_idx = 0; eq_idx < phba->io_channel_irqs; eq_idx++)
701 if (phba->sli4_hba.hba_eq[eq_idx]->queue_id == qid)
702 break;
703
704 if (eq_idx < phba->io_channel_irqs) {
705 printk(KERN_ERR "FCP EQ[Idx:%d|Qid:%d]\n", eq_idx, qid);
706 lpfc_debug_dump_q(phba->sli4_hba.hba_eq[eq_idx]);
707 return;
708 }
709}
710
711void lpfc_debug_dump_all_queues(struct lpfc_hba *);
712