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23#define FDMI_DID 0xfffffaU
24#define NameServer_DID 0xfffffcU
25#define SCR_DID 0xfffffdU
26#define Fabric_DID 0xfffffeU
27#define Bcast_DID 0xffffffU
28#define Mask_DID 0xffffffU
29#define CT_DID_MASK 0xffff00U
30#define Fabric_DID_MASK 0xfff000U
31#define WELL_KNOWN_DID_MASK 0xfffff0U
32
33#define PT2PT_LocalID 1
34#define PT2PT_RemoteID 2
35
36#define FF_DEF_EDTOV 2000
37#define FF_DEF_ALTOV 15
38#define FF_DEF_RATOV 10
39#define FF_DEF_ARBTOV 1900
40
41#define LPFC_BUF_RING0 64
42
43
44#define FCELSSIZE 1024
45
46#define LPFC_FCP_RING 0
47#define LPFC_EXTRA_RING 1
48#define LPFC_ELS_RING 2
49
50#define SLI2_IOCB_CMD_R0_ENTRIES 172
51#define SLI2_IOCB_RSP_R0_ENTRIES 134
52#define SLI2_IOCB_CMD_R1_ENTRIES 4
53#define SLI2_IOCB_RSP_R1_ENTRIES 4
54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52
56#define SLI2_IOCB_CMD_R2_ENTRIES 20
57#define SLI2_IOCB_RSP_R2_ENTRIES 20
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74#define FW_REV_STR_SIZE 32
75
76
77union CtRevisionId {
78
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93};
94
95
96#define FC4_FEATURE_TARGET 0x1
97#define FC4_FEATURE_INIT 0x2
98#define FC4_FEATURE_NVME_DISC 0x4
99
100struct lpfc_sli_ct_request {
101
102 union CtRevisionId RevisionId;
103 uint8_t FsType;
104 uint8_t FsSubType;
105 uint8_t Options;
106 uint8_t Rsrvd1;
107 union CtCommandResponse CommandResponse;
108 uint8_t Rsrvd2;
109 uint8_t ReasonCode;
110 uint8_t Explanation;
111 uint8_t VendorUnique;
112#define LPFC_CT_PREAMBLE 20
113
114 union {
115 uint32_t PortID;
116 struct gid {
117 uint8_t PortType;
118#define GID_PT_N_PORT 1
119 uint8_t DomainScope;
120 uint8_t AreaScope;
121 uint8_t Fc4Type;
122 } gid;
123 struct gid_ff {
124 uint8_t Flags;
125 uint8_t DomainScope;
126 uint8_t AreaScope;
127 uint8_t rsvd1;
128 uint8_t rsvd2;
129 uint8_t rsvd3;
130 uint8_t Fc4FBits;
131 uint8_t Fc4Type;
132 } gid_ff;
133 struct rft {
134 uint32_t PortId;
135
136#ifdef __BIG_ENDIAN_BITFIELD
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
139 uint32_t fcpReg:1;
140 uint32_t rsvd2:2;
141 uint32_t ipReg:1;
142 uint32_t rsvd3:5;
143#else
144 uint32_t rsvd0:16;
145 uint32_t fcpReg:1;
146 uint32_t rsvd1:7;
147 uint32_t rsvd3:5;
148 uint32_t ipReg:1;
149 uint32_t rsvd2:2;
150#endif
151
152 uint32_t rsvd[7];
153 } rft;
154 struct rnn {
155 uint32_t PortId;
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn {
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id {
164 uint32_t port_id;
165 } da_id;
166 struct rspn {
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183#define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code;
189 } rff;
190 } un;
191};
192
193#define LPFC_MAX_CT_SIZE (60 * 4096)
194
195#define SLI_CT_REVISION 1
196#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198#define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202#define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217
218
219
220
221#define SLI_CT_MANAGEMENT_SERVICE 0xFA
222#define SLI_CT_TIME_SERVICE 0xFB
223#define SLI_CT_DIRECTORY_SERVICE 0xFC
224#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226
227
228
229
230#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232
233
234
235
236#define SLI_CT_RESPONSE_FS_RJT 0x8001
237#define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239
240
241
242
243#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244#define SLI_CT_INVALID_COMMAND 0x01
245#define SLI_CT_INVALID_VERSION 0x02
246#define SLI_CT_LOGICAL_ERROR 0x03
247#define SLI_CT_INVALID_IU_SIZE 0x04
248#define SLI_CT_LOGICAL_BUSY 0x05
249#define SLI_CT_PROTOCOL_ERROR 0x07
250#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259#define SLI_CT_VENDOR_UNIQUE 0xff
260
261
262
263
264
265#define SLI_CT_NO_PORT_ID 0x01
266#define SLI_CT_NO_PORT_NAME 0x02
267#define SLI_CT_NO_NODE_NAME 0x03
268#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269#define SLI_CT_NO_IP_ADDRESS 0x05
270#define SLI_CT_NO_IPA 0x06
271#define SLI_CT_NO_FC4_TYPES 0x07
272#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274#define SLI_CT_NO_PORT_TYPE 0x0A
275#define SLI_CT_ACCESS_DENIED 0x10
276#define SLI_CT_INVALID_PORT_ID 0x11
277#define SLI_CT_DATABASE_EMPTY 0x12
278
279
280
281
282
283#define SLI_CTNS_GA_NXT 0x0100
284#define SLI_CTNS_GPN_ID 0x0112
285#define SLI_CTNS_GNN_ID 0x0113
286#define SLI_CTNS_GCS_ID 0x0114
287#define SLI_CTNS_GFT_ID 0x0117
288#define SLI_CTNS_GSPN_ID 0x0118
289#define SLI_CTNS_GPT_ID 0x011A
290#define SLI_CTNS_GFF_ID 0x011F
291#define SLI_CTNS_GID_PN 0x0121
292#define SLI_CTNS_GID_NN 0x0131
293#define SLI_CTNS_GIP_NN 0x0135
294#define SLI_CTNS_GIPA_NN 0x0136
295#define SLI_CTNS_GSNN_NN 0x0139
296#define SLI_CTNS_GNN_IP 0x0153
297#define SLI_CTNS_GIPA_IP 0x0156
298#define SLI_CTNS_GID_FT 0x0171
299#define SLI_CTNS_GID_FF 0x01F1
300#define SLI_CTNS_GID_PT 0x01A1
301#define SLI_CTNS_RPN_ID 0x0212
302#define SLI_CTNS_RNN_ID 0x0213
303#define SLI_CTNS_RCS_ID 0x0214
304#define SLI_CTNS_RFT_ID 0x0217
305#define SLI_CTNS_RSPN_ID 0x0218
306#define SLI_CTNS_RPT_ID 0x021A
307#define SLI_CTNS_RFF_ID 0x021F
308#define SLI_CTNS_RIP_NN 0x0235
309#define SLI_CTNS_RIPA_NN 0x0236
310#define SLI_CTNS_RSNN_NN 0x0239
311#define SLI_CTNS_DA_ID 0x0300
312
313
314
315
316
317#define SLI_CTPT_N_PORT 0x01
318#define SLI_CTPT_NL_PORT 0x02
319#define SLI_CTPT_FNL_PORT 0x03
320#define SLI_CTPT_IP 0x04
321#define SLI_CTPT_FCP 0x08
322#define SLI_CTPT_NVME 0x28
323#define SLI_CTPT_NX_PORT 0x7F
324#define SLI_CTPT_F_PORT 0x81
325#define SLI_CTPT_FL_PORT 0x82
326#define SLI_CTPT_E_PORT 0x84
327
328#define SLI_CT_LAST_ENTRY 0x80000000
329
330
331
332#define FC_PH_4_0 6
333#define FC_PH_4_1 7
334#define FC_PH_4_2 8
335#define FC_PH_4_3 9
336
337#define FC_PH_LOW 8
338#define FC_PH_HIGH 9
339#define FC_PH3 0x20
340
341#define FF_FRAME_SIZE 2048
342
343struct lpfc_name {
344 union {
345 struct {
346#ifdef __BIG_ENDIAN_BITFIELD
347 uint8_t nameType:4;
348 uint8_t IEEEextMsn:4;
349
350#else
351 uint8_t IEEEextMsn:4;
352
353 uint8_t nameType:4;
354#endif
355
356#define NAME_IEEE 0x1
357#define NAME_IEEE_EXT 0x2
358#define NAME_FC_TYPE 0x3
359#define NAME_IP_TYPE 0x4
360#define NAME_CCITT_TYPE 0xC
361#define NAME_CCITT_GR_TYPE 0xE
362 uint8_t IEEEextLsb;
363
364 uint8_t IEEE[6];
365 } s;
366 uint8_t wwn[8];
367 uint64_t name;
368 } u;
369};
370
371struct csp {
372 uint8_t fcphHigh;
373 uint8_t fcphLow;
374 uint8_t bbCreditMsb;
375 uint8_t bbCreditLsb;
376
377
378
379
380
381
382#define clean_address_bit request_multiple_Nport
383
384
385
386
387
388#define virtual_fabric_support randomOffset
389
390
391
392
393
394#define valid_vendor_ver_level response_multiple_NPort
395#ifdef __BIG_ENDIAN_BITFIELD
396 uint16_t request_multiple_Nport:1;
397 uint16_t randomOffset:1;
398 uint16_t response_multiple_NPort:1;
399 uint16_t fPort:1;
400 uint16_t altBbCredit:1;
401 uint16_t edtovResolution:1;
402 uint16_t multicast:1;
403 uint16_t broadcast:1;
404
405 uint16_t huntgroup:1;
406 uint16_t simplex:1;
407 uint16_t word1Reserved1:3;
408 uint16_t dhd:1;
409 uint16_t contIncSeqCnt:1;
410 uint16_t payloadlength:1;
411#else
412 uint16_t broadcast:1;
413 uint16_t multicast:1;
414 uint16_t edtovResolution:1;
415 uint16_t altBbCredit:1;
416 uint16_t fPort:1;
417 uint16_t response_multiple_NPort:1;
418 uint16_t randomOffset:1;
419 uint16_t request_multiple_Nport:1;
420
421 uint16_t payloadlength:1;
422 uint16_t contIncSeqCnt:1;
423 uint16_t dhd:1;
424 uint16_t word1Reserved1:3;
425 uint16_t simplex:1;
426 uint16_t huntgroup:1;
427#endif
428
429 uint8_t bbRcvSizeMsb;
430 uint8_t bbRcvSizeLsb;
431 union {
432 struct {
433 uint8_t word2Reserved1;
434
435 uint8_t totalConcurrSeq;
436 uint8_t roByCategoryMsb;
437
438 uint8_t roByCategoryLsb;
439 } nPort;
440 uint32_t r_a_tov;
441 } w2;
442
443 uint32_t e_d_tov;
444};
445
446struct class_parms {
447#ifdef __BIG_ENDIAN_BITFIELD
448 uint8_t classValid:1;
449 uint8_t intermix:1;
450 uint8_t stackedXparent:1;
451 uint8_t stackedLockDown:1;
452 uint8_t seqDelivery:1;
453 uint8_t word0Reserved1:3;
454#else
455 uint8_t word0Reserved1:3;
456 uint8_t seqDelivery:1;
457 uint8_t stackedLockDown:1;
458 uint8_t stackedXparent:1;
459 uint8_t intermix:1;
460 uint8_t classValid:1;
461
462#endif
463
464 uint8_t word0Reserved2;
465
466#ifdef __BIG_ENDIAN_BITFIELD
467 uint8_t iCtlXidReAssgn:2;
468 uint8_t iCtlInitialPa:2;
469 uint8_t iCtlAck0capable:1;
470 uint8_t iCtlAckNcapable:1;
471 uint8_t word0Reserved3:2;
472#else
473 uint8_t word0Reserved3:2;
474 uint8_t iCtlAckNcapable:1;
475 uint8_t iCtlAck0capable:1;
476 uint8_t iCtlInitialPa:2;
477 uint8_t iCtlXidReAssgn:2;
478#endif
479
480 uint8_t word0Reserved4;
481
482#ifdef __BIG_ENDIAN_BITFIELD
483 uint8_t rCtlAck0capable:1;
484 uint8_t rCtlAckNcapable:1;
485 uint8_t rCtlXidInterlck:1;
486 uint8_t rCtlErrorPolicy:2;
487 uint8_t word1Reserved1:1;
488 uint8_t rCtlCatPerSeq:2;
489#else
490 uint8_t rCtlCatPerSeq:2;
491 uint8_t word1Reserved1:1;
492 uint8_t rCtlErrorPolicy:2;
493 uint8_t rCtlXidInterlck:1;
494 uint8_t rCtlAckNcapable:1;
495 uint8_t rCtlAck0capable:1;
496#endif
497
498 uint8_t word1Reserved2;
499 uint8_t rcvDataSizeMsb;
500 uint8_t rcvDataSizeLsb;
501
502 uint8_t concurrentSeqMsb;
503 uint8_t concurrentSeqLsb;
504 uint8_t EeCreditSeqMsb;
505 uint8_t EeCreditSeqLsb;
506
507 uint8_t openSeqPerXchgMsb;
508 uint8_t openSeqPerXchgLsb;
509 uint8_t word3Reserved1;
510 uint8_t word3Reserved2;
511};
512
513#define FAPWWN_KEY_VENDOR 0x42524344
514
515struct serv_parm {
516 struct csp cmn;
517 struct lpfc_name portName;
518 struct lpfc_name nodeName;
519 struct class_parms cls1;
520 struct class_parms cls2;
521 struct class_parms cls3;
522 struct class_parms cls4;
523 union {
524 uint8_t vendorVersion[16];
525 struct {
526 uint32_t vid;
527#define LPFC_VV_EMLX_ID 0x454d4c58
528 uint32_t flags;
529#define LPFC_VV_SUPPRESS_RSP 1
530 } vv;
531 } un;
532};
533
534
535
536
537struct fc_vft_header {
538 uint32_t word0;
539#define fc_vft_hdr_r_ctl_SHIFT 24
540#define fc_vft_hdr_r_ctl_MASK 0xFF
541#define fc_vft_hdr_r_ctl_WORD word0
542#define fc_vft_hdr_ver_SHIFT 22
543#define fc_vft_hdr_ver_MASK 0x3
544#define fc_vft_hdr_ver_WORD word0
545#define fc_vft_hdr_type_SHIFT 18
546#define fc_vft_hdr_type_MASK 0xF
547#define fc_vft_hdr_type_WORD word0
548#define fc_vft_hdr_e_SHIFT 16
549#define fc_vft_hdr_e_MASK 0x1
550#define fc_vft_hdr_e_WORD word0
551#define fc_vft_hdr_priority_SHIFT 13
552#define fc_vft_hdr_priority_MASK 0x7
553#define fc_vft_hdr_priority_WORD word0
554#define fc_vft_hdr_vf_id_SHIFT 1
555#define fc_vft_hdr_vf_id_MASK 0xFFF
556#define fc_vft_hdr_vf_id_WORD word0
557 uint32_t word1;
558#define fc_vft_hdr_hopct_SHIFT 24
559#define fc_vft_hdr_hopct_MASK 0xFF
560#define fc_vft_hdr_hopct_WORD word1
561};
562
563
564
565
566#ifdef __BIG_ENDIAN_BITFIELD
567#define ELS_CMD_MASK 0xffff0000
568#define ELS_RSP_MASK 0xff000000
569#define ELS_CMD_LS_RJT 0x01000000
570#define ELS_CMD_ACC 0x02000000
571#define ELS_CMD_PLOGI 0x03000000
572#define ELS_CMD_FLOGI 0x04000000
573#define ELS_CMD_LOGO 0x05000000
574#define ELS_CMD_ABTX 0x06000000
575#define ELS_CMD_RCS 0x07000000
576#define ELS_CMD_RES 0x08000000
577#define ELS_CMD_RSS 0x09000000
578#define ELS_CMD_RSI 0x0A000000
579#define ELS_CMD_ESTS 0x0B000000
580#define ELS_CMD_ESTC 0x0C000000
581#define ELS_CMD_ADVC 0x0D000000
582#define ELS_CMD_RTV 0x0E000000
583#define ELS_CMD_RLS 0x0F000000
584#define ELS_CMD_ECHO 0x10000000
585#define ELS_CMD_TEST 0x11000000
586#define ELS_CMD_RRQ 0x12000000
587#define ELS_CMD_REC 0x13000000
588#define ELS_CMD_RDP 0x18000000
589#define ELS_CMD_PRLI 0x20100014
590#define ELS_CMD_NVMEPRLI 0x20140018
591#define ELS_CMD_PRLO 0x21100014
592#define ELS_CMD_PRLO_ACC 0x02100014
593#define ELS_CMD_PDISC 0x50000000
594#define ELS_CMD_FDISC 0x51000000
595#define ELS_CMD_ADISC 0x52000000
596#define ELS_CMD_FARP 0x54000000
597#define ELS_CMD_FARPR 0x55000000
598#define ELS_CMD_RPS 0x56000000
599#define ELS_CMD_RPL 0x57000000
600#define ELS_CMD_FAN 0x60000000
601#define ELS_CMD_RSCN 0x61040000
602#define ELS_CMD_SCR 0x62000000
603#define ELS_CMD_RNID 0x78000000
604#define ELS_CMD_LIRR 0x7A000000
605#define ELS_CMD_LCB 0x81000000
606#else
607#define ELS_CMD_MASK 0xffff
608#define ELS_RSP_MASK 0xff
609#define ELS_CMD_LS_RJT 0x01
610#define ELS_CMD_ACC 0x02
611#define ELS_CMD_PLOGI 0x03
612#define ELS_CMD_FLOGI 0x04
613#define ELS_CMD_LOGO 0x05
614#define ELS_CMD_ABTX 0x06
615#define ELS_CMD_RCS 0x07
616#define ELS_CMD_RES 0x08
617#define ELS_CMD_RSS 0x09
618#define ELS_CMD_RSI 0x0A
619#define ELS_CMD_ESTS 0x0B
620#define ELS_CMD_ESTC 0x0C
621#define ELS_CMD_ADVC 0x0D
622#define ELS_CMD_RTV 0x0E
623#define ELS_CMD_RLS 0x0F
624#define ELS_CMD_ECHO 0x10
625#define ELS_CMD_TEST 0x11
626#define ELS_CMD_RRQ 0x12
627#define ELS_CMD_REC 0x13
628#define ELS_CMD_RDP 0x18
629#define ELS_CMD_PRLI 0x14001020
630#define ELS_CMD_NVMEPRLI 0x18001420
631#define ELS_CMD_PRLO 0x14001021
632#define ELS_CMD_PRLO_ACC 0x14001002
633#define ELS_CMD_PDISC 0x50
634#define ELS_CMD_FDISC 0x51
635#define ELS_CMD_ADISC 0x52
636#define ELS_CMD_FARP 0x54
637#define ELS_CMD_FARPR 0x55
638#define ELS_CMD_RPS 0x56
639#define ELS_CMD_RPL 0x57
640#define ELS_CMD_FAN 0x60
641#define ELS_CMD_RSCN 0x0461
642#define ELS_CMD_SCR 0x62
643#define ELS_CMD_RNID 0x78
644#define ELS_CMD_LIRR 0x7A
645#define ELS_CMD_LCB 0x81
646#endif
647
648
649
650
651
652struct ls_rjt {
653 union {
654 uint32_t lsRjtError;
655 struct {
656 uint8_t lsRjtRsvd0;
657
658 uint8_t lsRjtRsnCode;
659
660#define LSRJT_INVALID_CMD 0x01
661#define LSRJT_LOGICAL_ERR 0x03
662#define LSRJT_LOGICAL_BSY 0x05
663#define LSRJT_PROTOCOL_ERR 0x07
664#define LSRJT_UNABLE_TPC 0x09
665#define LSRJT_CMD_UNSUPPORTED 0x0B
666#define LSRJT_VENDOR_UNIQUE 0xFF
667
668 uint8_t lsRjtRsnCodeExp;
669
670#define LSEXP_NOTHING_MORE 0x00
671#define LSEXP_SPARM_OPTIONS 0x01
672#define LSEXP_SPARM_ICTL 0x03
673#define LSEXP_SPARM_RCTL 0x05
674#define LSEXP_SPARM_RCV_SIZE 0x07
675#define LSEXP_SPARM_CONCUR_SEQ 0x09
676#define LSEXP_SPARM_CREDIT 0x0B
677#define LSEXP_INVALID_PNAME 0x0D
678#define LSEXP_INVALID_NNAME 0x0E
679#define LSEXP_INVALID_CSP 0x0F
680#define LSEXP_INVALID_ASSOC_HDR 0x11
681#define LSEXP_ASSOC_HDR_REQ 0x13
682#define LSEXP_INVALID_O_SID 0x15
683#define LSEXP_INVALID_OX_RX 0x17
684#define LSEXP_CMD_IN_PROGRESS 0x19
685#define LSEXP_PORT_LOGIN_REQ 0x1E
686#define LSEXP_INVALID_NPORT_ID 0x1F
687#define LSEXP_INVALID_SEQ_ID 0x21
688#define LSEXP_INVALID_XCHG 0x23
689#define LSEXP_INACTIVE_XCHG 0x25
690#define LSEXP_RQ_REQUIRED 0x27
691#define LSEXP_OUT_OF_RESOURCE 0x29
692#define LSEXP_CANT_GIVE_DATA 0x2A
693#define LSEXP_REQ_UNSUPPORTED 0x2C
694 uint8_t vendorUnique;
695 } b;
696 } un;
697};
698
699
700
701
702
703typedef struct _LOGO {
704 union {
705 uint32_t nPortId32;
706 struct {
707 uint8_t word1Reserved1;
708 uint8_t nPortIdByte0;
709 uint8_t nPortIdByte1;
710 uint8_t nPortIdByte2;
711 } b;
712 } un;
713 struct lpfc_name portName;
714} LOGO;
715
716
717
718
719
720#define PRLX_PAGE_LEN 0x10
721#define TPRLO_PAGE_LEN 0x14
722
723typedef struct _PRLI {
724 uint8_t prliType;
725
726#define PRLI_FCP_TYPE 0x08
727#define PRLI_NVME_TYPE 0x28
728 uint8_t word0Reserved1;
729
730#ifdef __BIG_ENDIAN_BITFIELD
731 uint8_t origProcAssocV:1;
732 uint8_t respProcAssocV:1;
733 uint8_t estabImagePair:1;
734
735
736 uint8_t word0Reserved2:1;
737 uint8_t acceptRspCode:4;
738#else
739 uint8_t acceptRspCode:4;
740 uint8_t word0Reserved2:1;
741 uint8_t estabImagePair:1;
742 uint8_t respProcAssocV:1;
743 uint8_t origProcAssocV:1;
744
745#endif
746
747#define PRLI_REQ_EXECUTED 0x1
748#define PRLI_NO_RESOURCES 0x2
749#define PRLI_INIT_INCOMPLETE 0x3
750#define PRLI_NO_SUCH_PA 0x4
751#define PRLI_PREDEF_CONFIG 0x5
752#define PRLI_PARTIAL_SUCCESS 0x6
753#define PRLI_INVALID_PAGE_CNT 0x7
754 uint8_t word0Reserved3;
755
756 uint32_t origProcAssoc;
757
758 uint32_t respProcAssoc;
759
760 uint8_t word3Reserved1;
761 uint8_t word3Reserved2;
762
763#ifdef __BIG_ENDIAN_BITFIELD
764 uint16_t Word3bit15Resved:1;
765 uint16_t Word3bit14Resved:1;
766 uint16_t Word3bit13Resved:1;
767 uint16_t Word3bit12Resved:1;
768 uint16_t Word3bit11Resved:1;
769 uint16_t Word3bit10Resved:1;
770 uint16_t TaskRetryIdReq:1;
771 uint16_t Retry:1;
772 uint16_t ConfmComplAllowed:1;
773 uint16_t dataOverLay:1;
774 uint16_t initiatorFunc:1;
775 uint16_t targetFunc:1;
776 uint16_t cmdDataMixEna:1;
777 uint16_t dataRspMixEna:1;
778 uint16_t readXferRdyDis:1;
779 uint16_t writeXferRdyDis:1;
780#else
781 uint16_t Retry:1;
782 uint16_t TaskRetryIdReq:1;
783 uint16_t Word3bit10Resved:1;
784 uint16_t Word3bit11Resved:1;
785 uint16_t Word3bit12Resved:1;
786 uint16_t Word3bit13Resved:1;
787 uint16_t Word3bit14Resved:1;
788 uint16_t Word3bit15Resved:1;
789 uint16_t writeXferRdyDis:1;
790 uint16_t readXferRdyDis:1;
791 uint16_t dataRspMixEna:1;
792 uint16_t cmdDataMixEna:1;
793 uint16_t targetFunc:1;
794 uint16_t initiatorFunc:1;
795 uint16_t dataOverLay:1;
796 uint16_t ConfmComplAllowed:1;
797#endif
798} PRLI;
799
800
801
802
803
804typedef struct _PRLO {
805 uint8_t prloType;
806
807#define PRLO_FCP_TYPE 0x08
808 uint8_t word0Reserved1;
809
810#ifdef __BIG_ENDIAN_BITFIELD
811 uint8_t origProcAssocV:1;
812 uint8_t respProcAssocV:1;
813 uint8_t word0Reserved2:2;
814 uint8_t acceptRspCode:4;
815#else
816 uint8_t acceptRspCode:4;
817 uint8_t word0Reserved2:2;
818 uint8_t respProcAssocV:1;
819 uint8_t origProcAssocV:1;
820#endif
821
822#define PRLO_REQ_EXECUTED 0x1
823#define PRLO_NO_SUCH_IMAGE 0x4
824#define PRLO_INVALID_PAGE_CNT 0x7
825
826 uint8_t word0Reserved3;
827
828 uint32_t origProcAssoc;
829
830 uint32_t respProcAssoc;
831
832 uint32_t word3Reserved1;
833} PRLO;
834
835typedef struct _ADISC {
836 uint32_t hardAL_PA;
837 struct lpfc_name portName;
838 struct lpfc_name nodeName;
839 uint32_t DID;
840} ADISC;
841
842typedef struct _FARP {
843 uint32_t Mflags:8;
844 uint32_t Odid:24;
845#define FARP_NO_ACTION 0
846
847#define FARP_MATCH_PORT 0x1
848#define FARP_MATCH_NODE 0x2
849#define FARP_MATCH_IP 0x4
850#define FARP_MATCH_IPV4 0x5
851
852#define FARP_MATCH_IPV6 0x6
853
854 uint32_t Rflags:8;
855 uint32_t Rdid:24;
856#define FARP_REQUEST_PLOGI 0x1
857#define FARP_REQUEST_FARPR 0x2
858 struct lpfc_name OportName;
859 struct lpfc_name OnodeName;
860 struct lpfc_name RportName;
861 struct lpfc_name RnodeName;
862 uint8_t Oipaddr[16];
863 uint8_t Ripaddr[16];
864} FARP;
865
866typedef struct _FAN {
867 uint32_t Fdid;
868 struct lpfc_name FportName;
869 struct lpfc_name FnodeName;
870} FAN;
871
872typedef struct _SCR {
873 uint8_t resvd1;
874 uint8_t resvd2;
875 uint8_t resvd3;
876 uint8_t Function;
877#define SCR_FUNC_FABRIC 0x01
878#define SCR_FUNC_NPORT 0x02
879#define SCR_FUNC_FULL 0x03
880#define SCR_CLEAR 0xff
881} SCR;
882
883typedef struct _RNID_TOP_DISC {
884 struct lpfc_name portName;
885 uint8_t resvd[8];
886 uint32_t unitType;
887#define RNID_HBA 0x7
888#define RNID_HOST 0xa
889#define RNID_DRIVER 0xd
890 uint32_t physPort;
891 uint32_t attachedNodes;
892 uint16_t ipVersion;
893#define RNID_IPV4 0x1
894#define RNID_IPV6 0x2
895 uint16_t UDPport;
896 uint8_t ipAddr[16];
897 uint16_t resvd1;
898 uint16_t flags;
899#define RNID_TD_SUPPORT 0x1
900#define RNID_LP_VALID 0x2
901} RNID_TOP_DISC;
902
903typedef struct _RNID {
904 uint8_t Format;
905#define RNID_TOPOLOGY_DISC 0xdf
906 uint8_t CommonLen;
907 uint8_t resvd1;
908 uint8_t SpecificLen;
909 struct lpfc_name portName;
910 struct lpfc_name nodeName;
911 union {
912 RNID_TOP_DISC topologyDisc;
913 } un;
914} RNID;
915
916typedef struct _RPS {
917 union {
918 uint32_t portNum;
919 struct lpfc_name portName;
920 } un;
921} RPS;
922
923typedef struct _RPS_RSP {
924 uint16_t rsvd1;
925 uint16_t portStatus;
926 uint32_t linkFailureCnt;
927 uint32_t lossSyncCnt;
928 uint32_t lossSignalCnt;
929 uint32_t primSeqErrCnt;
930 uint32_t invalidXmitWord;
931 uint32_t crcCnt;
932} RPS_RSP;
933
934struct RLS {
935 uint32_t rls;
936#define rls_rsvd_SHIFT 24
937#define rls_rsvd_MASK 0x000000ff
938#define rls_rsvd_WORD rls
939#define rls_did_SHIFT 0
940#define rls_did_MASK 0x00ffffff
941#define rls_did_WORD rls
942};
943
944struct RLS_RSP {
945 uint32_t linkFailureCnt;
946 uint32_t lossSyncCnt;
947 uint32_t lossSignalCnt;
948 uint32_t primSeqErrCnt;
949 uint32_t invalidXmitWord;
950 uint32_t crcCnt;
951};
952
953struct RRQ {
954 uint32_t rrq;
955#define rrq_rsvd_SHIFT 24
956#define rrq_rsvd_MASK 0x000000ff
957#define rrq_rsvd_WORD rrq
958#define rrq_did_SHIFT 0
959#define rrq_did_MASK 0x00ffffff
960#define rrq_did_WORD rrq
961 uint32_t rrq_exchg;
962#define rrq_oxid_SHIFT 16
963#define rrq_oxid_MASK 0xffff
964#define rrq_oxid_WORD rrq_exchg
965#define rrq_rxid_SHIFT 0
966#define rrq_rxid_MASK 0xffff
967#define rrq_rxid_WORD rrq_exchg
968};
969
970#define LPFC_MAX_VFN_PER_PFN 255
971#define LPFC_DEF_VFN_PER_PFN 0
972
973struct RTV_RSP {
974 uint32_t ratov;
975 uint32_t edtov;
976 uint32_t qtov;
977#define qtov_rsvd0_SHIFT 28
978#define qtov_rsvd0_MASK 0x0000000f
979#define qtov_rsvd0_WORD qtov
980#define qtov_edtovres_SHIFT 27
981#define qtov_edtovres_MASK 0x00000001
982#define qtov_edtovres_WORD qtov
983#define qtov__rsvd1_SHIFT 19
984#define qtov_rsvd1_MASK 0x0000003f
985#define qtov_rsvd1_WORD qtov
986#define qtov_rttov_SHIFT 18
987#define qtov_rttov_MASK 0x00000001
988#define qtov_rttov_WORD qtov
989#define qtov_rsvd2_SHIFT 0
990#define qtov_rsvd2_MASK 0x0003ffff
991#define qtov_rsvd2_WORD qtov
992};
993
994
995typedef struct _RPL {
996 uint32_t maxsize;
997 uint32_t index;
998} RPL;
999
1000typedef struct _PORT_NUM_BLK {
1001 uint32_t portNum;
1002 uint32_t portID;
1003 struct lpfc_name portName;
1004} PORT_NUM_BLK;
1005
1006typedef struct _RPL_RSP {
1007 uint32_t listLen;
1008 uint32_t index;
1009 PORT_NUM_BLK port_num_blk;
1010} RPL_RSP;
1011
1012
1013typedef struct _D_ID {
1014 union {
1015 uint32_t word;
1016 struct {
1017#ifdef __BIG_ENDIAN_BITFIELD
1018 uint8_t resv;
1019 uint8_t domain;
1020 uint8_t area;
1021 uint8_t id;
1022#else
1023 uint8_t id;
1024 uint8_t area;
1025 uint8_t domain;
1026 uint8_t resv;
1027#endif
1028 } b;
1029 } un;
1030} D_ID;
1031
1032#define RSCN_ADDRESS_FORMAT_PORT 0x0
1033#define RSCN_ADDRESS_FORMAT_AREA 0x1
1034#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1035#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1036#define RSCN_ADDRESS_FORMAT_MASK 0x3
1037
1038
1039
1040
1041
1042typedef struct _ELS_PKT {
1043 uint8_t elsCode;
1044 uint8_t elsByte1;
1045 uint8_t elsByte2;
1046 uint8_t elsByte3;
1047 union {
1048 struct ls_rjt lsRjt;
1049 struct serv_parm logi;
1050 LOGO logo;
1051 PRLI prli;
1052 PRLO prlo;
1053 ADISC adisc;
1054 FARP farp;
1055 FAN fan;
1056 SCR scr;
1057 RNID rnid;
1058 uint8_t pad[128 - 4];
1059 } un;
1060} ELS_PKT;
1061
1062
1063
1064
1065
1066struct fc_lcb_request_frame {
1067 uint32_t lcb_command;
1068 uint8_t lcb_sub_command;
1069#define LPFC_LCB_ON 0x1
1070#define LPFC_LCB_OFF 0x2
1071 uint8_t reserved[2];
1072 uint8_t capability;
1073 uint8_t lcb_type;
1074#define LPFC_LCB_GREEN 0x1
1075#define LPFC_LCB_AMBER 0x2
1076 uint8_t lcb_frequency;
1077#define LCB_CAPABILITY_DURATION 1
1078#define BEACON_VERSION_V1 1
1079#define BEACON_VERSION_V0 0
1080 uint16_t lcb_duration;
1081};
1082
1083
1084
1085
1086struct fc_lcb_res_frame {
1087 uint32_t lcb_ls_acc;
1088 uint8_t lcb_sub_command;
1089 uint8_t reserved[2];
1090 uint8_t capability;
1091 uint8_t lcb_type;
1092 uint8_t lcb_frequency;
1093 uint16_t lcb_duration;
1094};
1095
1096
1097
1098
1099#define SFF_PG0_IDENT_SFP 0x3
1100
1101#define SFP_FLAG_PT_OPTICAL 0x0
1102#define SFP_FLAG_PT_SWLASER 0x01
1103#define SFP_FLAG_PT_LWLASER_LC1310 0x02
1104#define SFP_FLAG_PT_LWLASER_LL1550 0x03
1105#define SFP_FLAG_PT_MASK 0x0F
1106#define SFP_FLAG_PT_SHIFT 0
1107
1108#define SFP_FLAG_IS_OPTICAL_PORT 0x01
1109#define SFP_FLAG_IS_OPTICAL_MASK 0x010
1110#define SFP_FLAG_IS_OPTICAL_SHIFT 4
1111
1112#define SFP_FLAG_IS_DESC_VALID 0x01
1113#define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1114#define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1115
1116#define SFP_FLAG_CT_UNKNOWN 0x0
1117#define SFP_FLAG_CT_SFP_PLUS 0x01
1118#define SFP_FLAG_CT_MASK 0x3C
1119#define SFP_FLAG_CT_SHIFT 6
1120
1121struct fc_rdp_port_name_info {
1122 uint8_t wwnn[8];
1123 uint8_t wwpn[8];
1124};
1125
1126
1127
1128
1129
1130
1131struct fc_link_status {
1132 uint32_t link_failure_cnt;
1133 uint32_t loss_of_synch_cnt;
1134 uint32_t loss_of_signal_cnt;
1135 uint32_t primitive_seq_proto_err;
1136 uint32_t invalid_trans_word;
1137 uint32_t invalid_crc_cnt;
1138
1139};
1140
1141#define RDP_PORT_NAMES_DESC_TAG 0x00010003
1142struct fc_rdp_port_name_desc {
1143 uint32_t tag;
1144 uint32_t length;
1145 struct fc_rdp_port_name_info port_names;
1146};
1147
1148
1149struct fc_rdp_fec_info {
1150 uint32_t CorrectedBlocks;
1151 uint32_t UncorrectableBlocks;
1152};
1153
1154#define RDP_FEC_DESC_TAG 0x00010005
1155struct fc_fec_rdp_desc {
1156 uint32_t tag;
1157 uint32_t length;
1158 struct fc_rdp_fec_info info;
1159};
1160
1161struct fc_rdp_link_error_status_payload_info {
1162 struct fc_link_status link_status;
1163 uint32_t port_type;
1164};
1165
1166#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1167struct fc_rdp_link_error_status_desc {
1168 uint32_t tag;
1169 uint32_t length;
1170 struct fc_rdp_link_error_status_payload_info info;
1171};
1172
1173#define VN_PT_PHY_UNKNOWN 0x00
1174#define VN_PT_PHY_PF_PORT 0x01
1175#define VN_PT_PHY_ETH_MAC 0x10
1176#define VN_PT_PHY_SHIFT 30
1177
1178#define RDP_PS_1GB 0x8000
1179#define RDP_PS_2GB 0x4000
1180#define RDP_PS_4GB 0x2000
1181#define RDP_PS_10GB 0x1000
1182#define RDP_PS_8GB 0x0800
1183#define RDP_PS_16GB 0x0400
1184#define RDP_PS_32GB 0x0200
1185#define RDP_PS_64GB 0x0100
1186#define RDP_PS_128GB 0x0080
1187#define RDP_PS_256GB 0x0040
1188
1189#define RDP_CAP_USER_CONFIGURED 0x0002
1190#define RDP_CAP_UNKNOWN 0x0001
1191#define RDP_PS_UNKNOWN 0x0002
1192#define RDP_PS_NOT_ESTABLISHED 0x0001
1193
1194struct fc_rdp_port_speed {
1195 uint16_t capabilities;
1196 uint16_t speed;
1197};
1198
1199struct fc_rdp_port_speed_info {
1200 struct fc_rdp_port_speed port_speed;
1201};
1202
1203#define RDP_PORT_SPEED_DESC_TAG 0x00010001
1204struct fc_rdp_port_speed_desc {
1205 uint32_t tag;
1206 uint32_t length;
1207 struct fc_rdp_port_speed_info info;
1208};
1209
1210#define RDP_NPORT_ID_SIZE 4
1211#define RDP_N_PORT_DESC_TAG 0x00000003
1212struct fc_rdp_nport_desc {
1213 uint32_t tag;
1214 uint32_t length;
1215 uint32_t nport_id : 12;
1216 uint32_t reserved : 8;
1217};
1218
1219
1220struct fc_rdp_link_service_info {
1221 uint32_t els_req;
1222};
1223
1224#define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1225struct fc_rdp_link_service_desc {
1226 uint32_t tag;
1227 uint32_t length;
1228 struct fc_rdp_link_service_info payload;
1229
1230};
1231
1232struct fc_rdp_sfp_info {
1233 uint16_t temperature;
1234 uint16_t vcc;
1235 uint16_t tx_bias;
1236 uint16_t tx_power;
1237 uint16_t rx_power;
1238 uint16_t flags;
1239};
1240
1241#define RDP_SFP_DESC_TAG 0x00010000
1242struct fc_rdp_sfp_desc {
1243 uint32_t tag;
1244 uint32_t length;
1245 struct fc_rdp_sfp_info sfp_info;
1246};
1247
1248
1249struct fc_rdp_bbc_info {
1250 uint32_t port_bbc;
1251 uint32_t attached_port_bbc;
1252 uint32_t rtt;
1253};
1254#define RDP_BBC_DESC_TAG 0x00010006
1255struct fc_rdp_bbc_desc {
1256 uint32_t tag;
1257 uint32_t length;
1258 struct fc_rdp_bbc_info bbc_info;
1259};
1260
1261
1262#define RDP_OET_LOW_WARNING 0x1
1263#define RDP_OET_HIGH_WARNING 0x2
1264#define RDP_OET_LOW_ALARM 0x4
1265#define RDP_OET_HIGH_ALARM 0x8
1266
1267#define RDP_OED_TEMPERATURE 0x1
1268#define RDP_OED_VOLTAGE 0x2
1269#define RDP_OED_TXBIAS 0x3
1270#define RDP_OED_TXPOWER 0x4
1271#define RDP_OED_RXPOWER 0x5
1272
1273#define RDP_OED_TYPE_SHIFT 28
1274
1275struct fc_rdp_oed_info {
1276 uint16_t hi_alarm;
1277 uint16_t lo_alarm;
1278 uint16_t hi_warning;
1279 uint16_t lo_warning;
1280 uint32_t function_flags;
1281};
1282#define RDP_OED_DESC_TAG 0x00010007
1283struct fc_rdp_oed_sfp_desc {
1284 uint32_t tag;
1285 uint32_t length;
1286 struct fc_rdp_oed_info oed_info;
1287};
1288
1289
1290struct fc_rdp_opd_sfp_info {
1291 uint8_t vendor_name[16];
1292 uint8_t model_number[16];
1293 uint8_t serial_number[16];
1294 uint8_t revision[4];
1295 uint8_t date[8];
1296};
1297
1298#define RDP_OPD_DESC_TAG 0x00010008
1299struct fc_rdp_opd_sfp_desc {
1300 uint32_t tag;
1301 uint32_t length;
1302 struct fc_rdp_opd_sfp_info opd_info;
1303};
1304
1305struct fc_rdp_req_frame {
1306 uint32_t rdp_command;
1307 uint32_t rdp_des_length;
1308 struct fc_rdp_nport_desc nport_id_desc;
1309};
1310
1311
1312struct fc_rdp_res_frame {
1313 uint32_t reply_sequence;
1314 uint32_t length;
1315 struct fc_rdp_link_service_desc link_service_desc;
1316 struct fc_rdp_sfp_desc sfp_desc;
1317 struct fc_rdp_port_speed_desc portspeed_desc;
1318 struct fc_rdp_link_error_status_desc link_error_desc;
1319 struct fc_rdp_port_name_desc diag_port_names_desc;
1320 struct fc_rdp_port_name_desc attached_port_names_desc;
1321 struct fc_fec_rdp_desc fec_desc;
1322 struct fc_rdp_bbc_desc bbc_desc;
1323 struct fc_rdp_oed_sfp_desc oed_temp_desc;
1324 struct fc_rdp_oed_sfp_desc oed_voltage_desc;
1325 struct fc_rdp_oed_sfp_desc oed_txbias_desc;
1326 struct fc_rdp_oed_sfp_desc oed_txpower_desc;
1327 struct fc_rdp_oed_sfp_desc oed_rxpower_desc;
1328 struct fc_rdp_opd_sfp_desc opd_desc;
1329};
1330
1331
1332
1333
1334
1335#define SLI_CT_FDMI_Subtypes 0x10
1336
1337
1338
1339
1340struct lpfc_fdmi_reg_port_list {
1341 uint32_t EntryCnt;
1342 uint32_t pe;
1343};
1344
1345
1346
1347
1348struct lpfc_fdmi_attr_def {
1349
1350 uint32_t AttrType:16;
1351 uint32_t AttrLen:16;
1352 uint32_t AttrValue;
1353};
1354
1355
1356
1357struct lpfc_fdmi_attr_entry {
1358 union {
1359 uint32_t AttrInt;
1360 uint8_t AttrTypes[32];
1361 uint8_t AttrString[256];
1362 struct lpfc_name AttrWWN;
1363 } un;
1364};
1365
1366#define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1367
1368
1369
1370
1371struct lpfc_fdmi_attr_block {
1372 uint32_t EntryCnt;
1373 struct lpfc_fdmi_attr_entry Entry;
1374};
1375
1376
1377
1378
1379struct lpfc_fdmi_port_entry {
1380 struct lpfc_name PortName;
1381};
1382
1383
1384
1385
1386struct lpfc_fdmi_hba_ident {
1387 struct lpfc_name PortName;
1388};
1389
1390
1391
1392
1393struct lpfc_fdmi_reg_hba {
1394 struct lpfc_fdmi_hba_ident hi;
1395 struct lpfc_fdmi_reg_port_list rpl;
1396
1397};
1398
1399
1400
1401
1402struct lpfc_fdmi_reg_hbaattr {
1403 struct lpfc_name HBA_PortName;
1404 struct lpfc_fdmi_attr_block ab;
1405};
1406
1407
1408
1409
1410struct lpfc_fdmi_reg_portattr {
1411 struct lpfc_name PortName;
1412 struct lpfc_fdmi_attr_block ab;
1413};
1414
1415
1416
1417
1418#define SLI_MGMT_GRHL 0x100
1419#define SLI_MGMT_GHAT 0x101
1420#define SLI_MGMT_GRPL 0x102
1421#define SLI_MGMT_GPAT 0x110
1422#define SLI_MGMT_GPAS 0x120
1423#define SLI_MGMT_RHBA 0x200
1424#define SLI_MGMT_RHAT 0x201
1425#define SLI_MGMT_RPRT 0x210
1426#define SLI_MGMT_RPA 0x211
1427#define SLI_MGMT_DHBA 0x300
1428#define SLI_MGMT_DHAT 0x301
1429#define SLI_MGMT_DPRT 0x310
1430#define SLI_MGMT_DPA 0x311
1431
1432#define LPFC_FDMI_MAX_RETRY 3
1433
1434
1435
1436
1437#define RHBA_NODENAME 0x1
1438#define RHBA_MANUFACTURER 0x2
1439#define RHBA_SERIAL_NUMBER 0x3
1440#define RHBA_MODEL 0x4
1441#define RHBA_MODEL_DESCRIPTION 0x5
1442#define RHBA_HARDWARE_VERSION 0x6
1443#define RHBA_DRIVER_VERSION 0x7
1444#define RHBA_OPTION_ROM_VERSION 0x8
1445#define RHBA_FIRMWARE_VERSION 0x9
1446#define RHBA_OS_NAME_VERSION 0xa
1447#define RHBA_MAX_CT_PAYLOAD_LEN 0xb
1448#define RHBA_SYM_NODENAME 0xc
1449#define RHBA_VENDOR_INFO 0xd
1450#define RHBA_NUM_PORTS 0xe
1451#define RHBA_FABRIC_WWNN 0xf
1452#define RHBA_BIOS_VERSION 0x10
1453#define RHBA_BIOS_STATE 0x11
1454#define RHBA_VENDOR_ID 0xe0
1455
1456
1457#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1458#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1459#define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1460#define LPFC_FDMI_HBA_ATTR_model 0x00000008
1461#define LPFC_FDMI_HBA_ATTR_description 0x00000010
1462#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1463#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1464#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1465#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1466#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1467#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1468#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1469#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000
1470#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1471#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1472#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1473#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000
1474#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1475
1476
1477#define LPFC_FDMI1_HBA_ATTR 0x000007ff
1478
1479
1480
1481#define LPFC_FDMI2_HBA_ATTR 0x0002efff
1482
1483
1484
1485
1486#define RPRT_SUPPORTED_FC4_TYPES 0x1
1487#define RPRT_SUPPORTED_SPEED 0x2
1488#define RPRT_PORT_SPEED 0x3
1489#define RPRT_MAX_FRAME_SIZE 0x4
1490#define RPRT_OS_DEVICE_NAME 0x5
1491#define RPRT_HOST_NAME 0x6
1492#define RPRT_NODENAME 0x7
1493#define RPRT_PORTNAME 0x8
1494#define RPRT_SYM_PORTNAME 0x9
1495#define RPRT_PORT_TYPE 0xa
1496#define RPRT_SUPPORTED_CLASS 0xb
1497#define RPRT_FABRICNAME 0xc
1498#define RPRT_ACTIVE_FC4_TYPES 0xd
1499#define RPRT_PORT_STATE 0x101
1500#define RPRT_DISC_PORT 0x102
1501#define RPRT_PORT_ID 0x103
1502#define RPRT_SMART_SERVICE 0xf100
1503#define RPRT_SMART_GUID 0xf101
1504#define RPRT_SMART_VERSION 0xf102
1505#define RPRT_SMART_MODEL 0xf103
1506#define RPRT_SMART_PORT_INFO 0xf104
1507#define RPRT_SMART_QOS 0xf105
1508#define RPRT_SMART_SECURITY 0xf106
1509
1510
1511#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1512#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1513#define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1514#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1515#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1516#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1517#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1518#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1519#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1520#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1521#define LPFC_FDMI_PORT_ATTR_class 0x00000400
1522#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1523#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1524#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1525#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1526#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1527#define LPFC_FDMI_SMART_ATTR_service 0x00010000
1528#define LPFC_FDMI_SMART_ATTR_guid 0x00020000
1529#define LPFC_FDMI_SMART_ATTR_version 0x00040000
1530#define LPFC_FDMI_SMART_ATTR_model 0x00080000
1531#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000
1532#define LPFC_FDMI_SMART_ATTR_qos 0x00200000
1533#define LPFC_FDMI_SMART_ATTR_security 0x00400000
1534
1535
1536#define LPFC_FDMI1_PORT_ATTR 0x0000003f
1537
1538
1539#define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1540
1541
1542#define LPFC_FDMI2_SMART_ATTR 0x007fffff
1543
1544
1545#define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1546#define LPFC_FDMI_PORTSTATE_ONLINE 2
1547
1548
1549#define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1550#define LPFC_FDMI_PORTTYPE_NPORT 1
1551#define LPFC_FDMI_PORTTYPE_NLPORT 2
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565#define MAX_SLI3_CONFIGURED_RINGS 3
1566#define MAX_SLI3_RINGS 4
1567
1568
1569#define OWN_CHIP 1
1570
1571
1572#define OWN_HOST 0
1573
1574
1575#define IOCB_WORD_SZ 8
1576
1577
1578#define FC_NET_HDR 0x20
1579
1580
1581#define PCI_VENDOR_ID_EMULEX 0x10df
1582#define PCI_DEVICE_ID_FIREFLY 0x1ae5
1583#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1584#define PCI_DEVICE_ID_BALIUS 0xe131
1585#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1586#define PCI_DEVICE_ID_LANCER_FC 0xe200
1587#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1588#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1589#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1590#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1591#define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1592#define PCI_DEVICE_ID_SAT_SMB 0xf011
1593#define PCI_DEVICE_ID_SAT_MID 0xf015
1594#define PCI_DEVICE_ID_RFLY 0xf095
1595#define PCI_DEVICE_ID_PFLY 0xf098
1596#define PCI_DEVICE_ID_LP101 0xf0a1
1597#define PCI_DEVICE_ID_TFLY 0xf0a5
1598#define PCI_DEVICE_ID_BSMB 0xf0d1
1599#define PCI_DEVICE_ID_BMID 0xf0d5
1600#define PCI_DEVICE_ID_ZSMB 0xf0e1
1601#define PCI_DEVICE_ID_ZMID 0xf0e5
1602#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1603#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1604#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1605#define PCI_DEVICE_ID_SAT 0xf100
1606#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1607#define PCI_DEVICE_ID_SAT_DCSP 0xf112
1608#define PCI_DEVICE_ID_FALCON 0xf180
1609#define PCI_DEVICE_ID_SUPERFLY 0xf700
1610#define PCI_DEVICE_ID_DRAGONFLY 0xf800
1611#define PCI_DEVICE_ID_CENTAUR 0xf900
1612#define PCI_DEVICE_ID_PEGASUS 0xf980
1613#define PCI_DEVICE_ID_THOR 0xfa00
1614#define PCI_DEVICE_ID_VIPER 0xfb00
1615#define PCI_DEVICE_ID_LP10000S 0xfc00
1616#define PCI_DEVICE_ID_LP11000S 0xfc10
1617#define PCI_DEVICE_ID_LPE11000S 0xfc20
1618#define PCI_DEVICE_ID_SAT_S 0xfc40
1619#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1620#define PCI_DEVICE_ID_HELIOS 0xfd00
1621#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1622#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1623#define PCI_DEVICE_ID_ZEPHYR 0xfe00
1624#define PCI_DEVICE_ID_HORNET 0xfe05
1625#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1626#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1627#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1628#define PCI_DEVICE_ID_TIGERSHARK 0x0704
1629#define PCI_DEVICE_ID_TOMCAT 0x0714
1630#define PCI_DEVICE_ID_SKYHAWK 0x0724
1631#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1632
1633#define JEDEC_ID_ADDRESS 0x0080001c
1634#define FIREFLY_JEDEC_ID 0x1ACC
1635#define SUPERFLY_JEDEC_ID 0x0020
1636#define DRAGONFLY_JEDEC_ID 0x0021
1637#define DRAGONFLY_V2_JEDEC_ID 0x0025
1638#define CENTAUR_2G_JEDEC_ID 0x0026
1639#define CENTAUR_1G_JEDEC_ID 0x0028
1640#define PEGASUS_ORION_JEDEC_ID 0x0036
1641#define PEGASUS_JEDEC_ID 0x0038
1642#define THOR_JEDEC_ID 0x0012
1643#define HELIOS_JEDEC_ID 0x0364
1644#define ZEPHYR_JEDEC_ID 0x0577
1645#define VIPER_JEDEC_ID 0x4838
1646#define SATURN_JEDEC_ID 0x1004
1647#define HORNET_JDEC_ID 0x2057706D
1648
1649#define JEDEC_ID_MASK 0x0FFFF000
1650#define JEDEC_ID_SHIFT 12
1651#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1652
1653typedef struct {
1654 uint32_t hostAtt;
1655
1656 uint32_t chipAtt;
1657
1658 uint32_t hostStatus;
1659 uint32_t hostControl;
1660 uint32_t buiConfig;
1661
1662} FF_REGS;
1663
1664
1665#define FF_REG_AREA_SIZE 256
1666
1667
1668
1669#define HA_REG_OFFSET 0
1670
1671#define HA_R0RE_REQ 0x00000001
1672#define HA_R0CE_RSP 0x00000002
1673#define HA_R0ATT 0x00000008
1674#define HA_R1RE_REQ 0x00000010
1675#define HA_R1CE_RSP 0x00000020
1676#define HA_R1ATT 0x00000080
1677#define HA_R2RE_REQ 0x00000100
1678#define HA_R2CE_RSP 0x00000200
1679#define HA_R2ATT 0x00000800
1680#define HA_R3RE_REQ 0x00001000
1681#define HA_R3CE_RSP 0x00002000
1682#define HA_R3ATT 0x00008000
1683#define HA_LATT 0x20000000
1684#define HA_MBATT 0x40000000
1685#define HA_ERATT 0x80000000
1686
1687#define HA_RXRE_REQ 0x00000001
1688#define HA_RXCE_RSP 0x00000002
1689#define HA_RXATT 0x00000008
1690#define HA_RXMASK 0x0000000f
1691
1692#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1693#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1694#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1695#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1696
1697#define HA_R0_POS 3
1698#define HA_R1_POS 7
1699#define HA_R2_POS 11
1700#define HA_R3_POS 15
1701#define HA_LE_POS 29
1702#define HA_MB_POS 30
1703#define HA_ER_POS 31
1704
1705
1706#define CA_REG_OFFSET 4
1707
1708#define CA_R0CE_REQ 0x00000001
1709#define CA_R0RE_RSP 0x00000002
1710#define CA_R0ATT 0x00000008
1711#define CA_R1CE_REQ 0x00000010
1712#define CA_R1RE_RSP 0x00000020
1713#define CA_R1ATT 0x00000080
1714#define CA_R2CE_REQ 0x00000100
1715#define CA_R2RE_RSP 0x00000200
1716#define CA_R2ATT 0x00000800
1717#define CA_R3CE_REQ 0x00001000
1718#define CA_R3RE_RSP 0x00002000
1719#define CA_R3ATT 0x00008000
1720#define CA_MBATT 0x40000000
1721
1722
1723
1724#define HS_REG_OFFSET 8
1725
1726#define HS_MBRDY 0x00400000
1727#define HS_FFRDY 0x00800000
1728#define HS_FFER8 0x01000000
1729#define HS_FFER7 0x02000000
1730#define HS_FFER6 0x04000000
1731#define HS_FFER5 0x08000000
1732#define HS_FFER4 0x10000000
1733#define HS_FFER3 0x20000000
1734#define HS_FFER2 0x40000000
1735#define HS_FFER1 0x80000000
1736#define HS_CRIT_TEMP 0x00000100
1737#define HS_FFERM 0xFF000100
1738#define UNPLUG_ERR 0x00000001
1739
1740
1741#define HC_REG_OFFSET 12
1742
1743#define HC_MBINT_ENA 0x00000001
1744#define HC_R0INT_ENA 0x00000002
1745#define HC_R1INT_ENA 0x00000004
1746#define HC_R2INT_ENA 0x00000008
1747#define HC_R3INT_ENA 0x00000010
1748#define HC_INITHBI 0x02000000
1749#define HC_INITMB 0x04000000
1750#define HC_INITFF 0x08000000
1751#define HC_LAINT_ENA 0x20000000
1752#define HC_ERINT_ENA 0x80000000
1753
1754
1755#define MSIX_DFLT_ID 0
1756#define MSIX_RNG0_ID 0
1757#define MSIX_RNG1_ID 1
1758#define MSIX_RNG2_ID 2
1759#define MSIX_RNG3_ID 3
1760
1761#define MSIX_LINK_ID 4
1762#define MSIX_MBOX_ID 5
1763
1764#define MSIX_SPARE0_ID 6
1765#define MSIX_SPARE1_ID 7
1766
1767
1768#define MBX_SHUTDOWN 0x00
1769#define MBX_LOAD_SM 0x01
1770#define MBX_READ_NV 0x02
1771#define MBX_WRITE_NV 0x03
1772#define MBX_RUN_BIU_DIAG 0x04
1773#define MBX_INIT_LINK 0x05
1774#define MBX_DOWN_LINK 0x06
1775#define MBX_CONFIG_LINK 0x07
1776#define MBX_CONFIG_RING 0x09
1777#define MBX_RESET_RING 0x0A
1778#define MBX_READ_CONFIG 0x0B
1779#define MBX_READ_RCONFIG 0x0C
1780#define MBX_READ_SPARM 0x0D
1781#define MBX_READ_STATUS 0x0E
1782#define MBX_READ_RPI 0x0F
1783#define MBX_READ_XRI 0x10
1784#define MBX_READ_REV 0x11
1785#define MBX_READ_LNK_STAT 0x12
1786#define MBX_REG_LOGIN 0x13
1787#define MBX_UNREG_LOGIN 0x14
1788#define MBX_CLEAR_LA 0x16
1789#define MBX_DUMP_MEMORY 0x17
1790#define MBX_DUMP_CONTEXT 0x18
1791#define MBX_RUN_DIAGS 0x19
1792#define MBX_RESTART 0x1A
1793#define MBX_UPDATE_CFG 0x1B
1794#define MBX_DOWN_LOAD 0x1C
1795#define MBX_DEL_LD_ENTRY 0x1D
1796#define MBX_RUN_PROGRAM 0x1E
1797#define MBX_SET_MASK 0x20
1798#define MBX_SET_VARIABLE 0x21
1799#define MBX_UNREG_D_ID 0x23
1800#define MBX_KILL_BOARD 0x24
1801#define MBX_CONFIG_FARP 0x25
1802#define MBX_BEACON 0x2A
1803#define MBX_CONFIG_MSI 0x30
1804#define MBX_HEARTBEAT 0x31
1805#define MBX_WRITE_VPARMS 0x32
1806#define MBX_ASYNCEVT_ENABLE 0x33
1807#define MBX_READ_EVENT_LOG_STATUS 0x37
1808#define MBX_READ_EVENT_LOG 0x38
1809#define MBX_WRITE_EVENT_LOG 0x39
1810
1811#define MBX_PORT_CAPABILITIES 0x3B
1812#define MBX_PORT_IOV_CONTROL 0x3C
1813
1814#define MBX_CONFIG_HBQ 0x7C
1815#define MBX_LOAD_AREA 0x81
1816#define MBX_RUN_BIU_DIAG64 0x84
1817#define MBX_CONFIG_PORT 0x88
1818#define MBX_READ_SPARM64 0x8D
1819#define MBX_READ_RPI64 0x8F
1820#define MBX_REG_LOGIN64 0x93
1821#define MBX_READ_TOPOLOGY 0x95
1822#define MBX_REG_VPI 0x96
1823#define MBX_UNREG_VPI 0x97
1824
1825#define MBX_WRITE_WWN 0x98
1826#define MBX_SET_DEBUG 0x99
1827#define MBX_LOAD_EXP_ROM 0x9C
1828#define MBX_SLI4_CONFIG 0x9B
1829#define MBX_SLI4_REQ_FTRS 0x9D
1830#define MBX_MAX_CMDS 0x9E
1831#define MBX_RESUME_RPI 0x9E
1832#define MBX_SLI2_CMD_MASK 0x80
1833#define MBX_REG_VFI 0x9F
1834#define MBX_REG_FCFI 0xA0
1835#define MBX_UNREG_VFI 0xA1
1836#define MBX_UNREG_FCFI 0xA2
1837#define MBX_INIT_VFI 0xA3
1838#define MBX_INIT_VPI 0xA4
1839#define MBX_ACCESS_VDATA 0xA5
1840#define MBX_REG_FCFI_MRQ 0xAF
1841
1842#define MBX_AUTH_PORT 0xF8
1843#define MBX_SECURITY_MGMT 0xF9
1844
1845
1846
1847#define CMD_RCV_SEQUENCE_CX 0x01
1848#define CMD_XMIT_SEQUENCE_CR 0x02
1849#define CMD_XMIT_SEQUENCE_CX 0x03
1850#define CMD_XMIT_BCAST_CN 0x04
1851#define CMD_XMIT_BCAST_CX 0x05
1852#define CMD_QUE_RING_BUF_CN 0x06
1853#define CMD_QUE_XRI_BUF_CX 0x07
1854#define CMD_IOCB_CONTINUE_CN 0x08
1855#define CMD_RET_XRI_BUF_CX 0x09
1856#define CMD_ELS_REQUEST_CR 0x0A
1857#define CMD_ELS_REQUEST_CX 0x0B
1858#define CMD_RCV_ELS_REQ_CX 0x0D
1859#define CMD_ABORT_XRI_CN 0x0E
1860#define CMD_ABORT_XRI_CX 0x0F
1861#define CMD_CLOSE_XRI_CN 0x10
1862#define CMD_CLOSE_XRI_CX 0x11
1863#define CMD_CREATE_XRI_CR 0x12
1864#define CMD_CREATE_XRI_CX 0x13
1865#define CMD_GET_RPI_CN 0x14
1866#define CMD_XMIT_ELS_RSP_CX 0x15
1867#define CMD_GET_RPI_CR 0x16
1868#define CMD_XRI_ABORTED_CX 0x17
1869#define CMD_FCP_IWRITE_CR 0x18
1870#define CMD_FCP_IWRITE_CX 0x19
1871#define CMD_FCP_IREAD_CR 0x1A
1872#define CMD_FCP_IREAD_CX 0x1B
1873#define CMD_FCP_ICMND_CR 0x1C
1874#define CMD_FCP_ICMND_CX 0x1D
1875#define CMD_FCP_TSEND_CX 0x1F
1876#define CMD_FCP_TRECEIVE_CX 0x21
1877#define CMD_FCP_TRSP_CX 0x23
1878#define CMD_FCP_AUTO_TRSP_CX 0x29
1879
1880#define CMD_ADAPTER_MSG 0x20
1881#define CMD_ADAPTER_DUMP 0x22
1882
1883
1884
1885#define CMD_ASYNC_STATUS 0x7C
1886#define CMD_RCV_SEQUENCE64_CX 0x81
1887#define CMD_XMIT_SEQUENCE64_CR 0x82
1888#define CMD_XMIT_SEQUENCE64_CX 0x83
1889#define CMD_XMIT_BCAST64_CN 0x84
1890#define CMD_XMIT_BCAST64_CX 0x85
1891#define CMD_QUE_RING_BUF64_CN 0x86
1892#define CMD_QUE_XRI_BUF64_CX 0x87
1893#define CMD_IOCB_CONTINUE64_CN 0x88
1894#define CMD_RET_XRI_BUF64_CX 0x89
1895#define CMD_ELS_REQUEST64_CR 0x8A
1896#define CMD_ELS_REQUEST64_CX 0x8B
1897#define CMD_ABORT_MXRI64_CN 0x8C
1898#define CMD_RCV_ELS_REQ64_CX 0x8D
1899#define CMD_XMIT_ELS_RSP64_CX 0x95
1900#define CMD_XMIT_BLS_RSP64_CX 0x97
1901#define CMD_FCP_IWRITE64_CR 0x98
1902#define CMD_FCP_IWRITE64_CX 0x99
1903#define CMD_FCP_IREAD64_CR 0x9A
1904#define CMD_FCP_IREAD64_CX 0x9B
1905#define CMD_FCP_ICMND64_CR 0x9C
1906#define CMD_FCP_ICMND64_CX 0x9D
1907#define CMD_FCP_TSEND64_CX 0x9F
1908#define CMD_FCP_TRECEIVE64_CX 0xA1
1909#define CMD_FCP_TRSP64_CX 0xA3
1910
1911#define CMD_QUE_XRI64_CX 0xB3
1912#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1913#define CMD_IOCB_RCV_ELS64_CX 0xB7
1914#define CMD_IOCB_RET_XRI64_CX 0xB9
1915#define CMD_IOCB_RCV_CONT64_CX 0xBB
1916
1917#define CMD_GEN_REQUEST64_CR 0xC2
1918#define CMD_GEN_REQUEST64_CX 0xC3
1919
1920
1921#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1922#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1923#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1924#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1925#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1926#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1927#define CMD_IOCB_RET_HBQE64_CN 0xCA
1928#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1929#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1930#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1931#define CMD_IOCB_LOGENTRY_CN 0x94
1932#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1933
1934
1935#define DSSCMD_IWRITE64_CR 0xF8
1936#define DSSCMD_IWRITE64_CX 0xF9
1937#define DSSCMD_IREAD64_CR 0xFA
1938#define DSSCMD_IREAD64_CX 0xFB
1939
1940#define CMD_MAX_IOCB_CMD 0xFB
1941#define CMD_IOCB_MASK 0xff
1942
1943#define MAX_MSG_DATA 28
1944
1945#define LPFC_MAX_ADPTMSG 32
1946
1947
1948
1949#define MBX_SUCCESS 0
1950#define MBXERR_NUM_RINGS 1
1951#define MBXERR_NUM_IOCBS 2
1952#define MBXERR_IOCBS_EXCEEDED 3
1953#define MBXERR_BAD_RING_NUMBER 4
1954#define MBXERR_MASK_ENTRIES_RANGE 5
1955#define MBXERR_MASKS_EXCEEDED 6
1956#define MBXERR_BAD_PROFILE 7
1957#define MBXERR_BAD_DEF_CLASS 8
1958#define MBXERR_BAD_MAX_RESPONDER 9
1959#define MBXERR_BAD_MAX_ORIGINATOR 10
1960#define MBXERR_RPI_REGISTERED 11
1961#define MBXERR_RPI_FULL 12
1962#define MBXERR_NO_RESOURCES 13
1963#define MBXERR_BAD_RCV_LENGTH 14
1964#define MBXERR_DMA_ERROR 15
1965#define MBXERR_ERROR 16
1966#define MBXERR_LINK_DOWN 0x33
1967#define MBXERR_SEC_NO_PERMISSION 0xF02
1968#define MBX_NOT_FINISHED 255
1969
1970#define MBX_BUSY 0xffffff
1971#define MBX_TIMEOUT 0xfffffe
1972
1973#define TEMPERATURE_OFFSET 0xB0
1974
1975
1976
1977
1978#define FAILURE 1
1979
1980
1981
1982
1983
1984typedef struct {
1985#ifdef __BIG_ENDIAN_BITFIELD
1986 uint8_t tval;
1987 uint8_t tmask;
1988 uint8_t rval;
1989 uint8_t rmask;
1990#else
1991 uint8_t rmask;
1992 uint8_t rval;
1993 uint8_t tmask;
1994 uint8_t tval;
1995#endif
1996} RR_REG;
1997
1998struct ulp_bde {
1999 uint32_t bdeAddress;
2000#ifdef __BIG_ENDIAN_BITFIELD
2001 uint32_t bdeReserved:4;
2002 uint32_t bdeAddrHigh:4;
2003 uint32_t bdeSize:24;
2004#else
2005 uint32_t bdeSize:24;
2006 uint32_t bdeAddrHigh:4;
2007 uint32_t bdeReserved:4;
2008#endif
2009};
2010
2011typedef struct ULP_BDL {
2012#ifdef __BIG_ENDIAN_BITFIELD
2013 uint32_t bdeFlags:8;
2014 uint32_t bdeSize:24;
2015#else
2016 uint32_t bdeSize:24;
2017 uint32_t bdeFlags:8;
2018#endif
2019
2020 uint32_t addrLow;
2021 uint32_t addrHigh;
2022 uint32_t ulpIoTag32;
2023} ULP_BDL;
2024
2025
2026
2027
2028
2029enum lpfc_protgrp_type {
2030 LPFC_PG_TYPE_INVALID = 0,
2031 LPFC_PG_TYPE_NO_DIF,
2032 LPFC_PG_TYPE_EMBD_DIF,
2033 LPFC_PG_TYPE_DIF_BUF
2034};
2035
2036
2037#define LPFC_PDE5_DESCRIPTOR 0x85
2038#define LPFC_PDE6_DESCRIPTOR 0x86
2039#define LPFC_PDE7_DESCRIPTOR 0x87
2040
2041
2042#define BG_OP_IN_NODIF_OUT_CRC 0x0
2043#define BG_OP_IN_CRC_OUT_NODIF 0x1
2044#define BG_OP_IN_NODIF_OUT_CSUM 0x2
2045#define BG_OP_IN_CSUM_OUT_NODIF 0x3
2046#define BG_OP_IN_CRC_OUT_CRC 0x4
2047#define BG_OP_IN_CSUM_OUT_CSUM 0x5
2048#define BG_OP_IN_CRC_OUT_CSUM 0x6
2049#define BG_OP_IN_CSUM_OUT_CRC 0x7
2050#define BG_OP_RAW_MODE 0x8
2051
2052struct lpfc_pde5 {
2053 uint32_t word0;
2054#define pde5_type_SHIFT 24
2055#define pde5_type_MASK 0x000000ff
2056#define pde5_type_WORD word0
2057#define pde5_rsvd0_SHIFT 0
2058#define pde5_rsvd0_MASK 0x00ffffff
2059#define pde5_rsvd0_WORD word0
2060 uint32_t reftag;
2061 uint32_t reftagtr;
2062};
2063
2064struct lpfc_pde6 {
2065 uint32_t word0;
2066#define pde6_type_SHIFT 24
2067#define pde6_type_MASK 0x000000ff
2068#define pde6_type_WORD word0
2069#define pde6_rsvd0_SHIFT 0
2070#define pde6_rsvd0_MASK 0x00ffffff
2071#define pde6_rsvd0_WORD word0
2072 uint32_t word1;
2073#define pde6_rsvd1_SHIFT 26
2074#define pde6_rsvd1_MASK 0x0000003f
2075#define pde6_rsvd1_WORD word1
2076#define pde6_na_SHIFT 25
2077#define pde6_na_MASK 0x00000001
2078#define pde6_na_WORD word1
2079#define pde6_rsvd2_SHIFT 16
2080#define pde6_rsvd2_MASK 0x000001FF
2081#define pde6_rsvd2_WORD word1
2082#define pde6_apptagtr_SHIFT 0
2083#define pde6_apptagtr_MASK 0x0000ffff
2084#define pde6_apptagtr_WORD word1
2085 uint32_t word2;
2086#define pde6_optx_SHIFT 28
2087#define pde6_optx_MASK 0x0000000f
2088#define pde6_optx_WORD word2
2089#define pde6_oprx_SHIFT 24
2090#define pde6_oprx_MASK 0x0000000f
2091#define pde6_oprx_WORD word2
2092#define pde6_nr_SHIFT 23
2093#define pde6_nr_MASK 0x00000001
2094#define pde6_nr_WORD word2
2095#define pde6_ce_SHIFT 22
2096#define pde6_ce_MASK 0x00000001
2097#define pde6_ce_WORD word2
2098#define pde6_re_SHIFT 21
2099#define pde6_re_MASK 0x00000001
2100#define pde6_re_WORD word2
2101#define pde6_ae_SHIFT 20
2102#define pde6_ae_MASK 0x00000001
2103#define pde6_ae_WORD word2
2104#define pde6_ai_SHIFT 19
2105#define pde6_ai_MASK 0x00000001
2106#define pde6_ai_WORD word2
2107#define pde6_bs_SHIFT 16
2108#define pde6_bs_MASK 0x00000007
2109#define pde6_bs_WORD word2
2110#define pde6_apptagval_SHIFT 0
2111#define pde6_apptagval_MASK 0x0000ffff
2112#define pde6_apptagval_WORD word2
2113};
2114
2115struct lpfc_pde7 {
2116 uint32_t word0;
2117#define pde7_type_SHIFT 24
2118#define pde7_type_MASK 0x000000ff
2119#define pde7_type_WORD word0
2120#define pde7_rsvd0_SHIFT 0
2121#define pde7_rsvd0_MASK 0x00ffffff
2122#define pde7_rsvd0_WORD word0
2123 uint32_t addrHigh;
2124 uint32_t addrLow;
2125};
2126
2127
2128
2129typedef struct {
2130#ifdef __BIG_ENDIAN_BITFIELD
2131 uint32_t rsvd2:25;
2132 uint32_t acknowledgment:1;
2133 uint32_t version:1;
2134 uint32_t erase_or_prog:1;
2135 uint32_t update_flash:1;
2136 uint32_t update_ram:1;
2137 uint32_t method:1;
2138 uint32_t load_cmplt:1;
2139#else
2140 uint32_t load_cmplt:1;
2141 uint32_t method:1;
2142 uint32_t update_ram:1;
2143 uint32_t update_flash:1;
2144 uint32_t erase_or_prog:1;
2145 uint32_t version:1;
2146 uint32_t acknowledgment:1;
2147 uint32_t rsvd2:25;
2148#endif
2149
2150 uint32_t dl_to_adr_low;
2151 uint32_t dl_to_adr_high;
2152 uint32_t dl_len;
2153 union {
2154 uint32_t dl_from_mbx_offset;
2155 struct ulp_bde dl_from_bde;
2156 struct ulp_bde64 dl_from_bde64;
2157 } un;
2158
2159} LOAD_SM_VAR;
2160
2161
2162
2163typedef struct {
2164 uint32_t rsvd1[3];
2165 uint32_t rsvd2;
2166 uint32_t portname[2];
2167 uint32_t nodename[2];
2168
2169#ifdef __BIG_ENDIAN_BITFIELD
2170 uint32_t pref_DID:24;
2171 uint32_t hardAL_PA:8;
2172#else
2173 uint32_t hardAL_PA:8;
2174 uint32_t pref_DID:24;
2175#endif
2176
2177 uint32_t rsvd3[21];
2178} READ_NV_VAR;
2179
2180
2181
2182typedef struct {
2183 uint32_t rsvd1[3];
2184 uint32_t rsvd2;
2185 uint32_t portname[2];
2186 uint32_t nodename[2];
2187
2188#ifdef __BIG_ENDIAN_BITFIELD
2189 uint32_t pref_DID:24;
2190 uint32_t hardAL_PA:8;
2191#else
2192 uint32_t hardAL_PA:8;
2193 uint32_t pref_DID:24;
2194#endif
2195
2196 uint32_t rsvd3[21];
2197} WRITE_NV_VAR;
2198
2199
2200
2201
2202typedef struct {
2203 uint32_t rsvd1;
2204 union {
2205 struct {
2206 struct ulp_bde xmit_bde;
2207 struct ulp_bde rcv_bde;
2208 } s1;
2209 struct {
2210 struct ulp_bde64 xmit_bde64;
2211 struct ulp_bde64 rcv_bde64;
2212 } s2;
2213 } un;
2214} BIU_DIAG_VAR;
2215
2216
2217struct READ_EVENT_LOG_VAR {
2218 uint32_t word1;
2219#define lpfc_event_log_SHIFT 29
2220#define lpfc_event_log_MASK 0x00000001
2221#define lpfc_event_log_WORD word1
2222#define USE_MAILBOX_RESPONSE 1
2223 uint32_t offset;
2224 struct ulp_bde64 rcv_bde64;
2225};
2226
2227
2228
2229typedef struct {
2230#ifdef __BIG_ENDIAN_BITFIELD
2231 uint32_t rsvd1:24;
2232 uint32_t lipsr_AL_PA:8;
2233#else
2234 uint32_t lipsr_AL_PA:8;
2235 uint32_t rsvd1:24;
2236#endif
2237
2238#ifdef __BIG_ENDIAN_BITFIELD
2239 uint8_t fabric_AL_PA;
2240 uint8_t rsvd2;
2241 uint16_t link_flags;
2242#else
2243 uint16_t link_flags;
2244 uint8_t rsvd2;
2245 uint8_t fabric_AL_PA;
2246#endif
2247
2248#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00
2249#define FLAGS_LOCAL_LB 0x01
2250#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02
2251#define FLAGS_TOPOLOGY_MODE_LOOP 0x04
2252#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06
2253#define FLAGS_UNREG_LOGIN_ALL 0x08
2254#define FLAGS_LIRP_LILP 0x80
2255
2256#define FLAGS_TOPOLOGY_FAILOVER 0x0400
2257#define FLAGS_LINK_SPEED 0x0800
2258#define FLAGS_IMED_ABORT 0x04000
2259
2260 uint32_t link_speed;
2261#define LINK_SPEED_AUTO 0x0
2262#define LINK_SPEED_1G 0x1
2263#define LINK_SPEED_2G 0x2
2264#define LINK_SPEED_4G 0x4
2265#define LINK_SPEED_8G 0x8
2266#define LINK_SPEED_10G 0x10
2267#define LINK_SPEED_16G 0x11
2268#define LINK_SPEED_32G 0x14
2269#define LINK_SPEED_64G 0x17
2270#define LINK_SPEED_128G 0x1A
2271#define LINK_SPEED_256G 0x1D
2272
2273} INIT_LINK_VAR;
2274
2275
2276
2277typedef struct {
2278 uint32_t rsvd1;
2279} DOWN_LINK_VAR;
2280
2281
2282
2283typedef struct {
2284#ifdef __BIG_ENDIAN_BITFIELD
2285 uint32_t cr:1;
2286 uint32_t ci:1;
2287 uint32_t cr_delay:6;
2288 uint32_t cr_count:8;
2289 uint32_t rsvd1:8;
2290 uint32_t MaxBBC:8;
2291#else
2292 uint32_t MaxBBC:8;
2293 uint32_t rsvd1:8;
2294 uint32_t cr_count:8;
2295 uint32_t cr_delay:6;
2296 uint32_t ci:1;
2297 uint32_t cr:1;
2298#endif
2299
2300 uint32_t myId;
2301 uint32_t rsvd2;
2302 uint32_t edtov;
2303 uint32_t arbtov;
2304 uint32_t ratov;
2305 uint32_t rttov;
2306 uint32_t altov;
2307 uint32_t crtov;
2308
2309#ifdef __BIG_ENDIAN_BITFIELD
2310 uint32_t rsvd4:19;
2311 uint32_t cscn:1;
2312 uint32_t bbscn:4;
2313 uint32_t rsvd3:8;
2314#else
2315 uint32_t rsvd3:8;
2316 uint32_t bbscn:4;
2317 uint32_t cscn:1;
2318 uint32_t rsvd4:19;
2319#endif
2320
2321#ifdef __BIG_ENDIAN_BITFIELD
2322 uint32_t rrq_enable:1;
2323 uint32_t rrq_immed:1;
2324 uint32_t rsvd5:29;
2325 uint32_t ack0_enable:1;
2326#else
2327 uint32_t ack0_enable:1;
2328 uint32_t rsvd5:29;
2329 uint32_t rrq_immed:1;
2330 uint32_t rrq_enable:1;
2331#endif
2332} CONFIG_LINK;
2333
2334
2335
2336
2337typedef struct {
2338#ifdef __BIG_ENDIAN_BITFIELD
2339 uint16_t offCiocb;
2340 uint16_t numCiocb;
2341 uint16_t offRiocb;
2342 uint16_t numRiocb;
2343#else
2344 uint16_t numCiocb;
2345 uint16_t offCiocb;
2346 uint16_t numRiocb;
2347 uint16_t offRiocb;
2348#endif
2349} RING_DEF;
2350
2351typedef struct {
2352#ifdef __BIG_ENDIAN_BITFIELD
2353 uint32_t unused1:24;
2354 uint32_t numRing:8;
2355#else
2356 uint32_t numRing:8;
2357 uint32_t unused1:24;
2358#endif
2359
2360 RING_DEF ringdef[4];
2361 uint32_t hbainit;
2362} PART_SLIM_VAR;
2363
2364
2365
2366typedef struct {
2367#ifdef __BIG_ENDIAN_BITFIELD
2368 uint32_t unused2:6;
2369 uint32_t recvSeq:1;
2370 uint32_t recvNotify:1;
2371 uint32_t numMask:8;
2372 uint32_t profile:8;
2373 uint32_t unused1:4;
2374 uint32_t ring:4;
2375#else
2376 uint32_t ring:4;
2377 uint32_t unused1:4;
2378 uint32_t profile:8;
2379 uint32_t numMask:8;
2380 uint32_t recvNotify:1;
2381 uint32_t recvSeq:1;
2382 uint32_t unused2:6;
2383#endif
2384
2385#ifdef __BIG_ENDIAN_BITFIELD
2386 uint16_t maxRespXchg;
2387 uint16_t maxOrigXchg;
2388#else
2389 uint16_t maxOrigXchg;
2390 uint16_t maxRespXchg;
2391#endif
2392
2393 RR_REG rrRegs[6];
2394} CONFIG_RING_VAR;
2395
2396
2397
2398typedef struct {
2399 uint32_t ring_no;
2400} RESET_RING_VAR;
2401
2402
2403
2404typedef struct {
2405#ifdef __BIG_ENDIAN_BITFIELD
2406 uint32_t cr:1;
2407 uint32_t ci:1;
2408 uint32_t cr_delay:6;
2409 uint32_t cr_count:8;
2410 uint32_t InitBBC:8;
2411 uint32_t MaxBBC:8;
2412#else
2413 uint32_t MaxBBC:8;
2414 uint32_t InitBBC:8;
2415 uint32_t cr_count:8;
2416 uint32_t cr_delay:6;
2417 uint32_t ci:1;
2418 uint32_t cr:1;
2419#endif
2420
2421#ifdef __BIG_ENDIAN_BITFIELD
2422 uint32_t topology:8;
2423 uint32_t myDid:24;
2424#else
2425 uint32_t myDid:24;
2426 uint32_t topology:8;
2427#endif
2428
2429
2430#ifdef __BIG_ENDIAN_BITFIELD
2431 uint32_t AR:1;
2432 uint32_t IR:1;
2433 uint32_t rsvd1:29;
2434 uint32_t ack0:1;
2435#else
2436 uint32_t ack0:1;
2437 uint32_t rsvd1:29;
2438 uint32_t IR:1;
2439 uint32_t AR:1;
2440#endif
2441
2442 uint32_t edtov;
2443 uint32_t arbtov;
2444 uint32_t ratov;
2445 uint32_t rttov;
2446 uint32_t altov;
2447 uint32_t lmt;
2448#define LMT_RESERVED 0x000
2449#define LMT_1Gb 0x004
2450#define LMT_2Gb 0x008
2451#define LMT_4Gb 0x040
2452#define LMT_8Gb 0x080
2453#define LMT_10Gb 0x100
2454#define LMT_16Gb 0x200
2455#define LMT_32Gb 0x400
2456#define LMT_64Gb 0x800
2457#define LMT_128Gb 0x1000
2458#define LMT_256Gb 0x2000
2459 uint32_t rsvd2;
2460 uint32_t rsvd3;
2461 uint32_t max_xri;
2462 uint32_t max_iocb;
2463 uint32_t max_rpi;
2464 uint32_t avail_xri;
2465 uint32_t avail_iocb;
2466 uint32_t avail_rpi;
2467 uint32_t max_vpi;
2468 uint32_t rsvd4;
2469 uint32_t rsvd5;
2470 uint32_t avail_vpi;
2471} READ_CONFIG_VAR;
2472
2473
2474
2475typedef struct {
2476#ifdef __BIG_ENDIAN_BITFIELD
2477 uint32_t rsvd2:7;
2478 uint32_t recvNotify:1;
2479 uint32_t numMask:8;
2480 uint32_t profile:8;
2481 uint32_t rsvd1:4;
2482 uint32_t ring:4;
2483#else
2484 uint32_t ring:4;
2485 uint32_t rsvd1:4;
2486 uint32_t profile:8;
2487 uint32_t numMask:8;
2488 uint32_t recvNotify:1;
2489 uint32_t rsvd2:7;
2490#endif
2491
2492#ifdef __BIG_ENDIAN_BITFIELD
2493 uint16_t maxResp;
2494 uint16_t maxOrig;
2495#else
2496 uint16_t maxOrig;
2497 uint16_t maxResp;
2498#endif
2499
2500 RR_REG rrRegs[6];
2501
2502#ifdef __BIG_ENDIAN_BITFIELD
2503 uint16_t cmdRingOffset;
2504 uint16_t cmdEntryCnt;
2505 uint16_t rspRingOffset;
2506 uint16_t rspEntryCnt;
2507 uint16_t nextCmdOffset;
2508 uint16_t rsvd3;
2509 uint16_t nextRspOffset;
2510 uint16_t rsvd4;
2511#else
2512 uint16_t cmdEntryCnt;
2513 uint16_t cmdRingOffset;
2514 uint16_t rspEntryCnt;
2515 uint16_t rspRingOffset;
2516 uint16_t rsvd3;
2517 uint16_t nextCmdOffset;
2518 uint16_t rsvd4;
2519 uint16_t nextRspOffset;
2520#endif
2521} READ_RCONF_VAR;
2522
2523
2524
2525
2526typedef struct {
2527 uint32_t rsvd1;
2528 uint32_t rsvd2;
2529 union {
2530 struct ulp_bde sp;
2531
2532 struct ulp_bde64 sp64;
2533 } un;
2534#ifdef __BIG_ENDIAN_BITFIELD
2535 uint16_t rsvd3;
2536 uint16_t vpi;
2537#else
2538 uint16_t vpi;
2539 uint16_t rsvd3;
2540#endif
2541} READ_SPARM_VAR;
2542
2543
2544
2545typedef struct {
2546#ifdef __BIG_ENDIAN_BITFIELD
2547 uint32_t rsvd1:31;
2548 uint32_t clrCounters:1;
2549 uint16_t activeXriCnt;
2550 uint16_t activeRpiCnt;
2551#else
2552 uint32_t clrCounters:1;
2553 uint32_t rsvd1:31;
2554 uint16_t activeRpiCnt;
2555 uint16_t activeXriCnt;
2556#endif
2557
2558 uint32_t xmitByteCnt;
2559 uint32_t rcvByteCnt;
2560 uint32_t xmitFrameCnt;
2561 uint32_t rcvFrameCnt;
2562 uint32_t xmitSeqCnt;
2563 uint32_t rcvSeqCnt;
2564 uint32_t totalOrigExchanges;
2565 uint32_t totalRespExchanges;
2566 uint32_t rcvPbsyCnt;
2567 uint32_t rcvFbsyCnt;
2568} READ_STATUS_VAR;
2569
2570
2571
2572
2573typedef struct {
2574#ifdef __BIG_ENDIAN_BITFIELD
2575 uint16_t nextRpi;
2576 uint16_t reqRpi;
2577 uint32_t rsvd2:8;
2578 uint32_t DID:24;
2579#else
2580 uint16_t reqRpi;
2581 uint16_t nextRpi;
2582 uint32_t DID:24;
2583 uint32_t rsvd2:8;
2584#endif
2585
2586 union {
2587 struct ulp_bde sp;
2588 struct ulp_bde64 sp64;
2589 } un;
2590
2591} READ_RPI_VAR;
2592
2593
2594
2595typedef struct {
2596#ifdef __BIG_ENDIAN_BITFIELD
2597 uint16_t nextXri;
2598 uint16_t reqXri;
2599 uint16_t rsvd1;
2600 uint16_t rpi;
2601 uint32_t rsvd2:8;
2602 uint32_t DID:24;
2603 uint32_t rsvd3:8;
2604 uint32_t SID:24;
2605 uint32_t rsvd4;
2606 uint8_t seqId;
2607 uint8_t rsvd5;
2608 uint16_t seqCount;
2609 uint16_t oxId;
2610 uint16_t rxId;
2611 uint32_t rsvd6:30;
2612 uint32_t si:1;
2613 uint32_t exchOrig:1;
2614#else
2615 uint16_t reqXri;
2616 uint16_t nextXri;
2617 uint16_t rpi;
2618 uint16_t rsvd1;
2619 uint32_t DID:24;
2620 uint32_t rsvd2:8;
2621 uint32_t SID:24;
2622 uint32_t rsvd3:8;
2623 uint32_t rsvd4;
2624 uint16_t seqCount;
2625 uint8_t rsvd5;
2626 uint8_t seqId;
2627 uint16_t rxId;
2628 uint16_t oxId;
2629 uint32_t exchOrig:1;
2630 uint32_t si:1;
2631 uint32_t rsvd6:30;
2632#endif
2633} READ_XRI_VAR;
2634
2635
2636
2637typedef struct {
2638#ifdef __BIG_ENDIAN_BITFIELD
2639 uint32_t cv:1;
2640 uint32_t rr:1;
2641 uint32_t rsvd2:2;
2642 uint32_t v3req:1;
2643 uint32_t v3rsp:1;
2644 uint32_t rsvd1:25;
2645 uint32_t rv:1;
2646#else
2647 uint32_t rv:1;
2648 uint32_t rsvd1:25;
2649 uint32_t v3rsp:1;
2650 uint32_t v3req:1;
2651 uint32_t rsvd2:2;
2652 uint32_t rr:1;
2653 uint32_t cv:1;
2654#endif
2655
2656 uint32_t biuRev;
2657 uint32_t smRev;
2658 union {
2659 uint32_t smFwRev;
2660 struct {
2661#ifdef __BIG_ENDIAN_BITFIELD
2662 uint8_t ProgType;
2663 uint8_t ProgId;
2664 uint16_t ProgVer:4;
2665 uint16_t ProgRev:4;
2666 uint16_t ProgFixLvl:2;
2667 uint16_t ProgDistType:2;
2668 uint16_t DistCnt:4;
2669#else
2670 uint16_t DistCnt:4;
2671 uint16_t ProgDistType:2;
2672 uint16_t ProgFixLvl:2;
2673 uint16_t ProgRev:4;
2674 uint16_t ProgVer:4;
2675 uint8_t ProgId;
2676 uint8_t ProgType;
2677#endif
2678
2679 } b;
2680 } un;
2681 uint32_t endecRev;
2682#ifdef __BIG_ENDIAN_BITFIELD
2683 uint8_t feaLevelHigh;
2684 uint8_t feaLevelLow;
2685 uint8_t fcphHigh;
2686 uint8_t fcphLow;
2687#else
2688 uint8_t fcphLow;
2689 uint8_t fcphHigh;
2690 uint8_t feaLevelLow;
2691 uint8_t feaLevelHigh;
2692#endif
2693
2694 uint32_t postKernRev;
2695 uint32_t opFwRev;
2696 uint8_t opFwName[16];
2697 uint32_t sli1FwRev;
2698 uint8_t sli1FwName[16];
2699 uint32_t sli2FwRev;
2700 uint8_t sli2FwName[16];
2701 uint32_t sli3Feat;
2702 uint32_t RandomData[6];
2703} READ_REV_VAR;
2704
2705
2706
2707typedef struct {
2708 uint32_t word0;
2709
2710#define lpfc_read_link_stat_rec_SHIFT 0
2711#define lpfc_read_link_stat_rec_MASK 0x1
2712#define lpfc_read_link_stat_rec_WORD word0
2713
2714#define lpfc_read_link_stat_gec_SHIFT 1
2715#define lpfc_read_link_stat_gec_MASK 0x1
2716#define lpfc_read_link_stat_gec_WORD word0
2717
2718#define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2719#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2720#define lpfc_read_link_stat_w02oftow23of_WORD word0
2721
2722#define lpfc_read_link_stat_rsvd_SHIFT 24
2723#define lpfc_read_link_stat_rsvd_MASK 0x1F
2724#define lpfc_read_link_stat_rsvd_WORD word0
2725
2726#define lpfc_read_link_stat_gec2_SHIFT 29
2727#define lpfc_read_link_stat_gec2_MASK 0x1
2728#define lpfc_read_link_stat_gec2_WORD word0
2729
2730#define lpfc_read_link_stat_clrc_SHIFT 30
2731#define lpfc_read_link_stat_clrc_MASK 0x1
2732#define lpfc_read_link_stat_clrc_WORD word0
2733
2734#define lpfc_read_link_stat_clof_SHIFT 31
2735#define lpfc_read_link_stat_clof_MASK 0x1
2736#define lpfc_read_link_stat_clof_WORD word0
2737
2738 uint32_t linkFailureCnt;
2739 uint32_t lossSyncCnt;
2740 uint32_t lossSignalCnt;
2741 uint32_t primSeqErrCnt;
2742 uint32_t invalidXmitWord;
2743 uint32_t crcCnt;
2744 uint32_t primSeqTimeout;
2745 uint32_t elasticOverrun;
2746 uint32_t arbTimeout;
2747 uint32_t advRecBufCredit;
2748 uint32_t curRecBufCredit;
2749 uint32_t advTransBufCredit;
2750 uint32_t curTransBufCredit;
2751 uint32_t recEofCount;
2752 uint32_t recEofdtiCount;
2753 uint32_t recEofniCount;
2754 uint32_t recSofcount;
2755 uint32_t rsvd1;
2756 uint32_t rsvd2;
2757 uint32_t recDrpXriCount;
2758 uint32_t fecCorrBlkCount;
2759 uint32_t fecUncorrBlkCount;
2760} READ_LNK_VAR;
2761
2762
2763
2764
2765typedef struct {
2766#ifdef __BIG_ENDIAN_BITFIELD
2767 uint16_t rsvd1;
2768 uint16_t rpi;
2769 uint32_t rsvd2:8;
2770 uint32_t did:24;
2771#else
2772 uint16_t rpi;
2773 uint16_t rsvd1;
2774 uint32_t did:24;
2775 uint32_t rsvd2:8;
2776#endif
2777
2778 union {
2779 struct ulp_bde sp;
2780 struct ulp_bde64 sp64;
2781 } un;
2782
2783#ifdef __BIG_ENDIAN_BITFIELD
2784 uint16_t rsvd6;
2785 uint16_t vpi;
2786#else
2787 uint16_t vpi;
2788 uint16_t rsvd6;
2789#endif
2790
2791} REG_LOGIN_VAR;
2792
2793
2794typedef union {
2795 struct {
2796#ifdef __BIG_ENDIAN_BITFIELD
2797 uint16_t rsvd1:12;
2798 uint16_t wd30_class:4;
2799 uint16_t xri;
2800#else
2801 uint16_t xri;
2802 uint16_t wd30_class:4;
2803 uint16_t rsvd1:12;
2804#endif
2805 } f;
2806 uint32_t word;
2807} REG_WD30;
2808
2809
2810
2811typedef struct {
2812#ifdef __BIG_ENDIAN_BITFIELD
2813 uint16_t rsvd1;
2814 uint16_t rpi;
2815 uint32_t rsvd2;
2816 uint32_t rsvd3;
2817 uint32_t rsvd4;
2818 uint32_t rsvd5;
2819 uint16_t rsvd6;
2820 uint16_t vpi;
2821#else
2822 uint16_t rpi;
2823 uint16_t rsvd1;
2824 uint32_t rsvd2;
2825 uint32_t rsvd3;
2826 uint32_t rsvd4;
2827 uint32_t rsvd5;
2828 uint16_t vpi;
2829 uint16_t rsvd6;
2830#endif
2831} UNREG_LOGIN_VAR;
2832
2833
2834typedef struct {
2835#ifdef __BIG_ENDIAN_BITFIELD
2836 uint32_t rsvd1;
2837 uint32_t rsvd2:7;
2838 uint32_t upd:1;
2839 uint32_t sid:24;
2840 uint32_t wwn[2];
2841 uint32_t rsvd5;
2842 uint16_t vfi;
2843 uint16_t vpi;
2844#else
2845 uint32_t rsvd1;
2846 uint32_t sid:24;
2847 uint32_t upd:1;
2848 uint32_t rsvd2:7;
2849 uint32_t wwn[2];
2850 uint32_t rsvd5;
2851 uint16_t vpi;
2852 uint16_t vfi;
2853#endif
2854} REG_VPI_VAR;
2855
2856
2857typedef struct {
2858 uint32_t rsvd1;
2859#ifdef __BIG_ENDIAN_BITFIELD
2860 uint16_t rsvd2;
2861 uint16_t sli4_vpi;
2862#else
2863 uint16_t sli4_vpi;
2864 uint16_t rsvd2;
2865#endif
2866 uint32_t rsvd3;
2867 uint32_t rsvd4;
2868 uint32_t rsvd5;
2869#ifdef __BIG_ENDIAN_BITFIELD
2870 uint16_t rsvd6;
2871 uint16_t vpi;
2872#else
2873 uint16_t vpi;
2874 uint16_t rsvd6;
2875#endif
2876} UNREG_VPI_VAR;
2877
2878
2879
2880typedef struct {
2881 uint32_t did;
2882 uint32_t rsvd2;
2883 uint32_t rsvd3;
2884 uint32_t rsvd4;
2885 uint32_t rsvd5;
2886#ifdef __BIG_ENDIAN_BITFIELD
2887 uint16_t rsvd6;
2888 uint16_t vpi;
2889#else
2890 uint16_t vpi;
2891 uint16_t rsvd6;
2892#endif
2893} UNREG_D_ID_VAR;
2894
2895
2896struct lpfc_mbx_read_top {
2897 uint32_t eventTag;
2898 uint32_t word2;
2899#define lpfc_mbx_read_top_fa_SHIFT 12
2900#define lpfc_mbx_read_top_fa_MASK 0x00000001
2901#define lpfc_mbx_read_top_fa_WORD word2
2902#define lpfc_mbx_read_top_mm_SHIFT 11
2903#define lpfc_mbx_read_top_mm_MASK 0x00000001
2904#define lpfc_mbx_read_top_mm_WORD word2
2905#define lpfc_mbx_read_top_pb_SHIFT 9
2906#define lpfc_mbx_read_top_pb_MASK 0X00000001
2907#define lpfc_mbx_read_top_pb_WORD word2
2908#define lpfc_mbx_read_top_il_SHIFT 8
2909#define lpfc_mbx_read_top_il_MASK 0x00000001
2910#define lpfc_mbx_read_top_il_WORD word2
2911#define lpfc_mbx_read_top_att_type_SHIFT 0
2912#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2913#define lpfc_mbx_read_top_att_type_WORD word2
2914#define LPFC_ATT_RESERVED 0x00
2915#define LPFC_ATT_LINK_UP 0x01
2916#define LPFC_ATT_LINK_DOWN 0x02
2917#define LPFC_ATT_UNEXP_WWPN 0x06
2918 uint32_t word3;
2919#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2920#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2921#define lpfc_mbx_read_top_alpa_granted_WORD word3
2922#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2923#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2924#define lpfc_mbx_read_top_lip_alps_WORD word3
2925#define lpfc_mbx_read_top_lip_type_SHIFT 8
2926#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2927#define lpfc_mbx_read_top_lip_type_WORD word3
2928#define lpfc_mbx_read_top_topology_SHIFT 0
2929#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2930#define lpfc_mbx_read_top_topology_WORD word3
2931#define LPFC_TOPOLOGY_PT_PT 0x01
2932#define LPFC_TOPOLOGY_LOOP 0x02
2933#define LPFC_TOPOLOGY_MM 0x05
2934
2935 struct ulp_bde64 lilpBde64;
2936#define LPFC_ALPA_MAP_SIZE 128
2937 uint32_t word7;
2938#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2939#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2940#define lpfc_mbx_read_top_ld_lu_WORD word7
2941#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2942#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2943#define lpfc_mbx_read_top_ld_tf_WORD word7
2944#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2945#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2946#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2947#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2948#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2949#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2950#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2951#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2952#define lpfc_mbx_read_top_ld_tx_WORD word7
2953#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2954#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2955#define lpfc_mbx_read_top_ld_rx_WORD word7
2956 uint32_t word8;
2957#define lpfc_mbx_read_top_lu_SHIFT 31
2958#define lpfc_mbx_read_top_lu_MASK 0x00000001
2959#define lpfc_mbx_read_top_lu_WORD word8
2960#define lpfc_mbx_read_top_tf_SHIFT 30
2961#define lpfc_mbx_read_top_tf_MASK 0x00000001
2962#define lpfc_mbx_read_top_tf_WORD word8
2963#define lpfc_mbx_read_top_link_spd_SHIFT 8
2964#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2965#define lpfc_mbx_read_top_link_spd_WORD word8
2966#define lpfc_mbx_read_top_nl_port_SHIFT 4
2967#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2968#define lpfc_mbx_read_top_nl_port_WORD word8
2969#define lpfc_mbx_read_top_tx_SHIFT 2
2970#define lpfc_mbx_read_top_tx_MASK 0x00000003
2971#define lpfc_mbx_read_top_tx_WORD word8
2972#define lpfc_mbx_read_top_rx_SHIFT 0
2973#define lpfc_mbx_read_top_rx_MASK 0x00000003
2974#define lpfc_mbx_read_top_rx_WORD word8
2975#define LPFC_LINK_SPEED_UNKNOWN 0x0
2976#define LPFC_LINK_SPEED_1GHZ 0x04
2977#define LPFC_LINK_SPEED_2GHZ 0x08
2978#define LPFC_LINK_SPEED_4GHZ 0x10
2979#define LPFC_LINK_SPEED_8GHZ 0x20
2980#define LPFC_LINK_SPEED_10GHZ 0x40
2981#define LPFC_LINK_SPEED_16GHZ 0x80
2982#define LPFC_LINK_SPEED_32GHZ 0x90
2983#define LPFC_LINK_SPEED_64GHZ 0xA0
2984#define LPFC_LINK_SPEED_128GHZ 0xB0
2985#define LPFC_LINK_SPEED_256GHZ 0xC0
2986};
2987
2988
2989
2990typedef struct {
2991 uint32_t eventTag;
2992 uint32_t rsvd1;
2993} CLEAR_LA_VAR;
2994
2995
2996
2997typedef struct {
2998#ifdef __BIG_ENDIAN_BITFIELD
2999 uint32_t rsvd:25;
3000 uint32_t ra:1;
3001 uint32_t co:1;
3002 uint32_t cv:1;
3003 uint32_t type:4;
3004 uint32_t entry_index:16;
3005 uint32_t region_id:16;
3006#else
3007 uint32_t type:4;
3008 uint32_t cv:1;
3009 uint32_t co:1;
3010 uint32_t ra:1;
3011 uint32_t rsvd:25;
3012 uint32_t region_id:16;
3013 uint32_t entry_index:16;
3014#endif
3015
3016 uint32_t sli4_length;
3017 uint32_t word_cnt;
3018 uint32_t resp_offset;
3019} DUMP_VAR;
3020
3021#define DMP_MEM_REG 0x1
3022#define DMP_NV_PARAMS 0x2
3023#define DMP_LMSD 0x3
3024#define DMP_WELL_KNOWN 0x4
3025
3026#define DMP_REGION_VPD 0xe
3027#define DMP_VPD_SIZE 0x400
3028#define DMP_RSP_OFFSET 0x14
3029#define DMP_RSP_SIZE 0x6C
3030
3031#define DMP_REGION_VPORT 0x16
3032#define DMP_VPORT_REGION_SIZE 0x200
3033#define DMP_MBOX_OFFSET_WORD 0x5
3034
3035#define DMP_REGION_23 0x17
3036#define DMP_RGN23_SIZE 0x400
3037
3038#define WAKE_UP_PARMS_REGION_ID 4
3039#define WAKE_UP_PARMS_WORD_SIZE 15
3040
3041struct vport_rec {
3042 uint8_t wwpn[8];
3043 uint8_t wwnn[8];
3044};
3045
3046#define VPORT_INFO_SIG 0x32324752
3047#define VPORT_INFO_REV_MASK 0xff
3048#define VPORT_INFO_REV 0x1
3049#define MAX_STATIC_VPORT_COUNT 16
3050struct static_vport_info {
3051 uint32_t signature;
3052 uint32_t rev;
3053 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3054 uint32_t resvd[66];
3055};
3056
3057
3058struct prog_id {
3059#ifdef __BIG_ENDIAN_BITFIELD
3060 uint8_t type;
3061 uint8_t id;
3062 uint32_t ver:4;
3063 uint32_t rev:4;
3064 uint32_t lev:2;
3065 uint32_t dist:2;
3066 uint32_t num:4;
3067#else
3068 uint32_t num:4;
3069 uint32_t dist:2;
3070 uint32_t lev:2;
3071 uint32_t rev:4;
3072 uint32_t ver:4;
3073 uint8_t id;
3074 uint8_t type;
3075#endif
3076};
3077
3078
3079
3080struct update_cfg_var {
3081#ifdef __BIG_ENDIAN_BITFIELD
3082 uint32_t rsvd2:16;
3083 uint32_t type:8;
3084 uint32_t rsvd:1;
3085 uint32_t ra:1;
3086 uint32_t co:1;
3087 uint32_t cv:1;
3088 uint32_t req:4;
3089 uint32_t entry_length:16;
3090 uint32_t region_id:16;
3091#else
3092 uint32_t req:4;
3093 uint32_t cv:1;
3094 uint32_t co:1;
3095 uint32_t ra:1;
3096 uint32_t rsvd:1;
3097 uint32_t type:8;
3098 uint32_t rsvd2:16;
3099 uint32_t region_id:16;
3100 uint32_t entry_length:16;
3101#endif
3102
3103 uint32_t resp_info;
3104 uint32_t byte_cnt;
3105 uint32_t data_offset;
3106};
3107
3108struct hbq_mask {
3109#ifdef __BIG_ENDIAN_BITFIELD
3110 uint8_t tmatch;
3111 uint8_t tmask;
3112 uint8_t rctlmatch;
3113 uint8_t rctlmask;
3114#else
3115 uint8_t rctlmask;
3116 uint8_t rctlmatch;
3117 uint8_t tmask;
3118 uint8_t tmatch;
3119#endif
3120};
3121
3122
3123
3124
3125struct config_hbq_var {
3126#ifdef __BIG_ENDIAN_BITFIELD
3127 uint32_t rsvd1 :7;
3128 uint32_t recvNotify :1;
3129 uint32_t numMask :8;
3130 uint32_t profile :8;
3131 uint32_t rsvd2 :8;
3132#else
3133 uint32_t rsvd2 :8;
3134 uint32_t profile :8;
3135 uint32_t numMask :8;
3136 uint32_t recvNotify :1;
3137 uint32_t rsvd1 :7;
3138#endif
3139
3140#ifdef __BIG_ENDIAN_BITFIELD
3141 uint32_t hbqId :16;
3142 uint32_t rsvd3 :12;
3143 uint32_t ringMask :4;
3144#else
3145 uint32_t ringMask :4;
3146 uint32_t rsvd3 :12;
3147 uint32_t hbqId :16;
3148#endif
3149
3150#ifdef __BIG_ENDIAN_BITFIELD
3151 uint32_t entry_count :16;
3152 uint32_t rsvd4 :8;
3153 uint32_t headerLen :8;
3154#else
3155 uint32_t headerLen :8;
3156 uint32_t rsvd4 :8;
3157 uint32_t entry_count :16;
3158#endif
3159
3160 uint32_t hbqaddrLow;
3161 uint32_t hbqaddrHigh;
3162
3163#ifdef __BIG_ENDIAN_BITFIELD
3164 uint32_t rsvd5 :31;
3165 uint32_t logEntry :1;
3166#else
3167 uint32_t logEntry :1;
3168 uint32_t rsvd5 :31;
3169#endif
3170
3171 uint32_t rsvd6;
3172 uint32_t rsvd7;
3173 uint32_t rsvd8;
3174
3175 struct hbq_mask hbqMasks[6];
3176
3177
3178 union {
3179 uint32_t allprofiles[12];
3180
3181 struct {
3182 #ifdef __BIG_ENDIAN_BITFIELD
3183 uint32_t seqlenoff :16;
3184 uint32_t maxlen :16;
3185 #else
3186 uint32_t maxlen :16;
3187 uint32_t seqlenoff :16;
3188 #endif
3189 #ifdef __BIG_ENDIAN_BITFIELD
3190 uint32_t rsvd1 :28;
3191 uint32_t seqlenbcnt :4;
3192 #else
3193 uint32_t seqlenbcnt :4;
3194 uint32_t rsvd1 :28;
3195 #endif
3196 uint32_t rsvd[10];
3197 } profile2;
3198
3199 struct {
3200 #ifdef __BIG_ENDIAN_BITFIELD
3201 uint32_t seqlenoff :16;
3202 uint32_t maxlen :16;
3203 #else
3204 uint32_t maxlen :16;
3205 uint32_t seqlenoff :16;
3206 #endif
3207 #ifdef __BIG_ENDIAN_BITFIELD
3208 uint32_t cmdcodeoff :28;
3209 uint32_t rsvd1 :12;
3210 uint32_t seqlenbcnt :4;
3211 #else
3212 uint32_t seqlenbcnt :4;
3213 uint32_t rsvd1 :12;
3214 uint32_t cmdcodeoff :28;
3215 #endif
3216 uint32_t cmdmatch[8];
3217
3218 uint32_t rsvd[2];
3219 } profile3;
3220
3221 struct {
3222 #ifdef __BIG_ENDIAN_BITFIELD
3223 uint32_t seqlenoff :16;
3224 uint32_t maxlen :16;
3225 #else
3226 uint32_t maxlen :16;
3227 uint32_t seqlenoff :16;
3228 #endif
3229 #ifdef __BIG_ENDIAN_BITFIELD
3230 uint32_t cmdcodeoff :28;
3231 uint32_t rsvd1 :12;
3232 uint32_t seqlenbcnt :4;
3233 #else
3234 uint32_t seqlenbcnt :4;
3235 uint32_t rsvd1 :12;
3236 uint32_t cmdcodeoff :28;
3237 #endif
3238 uint32_t cmdmatch[8];
3239
3240 uint32_t rsvd[2];
3241 } profile5;
3242
3243 } profiles;
3244
3245};
3246
3247
3248
3249
3250typedef struct {
3251#ifdef __BIG_ENDIAN_BITFIELD
3252 uint32_t cBE : 1;
3253 uint32_t cET : 1;
3254 uint32_t cHpcb : 1;
3255 uint32_t cMA : 1;
3256 uint32_t sli_mode : 4;
3257 uint32_t pcbLen : 24;
3258
3259#else
3260 uint32_t pcbLen : 24;
3261
3262 uint32_t sli_mode : 4;
3263 uint32_t cMA : 1;
3264 uint32_t cHpcb : 1;
3265 uint32_t cET : 1;
3266 uint32_t cBE : 1;
3267#endif
3268
3269 uint32_t pcbLow;
3270 uint32_t pcbHigh;
3271 uint32_t hbainit[5];
3272#ifdef __BIG_ENDIAN_BITFIELD
3273 uint32_t hps : 1;
3274 uint32_t rsvd : 31;
3275#else
3276 uint32_t rsvd : 31;
3277 uint32_t hps : 1;
3278#endif
3279
3280#ifdef __BIG_ENDIAN_BITFIELD
3281 uint32_t rsvd1 : 19;
3282 uint32_t cdss : 1;
3283 uint32_t casabt : 1;
3284 uint32_t rsvd2 : 2;
3285 uint32_t cbg : 1;
3286 uint32_t cmv : 1;
3287 uint32_t ccrp : 1;
3288 uint32_t csah : 1;
3289 uint32_t chbs : 1;
3290 uint32_t cinb : 1;
3291 uint32_t cerbm : 1;
3292 uint32_t cmx : 1;
3293 uint32_t cmr : 1;
3294#else
3295 uint32_t cmr : 1;
3296 uint32_t cmx : 1;
3297 uint32_t cerbm : 1;
3298 uint32_t cinb : 1;
3299 uint32_t chbs : 1;
3300 uint32_t csah : 1;
3301 uint32_t ccrp : 1;
3302 uint32_t cmv : 1;
3303 uint32_t cbg : 1;
3304 uint32_t rsvd2 : 2;
3305 uint32_t casabt : 1;
3306 uint32_t cdss : 1;
3307 uint32_t rsvd1 : 19;
3308#endif
3309#ifdef __BIG_ENDIAN_BITFIELD
3310 uint32_t rsvd3 : 19;
3311 uint32_t gdss : 1;
3312 uint32_t gasabt : 1;
3313 uint32_t rsvd4 : 2;
3314 uint32_t gbg : 1;
3315 uint32_t gmv : 1;
3316 uint32_t gcrp : 1;
3317 uint32_t gsah : 1;
3318 uint32_t ghbs : 1;
3319 uint32_t ginb : 1;
3320 uint32_t gerbm : 1;
3321 uint32_t gmx : 1;
3322 uint32_t gmr : 1;
3323#else
3324 uint32_t gmr : 1;
3325 uint32_t gmx : 1;
3326 uint32_t gerbm : 1;
3327 uint32_t ginb : 1;
3328 uint32_t ghbs : 1;
3329 uint32_t gsah : 1;
3330 uint32_t gcrp : 1;
3331 uint32_t gmv : 1;
3332 uint32_t gbg : 1;
3333 uint32_t rsvd4 : 2;
3334 uint32_t gasabt : 1;
3335 uint32_t gdss : 1;
3336 uint32_t rsvd3 : 19;
3337#endif
3338
3339#ifdef __BIG_ENDIAN_BITFIELD
3340 uint32_t max_rpi : 16;
3341 uint32_t max_xri : 16;
3342#else
3343 uint32_t max_xri : 16;
3344 uint32_t max_rpi : 16;
3345#endif
3346
3347#ifdef __BIG_ENDIAN_BITFIELD
3348 uint32_t max_hbq : 16;
3349 uint32_t rsvd5 : 16;
3350#else
3351 uint32_t rsvd5 : 16;
3352 uint32_t max_hbq : 16;
3353#endif
3354
3355 uint32_t rsvd6;
3356
3357#ifdef __BIG_ENDIAN_BITFIELD
3358 uint32_t fips_rev : 3;
3359 uint32_t fips_level : 4;
3360 uint32_t sec_err : 9;
3361 uint32_t max_vpi : 16;
3362#else
3363 uint32_t max_vpi : 16;
3364 uint32_t sec_err : 9;
3365 uint32_t fips_level : 4;
3366 uint32_t fips_rev : 3;
3367#endif
3368
3369} CONFIG_PORT_VAR;
3370
3371
3372struct config_msi_var {
3373#ifdef __BIG_ENDIAN_BITFIELD
3374 uint32_t dfltMsgNum:8;
3375 uint32_t rsvd1:11;
3376 uint32_t NID:5;
3377 uint32_t rsvd2:5;
3378 uint32_t dfltPresent:1;
3379 uint32_t addFlag:1;
3380 uint32_t reportFlag:1;
3381#else
3382 uint32_t reportFlag:1;
3383 uint32_t addFlag:1;
3384 uint32_t dfltPresent:1;
3385 uint32_t rsvd2:5;
3386 uint32_t NID:5;
3387 uint32_t rsvd1:11;
3388 uint32_t dfltMsgNum:8;
3389#endif
3390 uint32_t attentionConditions[2];
3391 uint8_t attentionId[16];
3392 uint8_t messageNumberByHA[64];
3393 uint8_t messageNumberByID[16];
3394 uint32_t autoClearHA[2];
3395#ifdef __BIG_ENDIAN_BITFIELD
3396 uint32_t rsvd3:16;
3397 uint32_t autoClearID:16;
3398#else
3399 uint32_t autoClearID:16;
3400 uint32_t rsvd3:16;
3401#endif
3402 uint32_t rsvd4;
3403};
3404
3405
3406
3407
3408#define SLIMOFF 0x30
3409
3410typedef struct _SLI2_RDSC {
3411 uint32_t cmdEntries;
3412 uint32_t cmdAddrLow;
3413 uint32_t cmdAddrHigh;
3414
3415 uint32_t rspEntries;
3416 uint32_t rspAddrLow;
3417 uint32_t rspAddrHigh;
3418} SLI2_RDSC;
3419
3420typedef struct _PCB {
3421#ifdef __BIG_ENDIAN_BITFIELD
3422 uint32_t type:8;
3423#define TYPE_NATIVE_SLI2 0x01
3424 uint32_t feature:8;
3425#define FEATURE_INITIAL_SLI2 0x01
3426 uint32_t rsvd:12;
3427 uint32_t maxRing:4;
3428#else
3429 uint32_t maxRing:4;
3430 uint32_t rsvd:12;
3431 uint32_t feature:8;
3432#define FEATURE_INITIAL_SLI2 0x01
3433 uint32_t type:8;
3434#define TYPE_NATIVE_SLI2 0x01
3435#endif
3436
3437 uint32_t mailBoxSize;
3438 uint32_t mbAddrLow;
3439 uint32_t mbAddrHigh;
3440
3441 uint32_t hgpAddrLow;
3442 uint32_t hgpAddrHigh;
3443
3444 uint32_t pgpAddrLow;
3445 uint32_t pgpAddrHigh;
3446 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3447} PCB_t;
3448
3449
3450typedef struct {
3451#ifdef __BIG_ENDIAN_BITFIELD
3452 uint32_t rsvd0:27;
3453 uint32_t discardFarp:1;
3454 uint32_t IPEnable:1;
3455 uint32_t nodeName:1;
3456 uint32_t portName:1;
3457 uint32_t filterEnable:1;
3458#else
3459 uint32_t filterEnable:1;
3460 uint32_t portName:1;
3461 uint32_t nodeName:1;
3462 uint32_t IPEnable:1;
3463 uint32_t discardFarp:1;
3464 uint32_t rsvd:27;
3465#endif
3466
3467 uint8_t portname[8];
3468 uint8_t nodename[8];
3469 uint32_t rsvd1;
3470 uint32_t rsvd2;
3471 uint32_t rsvd3;
3472 uint32_t IPAddress;
3473} CONFIG_FARP_VAR;
3474
3475
3476
3477typedef struct {
3478#ifdef __BIG_ENDIAN_BITFIELD
3479 uint32_t rsvd:30;
3480 uint32_t ring:2;
3481#else
3482 uint32_t ring:2;
3483 uint32_t rsvd:30;
3484#endif
3485} ASYNCEVT_ENABLE_VAR;
3486
3487
3488#define MAILBOX_CMD_WSIZE 32
3489#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3490
3491#define MAILBOX_EXT_WSIZE 512
3492#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3493#define MAILBOX_HBA_EXT_OFFSET 0x100
3494
3495#define MAILBOX_SYSFS_MAX 4096
3496
3497typedef union {
3498 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
3499
3500
3501 LOAD_SM_VAR varLdSM;
3502 READ_NV_VAR varRDnvp;
3503 WRITE_NV_VAR varWTnvp;
3504 BIU_DIAG_VAR varBIUdiag;
3505 INIT_LINK_VAR varInitLnk;
3506 DOWN_LINK_VAR varDwnLnk;
3507 CONFIG_LINK varCfgLnk;
3508 PART_SLIM_VAR varSlim;
3509 CONFIG_RING_VAR varCfgRing;
3510 RESET_RING_VAR varRstRing;
3511 READ_CONFIG_VAR varRdConfig;
3512 READ_RCONF_VAR varRdRConfig;
3513 READ_SPARM_VAR varRdSparm;
3514 READ_STATUS_VAR varRdStatus;
3515 READ_RPI_VAR varRdRPI;
3516 READ_XRI_VAR varRdXRI;
3517 READ_REV_VAR varRdRev;
3518 READ_LNK_VAR varRdLnk;
3519 REG_LOGIN_VAR varRegLogin;
3520 UNREG_LOGIN_VAR varUnregLogin;
3521 CLEAR_LA_VAR varClearLA;
3522 DUMP_VAR varDmp;
3523 UNREG_D_ID_VAR varUnregDID;
3524 CONFIG_FARP_VAR varCfgFarp;
3525
3526
3527 struct config_hbq_var varCfgHbq;
3528 struct update_cfg_var varUpdateCfg;
3529 CONFIG_PORT_VAR varCfgPort;
3530 struct lpfc_mbx_read_top varReadTop;
3531 REG_VPI_VAR varRegVpi;
3532 UNREG_VPI_VAR varUnregVpi;
3533 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent;
3534 struct READ_EVENT_LOG_VAR varRdEventLog;
3535
3536
3537 struct config_msi_var varCfgMSI;
3538} MAILVARIANTS;
3539
3540
3541
3542
3543
3544struct lpfc_hgp {
3545 __le32 cmdPutInx;
3546 __le32 rspGetInx;
3547};
3548
3549struct lpfc_pgp {
3550 __le32 cmdGetInx;
3551 __le32 rspPutInx;
3552};
3553
3554struct sli2_desc {
3555 uint32_t unused1[16];
3556 struct lpfc_hgp host[MAX_SLI3_RINGS];
3557 struct lpfc_pgp port[MAX_SLI3_RINGS];
3558};
3559
3560struct sli3_desc {
3561 struct lpfc_hgp host[MAX_SLI3_RINGS];
3562 uint32_t reserved[8];
3563 uint32_t hbq_put[16];
3564};
3565
3566struct sli3_pgp {
3567 struct lpfc_pgp port[MAX_SLI3_RINGS];
3568 uint32_t hbq_get[16];
3569};
3570
3571union sli_var {
3572 struct sli2_desc s2;
3573 struct sli3_desc s3;
3574 struct sli3_pgp s3_pgp;
3575};
3576
3577typedef struct {
3578#ifdef __BIG_ENDIAN_BITFIELD
3579 uint16_t mbxStatus;
3580 uint8_t mbxCommand;
3581 uint8_t mbxReserved:6;
3582 uint8_t mbxHc:1;
3583 uint8_t mbxOwner:1;
3584#else
3585 uint8_t mbxOwner:1;
3586 uint8_t mbxHc:1;
3587 uint8_t mbxReserved:6;
3588 uint8_t mbxCommand;
3589 uint16_t mbxStatus;
3590#endif
3591
3592 MAILVARIANTS un;
3593 union sli_var us;
3594} MAILBOX_t;
3595
3596
3597
3598
3599
3600typedef struct {
3601#ifdef __BIG_ENDIAN_BITFIELD
3602 uint8_t statAction;
3603 uint8_t statRsn;
3604 uint8_t statBaExp;
3605 uint8_t statLocalError;
3606#else
3607 uint8_t statLocalError;
3608 uint8_t statBaExp;
3609 uint8_t statRsn;
3610 uint8_t statAction;
3611#endif
3612
3613#define RJT_BAD_D_ID 0x01
3614#define RJT_BAD_S_ID 0x02
3615#define RJT_UNAVAIL_TEMP 0x03
3616#define RJT_UNAVAIL_PERM 0x04
3617#define RJT_UNSUP_CLASS 0x05
3618#define RJT_DELIM_ERR 0x06
3619#define RJT_UNSUP_TYPE 0x07
3620#define RJT_BAD_CONTROL 0x08
3621#define RJT_BAD_RCTL 0x09
3622#define RJT_BAD_FCTL 0x0A
3623#define RJT_BAD_OXID 0x0B
3624#define RJT_BAD_RXID 0x0C
3625#define RJT_BAD_SEQID 0x0D
3626#define RJT_BAD_DFCTL 0x0E
3627#define RJT_BAD_SEQCNT 0x0F
3628#define RJT_BAD_PARM 0x10
3629#define RJT_XCHG_ERR 0x11
3630#define RJT_PROT_ERR 0x12
3631#define RJT_BAD_LENGTH 0x13
3632#define RJT_UNEXPECTED_ACK 0x14
3633#define RJT_LOGIN_REQUIRED 0x16
3634#define RJT_TOO_MANY_SEQ 0x17
3635#define RJT_XCHG_NOT_STRT 0x18
3636#define RJT_UNSUP_SEC_HDR 0x19
3637#define RJT_UNAVAIL_PATH 0x1A
3638#define RJT_VENDOR_UNIQUE 0xFF
3639
3640#define IOERR_SUCCESS 0x00
3641#define IOERR_MISSING_CONTINUE 0x01
3642#define IOERR_SEQUENCE_TIMEOUT 0x02
3643#define IOERR_INTERNAL_ERROR 0x03
3644#define IOERR_INVALID_RPI 0x04
3645#define IOERR_NO_XRI 0x05
3646#define IOERR_ILLEGAL_COMMAND 0x06
3647#define IOERR_XCHG_DROPPED 0x07
3648#define IOERR_ILLEGAL_FIELD 0x08
3649#define IOERR_BAD_CONTINUE 0x09
3650#define IOERR_TOO_MANY_BUFFERS 0x0A
3651#define IOERR_RCV_BUFFER_WAITING 0x0B
3652#define IOERR_NO_CONNECTION 0x0C
3653#define IOERR_TX_DMA_FAILED 0x0D
3654#define IOERR_RX_DMA_FAILED 0x0E
3655#define IOERR_ILLEGAL_FRAME 0x0F
3656#define IOERR_EXTRA_DATA 0x10
3657#define IOERR_NO_RESOURCES 0x11
3658#define IOERR_RESERVED 0x12
3659#define IOERR_ILLEGAL_LENGTH 0x13
3660#define IOERR_UNSUPPORTED_FEATURE 0x14
3661#define IOERR_ABORT_IN_PROGRESS 0x15
3662#define IOERR_ABORT_REQUESTED 0x16
3663#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3664#define IOERR_LOOP_OPEN_FAILURE 0x18
3665#define IOERR_RING_RESET 0x19
3666#define IOERR_LINK_DOWN 0x1A
3667#define IOERR_CORRUPTED_DATA 0x1B
3668#define IOERR_CORRUPTED_RPI 0x1C
3669#define IOERR_OUT_OF_ORDER_DATA 0x1D
3670#define IOERR_OUT_OF_ORDER_ACK 0x1E
3671#define IOERR_DUP_FRAME 0x1F
3672#define IOERR_LINK_CONTROL_FRAME 0x20
3673#define IOERR_BAD_HOST_ADDRESS 0x21
3674#define IOERR_RCV_HDRBUF_WAITING 0x22
3675#define IOERR_MISSING_HDR_BUFFER 0x23
3676#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3677#define IOERR_ABORTMULT_REQUESTED 0x25
3678#define IOERR_BUFFER_SHORTAGE 0x28
3679#define IOERR_DEFAULT 0x29
3680#define IOERR_CNT 0x2A
3681#define IOERR_SLER_FAILURE 0x46
3682#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3683#define IOERR_SLER_REC_RJT_ERR 0x48
3684#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3685#define IOERR_SLER_SRR_RJT_ERR 0x4A
3686#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3687#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3688#define IOERR_SLER_ABTS_ERR 0x4E
3689#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3690#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3691#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3692#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3693#define IOERR_DRVR_MASK 0x100
3694#define IOERR_SLI_DOWN 0x101
3695#define IOERR_SLI_BRESET 0x102
3696#define IOERR_SLI_ABORTED 0x103
3697#define IOERR_PARAM_MASK 0x1ff
3698} PARM_ERR;
3699
3700typedef union {
3701 struct {
3702#ifdef __BIG_ENDIAN_BITFIELD
3703 uint8_t Rctl;
3704 uint8_t Type;
3705 uint8_t Dfctl;
3706 uint8_t Fctl;
3707#else
3708 uint8_t Fctl;
3709 uint8_t Dfctl;
3710 uint8_t Type;
3711 uint8_t Rctl;
3712#endif
3713
3714#define BC 0x02
3715#define SI 0x04
3716#define LA 0x08
3717#define LS 0x80
3718 } hcsw;
3719 uint32_t reserved;
3720} WORD5;
3721
3722
3723typedef struct {
3724 uint32_t reserved[4];
3725 PARM_ERR perr;
3726} GENERIC_RSP;
3727
3728
3729typedef struct {
3730 struct ulp_bde xrsqbde[2];
3731 uint32_t xrsqRo;
3732 WORD5 w5;
3733} XR_SEQ_FIELDS;
3734
3735
3736typedef struct {
3737 struct ulp_bde elsReq;
3738 struct ulp_bde elsRsp;
3739
3740#ifdef __BIG_ENDIAN_BITFIELD
3741 uint32_t word4Rsvd:7;
3742 uint32_t fl:1;
3743 uint32_t myID:24;
3744 uint32_t word5Rsvd:8;
3745 uint32_t remoteID:24;
3746#else
3747 uint32_t myID:24;
3748 uint32_t fl:1;
3749 uint32_t word4Rsvd:7;
3750 uint32_t remoteID:24;
3751 uint32_t word5Rsvd:8;
3752#endif
3753} ELS_REQUEST;
3754
3755
3756typedef struct {
3757 struct ulp_bde elsReq[2];
3758 uint32_t parmRo;
3759
3760#ifdef __BIG_ENDIAN_BITFIELD
3761 uint32_t word5Rsvd:8;
3762 uint32_t remoteID:24;
3763#else
3764 uint32_t remoteID:24;
3765 uint32_t word5Rsvd:8;
3766#endif
3767} RCV_ELS_REQ;
3768
3769
3770typedef struct {
3771 uint32_t rsvd[3];
3772 uint32_t abortType;
3773#define ABORT_TYPE_ABTX 0x00000000
3774#define ABORT_TYPE_ABTS 0x00000001
3775 uint32_t parm;
3776#ifdef __BIG_ENDIAN_BITFIELD
3777 uint16_t abortContextTag;
3778 uint16_t abortIoTag;
3779#else
3780 uint16_t abortIoTag;
3781 uint16_t abortContextTag;
3782#endif
3783} AC_XRI;
3784
3785
3786typedef struct {
3787 uint32_t rsvd[3];
3788 uint32_t abortType;
3789 uint32_t parm;
3790 uint32_t iotag32;
3791} A_MXRI64;
3792
3793
3794typedef struct {
3795 uint32_t rsvd[4];
3796 uint32_t parmRo;
3797#ifdef __BIG_ENDIAN_BITFIELD
3798 uint32_t word5Rsvd:8;
3799 uint32_t remoteID:24;
3800#else
3801 uint32_t remoteID:24;
3802 uint32_t word5Rsvd:8;
3803#endif
3804} GET_RPI;
3805
3806
3807typedef struct {
3808 struct ulp_bde fcpi_cmnd;
3809 struct ulp_bde fcpi_rsp;
3810 uint32_t fcpi_parm;
3811 uint32_t fcpi_XRdy;
3812} FCPI_FIELDS;
3813
3814
3815typedef struct {
3816 struct ulp_bde fcpt_Buffer[2];
3817 uint32_t fcpt_Offset;
3818 uint32_t fcpt_Length;
3819} FCPT_FIELDS;
3820
3821
3822
3823
3824typedef struct {
3825 ULP_BDL bdl;
3826 uint32_t xrsqRo;
3827 WORD5 w5;
3828} XMT_SEQ_FIELDS64;
3829
3830
3831#define xmit_els_remoteID xrsqRo
3832
3833
3834typedef struct {
3835 struct ulp_bde64 rcvBde;
3836 uint32_t rsvd1;
3837 uint32_t xrsqRo;
3838 WORD5 w5;
3839} RCV_SEQ_FIELDS64;
3840
3841
3842typedef struct {
3843 ULP_BDL bdl;
3844#ifdef __BIG_ENDIAN_BITFIELD
3845 uint32_t word4Rsvd:7;
3846 uint32_t fl:1;
3847 uint32_t myID:24;
3848 uint32_t word5Rsvd:8;
3849 uint32_t remoteID:24;
3850#else
3851 uint32_t myID:24;
3852 uint32_t fl:1;
3853 uint32_t word4Rsvd:7;
3854 uint32_t remoteID:24;
3855 uint32_t word5Rsvd:8;
3856#endif
3857} ELS_REQUEST64;
3858
3859
3860typedef struct {
3861 ULP_BDL bdl;
3862 uint32_t xrsqRo;
3863 WORD5 w5;
3864} GEN_REQUEST64;
3865
3866
3867typedef struct {
3868 struct ulp_bde64 elsReq;
3869 uint32_t rcvd1;
3870 uint32_t parmRo;
3871
3872#ifdef __BIG_ENDIAN_BITFIELD
3873 uint32_t word5Rsvd:8;
3874 uint32_t remoteID:24;
3875#else
3876 uint32_t remoteID:24;
3877 uint32_t word5Rsvd:8;
3878#endif
3879} RCV_ELS_REQ64;
3880
3881
3882struct rcv_seq64 {
3883 struct ulp_bde64 elsReq;
3884 uint32_t hbq_1;
3885 uint32_t parmRo;
3886#ifdef __BIG_ENDIAN_BITFIELD
3887 uint32_t rctl:8;
3888 uint32_t type:8;
3889 uint32_t dfctl:8;
3890 uint32_t ls:1;
3891 uint32_t fs:1;
3892 uint32_t rsvd2:3;
3893 uint32_t si:1;
3894 uint32_t bc:1;
3895 uint32_t rsvd3:1;
3896#else
3897 uint32_t rsvd3:1;
3898 uint32_t bc:1;
3899 uint32_t si:1;
3900 uint32_t rsvd2:3;
3901 uint32_t fs:1;
3902 uint32_t ls:1;
3903 uint32_t dfctl:8;
3904 uint32_t type:8;
3905 uint32_t rctl:8;
3906#endif
3907};
3908
3909
3910typedef struct {
3911 ULP_BDL bdl;
3912 uint32_t fcpi_parm;
3913 uint32_t fcpi_XRdy;
3914} FCPI_FIELDS64;
3915
3916
3917typedef struct {
3918 ULP_BDL bdl;
3919 uint32_t fcpt_Offset;
3920 uint32_t fcpt_Length;
3921} FCPT_FIELDS64;
3922
3923
3924typedef struct {
3925 uint32_t rsvd[4];
3926 uint32_t param;
3927#ifdef __BIG_ENDIAN_BITFIELD
3928 uint16_t evt_code;
3929 uint16_t sub_ctxt_tag;
3930#else
3931 uint16_t sub_ctxt_tag;
3932 uint16_t evt_code;
3933#endif
3934} ASYNCSTAT_FIELDS;
3935#define ASYNC_TEMP_WARN 0x100
3936#define ASYNC_TEMP_SAFE 0x101
3937#define ASYNC_STATUS_CN 0x102
3938
3939
3940
3941
3942struct rcv_sli3 {
3943#ifdef __BIG_ENDIAN_BITFIELD
3944 uint16_t ox_id;
3945 uint16_t seq_cnt;
3946
3947 uint16_t vpi;
3948 uint16_t word9Rsvd;
3949#else
3950 uint16_t seq_cnt;
3951 uint16_t ox_id;
3952
3953 uint16_t word9Rsvd;
3954 uint16_t vpi;
3955#endif
3956 uint32_t word10Rsvd;
3957 uint32_t acc_len;
3958 struct ulp_bde64 bde2;
3959};
3960
3961
3962struct lpfc_hbq_entry {
3963 struct ulp_bde64 bde;
3964 uint32_t buffer_tag;
3965};
3966
3967
3968typedef struct {
3969 struct lpfc_hbq_entry buff;
3970 uint32_t rsvd;
3971 uint32_t rsvd1;
3972} QUE_XRI64_CX_FIELDS;
3973
3974struct que_xri64cx_ext_fields {
3975 uint32_t iotag64_low;
3976 uint32_t iotag64_high;
3977 uint32_t ebde_count;
3978 uint32_t rsvd;
3979 struct lpfc_hbq_entry buff[5];
3980};
3981
3982struct sli3_bg_fields {
3983 uint32_t filler[6];
3984 uint32_t bghm;
3985
3986#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3987#define BGS_BIDIR_BG_PROF_SHIFT 24
3988#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3989#define BGS_BIDIR_ERR_COND_SHIFT 16
3990#define BGS_BG_PROFILE_MASK 0x0000ff00
3991#define BGS_BG_PROFILE_SHIFT 8
3992#define BGS_INVALID_PROF_MASK 0x00000020
3993#define BGS_INVALID_PROF_SHIFT 5
3994#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3995#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3996#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3997#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3998#define BGS_REFTAG_ERR_MASK 0x00000004
3999#define BGS_REFTAG_ERR_SHIFT 2
4000#define BGS_APPTAG_ERR_MASK 0x00000002
4001#define BGS_APPTAG_ERR_SHIFT 1
4002#define BGS_GUARD_ERR_MASK 0x00000001
4003#define BGS_GUARD_ERR_SHIFT 0
4004 uint32_t bgstat;
4005};
4006
4007static inline uint32_t
4008lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4009{
4010 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4011 BGS_BIDIR_BG_PROF_SHIFT;
4012}
4013
4014static inline uint32_t
4015lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4016{
4017 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4018 BGS_BIDIR_ERR_COND_SHIFT;
4019}
4020
4021static inline uint32_t
4022lpfc_bgs_get_bg_prof(uint32_t bgstat)
4023{
4024 return (bgstat & BGS_BG_PROFILE_MASK) >>
4025 BGS_BG_PROFILE_SHIFT;
4026}
4027
4028static inline uint32_t
4029lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4030{
4031 return (bgstat & BGS_INVALID_PROF_MASK) >>
4032 BGS_INVALID_PROF_SHIFT;
4033}
4034
4035static inline uint32_t
4036lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4037{
4038 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4039 BGS_UNINIT_DIF_BLOCK_SHIFT;
4040}
4041
4042static inline uint32_t
4043lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4044{
4045 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4046 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4047}
4048
4049static inline uint32_t
4050lpfc_bgs_get_reftag_err(uint32_t bgstat)
4051{
4052 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4053 BGS_REFTAG_ERR_SHIFT;
4054}
4055
4056static inline uint32_t
4057lpfc_bgs_get_apptag_err(uint32_t bgstat)
4058{
4059 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4060 BGS_APPTAG_ERR_SHIFT;
4061}
4062
4063static inline uint32_t
4064lpfc_bgs_get_guard_err(uint32_t bgstat)
4065{
4066 return (bgstat & BGS_GUARD_ERR_MASK) >>
4067 BGS_GUARD_ERR_SHIFT;
4068}
4069
4070#define LPFC_EXT_DATA_BDE_COUNT 3
4071struct fcp_irw_ext {
4072 uint32_t io_tag64_low;
4073 uint32_t io_tag64_high;
4074#ifdef __BIG_ENDIAN_BITFIELD
4075 uint8_t reserved1;
4076 uint8_t reserved2;
4077 uint8_t reserved3;
4078 uint8_t ebde_count;
4079#else
4080 uint8_t ebde_count;
4081 uint8_t reserved3;
4082 uint8_t reserved2;
4083 uint8_t reserved1;
4084#endif
4085 uint32_t reserved4;
4086 struct ulp_bde64 rbde;
4087 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT];
4088 uint8_t icd[32];
4089};
4090
4091typedef struct _IOCB {
4092 union {
4093 GENERIC_RSP grsp;
4094 XR_SEQ_FIELDS xrseq;
4095 struct ulp_bde cont[3];
4096 RCV_ELS_REQ rcvels;
4097 AC_XRI acxri;
4098 A_MXRI64 amxri;
4099 GET_RPI getrpi;
4100 FCPI_FIELDS fcpi;
4101 FCPT_FIELDS fcpt;
4102
4103
4104
4105 struct ulp_bde64 cont64[2];
4106
4107 ELS_REQUEST64 elsreq64;
4108 GEN_REQUEST64 genreq64;
4109 RCV_ELS_REQ64 rcvels64;
4110 XMT_SEQ_FIELDS64 xseq64;
4111 FCPI_FIELDS64 fcpi64;
4112 FCPT_FIELDS64 fcpt64;
4113 ASYNCSTAT_FIELDS asyncstat;
4114 QUE_XRI64_CX_FIELDS quexri64cx;
4115 struct rcv_seq64 rcvseq64;
4116 struct sli4_bls_rsp bls_rsp;
4117 uint32_t ulpWord[IOCB_WORD_SZ - 2];
4118 } un;
4119 union {
4120 struct {
4121#ifdef __BIG_ENDIAN_BITFIELD
4122 uint16_t ulpContext;
4123 uint16_t ulpIoTag;
4124#else
4125 uint16_t ulpIoTag;
4126 uint16_t ulpContext;
4127#endif
4128 } t1;
4129 struct {
4130#ifdef __BIG_ENDIAN_BITFIELD
4131 uint16_t ulpContext;
4132 uint16_t ulpIoTag1:2;
4133 uint16_t ulpIoTag0:14;
4134#else
4135 uint16_t ulpIoTag0:14;
4136 uint16_t ulpIoTag1:2;
4137 uint16_t ulpContext;
4138#endif
4139 } t2;
4140 } un1;
4141#define ulpContext un1.t1.ulpContext
4142#define ulpIoTag un1.t1.ulpIoTag
4143#define ulpIoTag0 un1.t2.ulpIoTag0
4144
4145#ifdef __BIG_ENDIAN_BITFIELD
4146 uint32_t ulpTimeout:8;
4147 uint32_t ulpXS:1;
4148 uint32_t ulpFCP2Rcvy:1;
4149 uint32_t ulpPU:2;
4150 uint32_t ulpIr:1;
4151 uint32_t ulpClass:3;
4152 uint32_t ulpCommand:8;
4153 uint32_t ulpStatus:4;
4154 uint32_t ulpBdeCount:2;
4155 uint32_t ulpLe:1;
4156 uint32_t ulpOwner:1;
4157#else
4158 uint32_t ulpOwner:1;
4159 uint32_t ulpLe:1;
4160 uint32_t ulpBdeCount:2;
4161 uint32_t ulpStatus:4;
4162 uint32_t ulpCommand:8;
4163 uint32_t ulpClass:3;
4164 uint32_t ulpIr:1;
4165 uint32_t ulpPU:2;
4166 uint32_t ulpFCP2Rcvy:1;
4167 uint32_t ulpXS:1;
4168 uint32_t ulpTimeout:8;
4169#endif
4170
4171 union {
4172 struct rcv_sli3 rcvsli3;
4173
4174
4175 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4176 struct fcp_irw_ext fcp_ext;
4177 uint32_t sli3Words[24];
4178
4179
4180 struct sli3_bg_fields sli3_bg;
4181 } unsli3;
4182
4183#define ulpCt_h ulpXS
4184#define ulpCt_l ulpFCP2Rcvy
4185
4186#define IOCB_FCP 1
4187#define IOCB_IP 2
4188#define PARM_UNUSED 0
4189#define PARM_REL_OFF 1
4190#define PARM_READ_CHECK 2
4191#define PARM_NPIV_DID 3
4192#define CLASS1 0
4193#define CLASS2 1
4194#define CLASS3 2
4195#define CLASS_FCP_INTERMIX 7
4196
4197#define IOSTAT_SUCCESS 0x0
4198#define IOSTAT_FCP_RSP_ERROR 0x1
4199#define IOSTAT_REMOTE_STOP 0x2
4200#define IOSTAT_LOCAL_REJECT 0x3
4201#define IOSTAT_NPORT_RJT 0x4
4202#define IOSTAT_FABRIC_RJT 0x5
4203#define IOSTAT_NPORT_BSY 0x6
4204#define IOSTAT_FABRIC_BSY 0x7
4205#define IOSTAT_INTERMED_RSP 0x8
4206#define IOSTAT_LS_RJT 0x9
4207#define IOSTAT_BA_RJT 0xA
4208#define IOSTAT_RSVD1 0xB
4209#define IOSTAT_RSVD2 0xC
4210#define IOSTAT_RSVD3 0xD
4211#define IOSTAT_RSVD4 0xE
4212#define IOSTAT_NEED_BUFFER 0xF
4213#define IOSTAT_DRIVER_REJECT 0x10
4214#define IOSTAT_DEFAULT 0xF
4215#define IOSTAT_CNT 0x11
4216
4217} IOCB_t;
4218
4219
4220#define SLI1_SLIM_SIZE (4 * 1024)
4221
4222
4223
4224
4225#define SLI2_SLIM_SIZE (64 * 1024)
4226
4227
4228#define MAX_SLI2_IOCB 498
4229#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4230 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4231 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4232
4233
4234#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4235 lpfc_sli_hbq_count())
4236
4237struct lpfc_sli2_slim {
4238 MAILBOX_t mbx;
4239 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4240 PCB_t pcb;
4241 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4242};
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253static inline int
4254lpfc_is_LC_HBA(unsigned short device)
4255{
4256 if ((device == PCI_DEVICE_ID_TFLY) ||
4257 (device == PCI_DEVICE_ID_PFLY) ||
4258 (device == PCI_DEVICE_ID_LP101) ||
4259 (device == PCI_DEVICE_ID_BMID) ||
4260 (device == PCI_DEVICE_ID_BSMB) ||
4261 (device == PCI_DEVICE_ID_ZMID) ||
4262 (device == PCI_DEVICE_ID_ZSMB) ||
4263 (device == PCI_DEVICE_ID_SAT_MID) ||
4264 (device == PCI_DEVICE_ID_SAT_SMB) ||
4265 (device == PCI_DEVICE_ID_RFLY))
4266 return 1;
4267 else
4268 return 0;
4269}
4270
4271
4272
4273
4274
4275static inline int
4276lpfc_error_lost_link(IOCB_t *iocbp)
4277{
4278 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4279 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4280 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4281 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4282}
4283
4284#define MENLO_TRANSPORT_TYPE 0xfe
4285#define MENLO_CONTEXT 0
4286#define MENLO_PU 3
4287#define MENLO_TIMEOUT 30
4288#define SETVAR_MLOMNT 0x103107
4289#define SETVAR_MLORST 0x103007
4290
4291#define BPL_ALIGN_SZ 8
4292