LXR linux/drivers/staging/vt6656/mac.h

   1/*
   2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3 * All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, write to the Free Software Foundation, Inc.,
  17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18 *
  19 *
  20 * File: mac.h
  21 *
  22 * Purpose: MAC routines
  23 *
  24 * Author: Tevin Chen
  25 *
  26 * Date: May 21, 1996
  27 *
  28 * Revision History:
  29 *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  30 *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  31 *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  32 */
  33
  34#ifndef __MAC_H__
  35#define __MAC_H__
  36
  37#include "device.h"
  38#include "tmacro.h"
  39
  40#define REV_ID_VT3253_A0    0x00
  41#define REV_ID_VT3253_A1    0x01
  42#define REV_ID_VT3253_B0    0x08
  43#define REV_ID_VT3253_B1    0x09
  44
  45//
  46// Registers in the MAC
  47//
  48#define MAC_REG_BISTCMD     0x04
  49#define MAC_REG_BISTSR0     0x05
  50#define MAC_REG_BISTSR1     0x06
  51#define MAC_REG_BISTSR2     0x07
  52#define MAC_REG_I2MCSR      0x08
  53#define MAC_REG_I2MTGID     0x09
  54#define MAC_REG_I2MTGAD     0x0A
  55#define MAC_REG_I2MCFG      0x0B
  56#define MAC_REG_I2MDIPT     0x0C
  57#define MAC_REG_I2MDOPT     0x0E
  58#define MAC_REG_USBSUS      0x0F
  59
  60#define MAC_REG_LOCALID     0x14
  61#define MAC_REG_TESTCFG     0x15
  62#define MAC_REG_JUMPER0     0x16
  63#define MAC_REG_JUMPER1     0x17
  64#define MAC_REG_TMCTL       0x18
  65#define MAC_REG_TMDATA0     0x1C
  66#define MAC_REG_TMDATA1     0x1D
  67#define MAC_REG_TMDATA2     0x1E
  68#define MAC_REG_TMDATA3     0x1F
  69
  70// MAC Parameter related
  71#define MAC_REG_LRT         0x20        //
  72#define MAC_REG_SRT         0x21        //
  73#define MAC_REG_SIFS        0x22        //
  74#define MAC_REG_DIFS        0x23        //
  75#define MAC_REG_EIFS        0x24        //
  76#define MAC_REG_SLOT        0x25        //
  77#define MAC_REG_BI          0x26        //
  78#define MAC_REG_CWMAXMIN0   0x28        //
  79#define MAC_REG_LINKOFFTOTM 0x2A
  80#define MAC_REG_SWTMOT      0x2B
  81#define MAC_REG_RTSOKCNT    0x2C
  82#define MAC_REG_RTSFAILCNT  0x2D
  83#define MAC_REG_ACKFAILCNT  0x2E
  84#define MAC_REG_FCSERRCNT   0x2F
  85// TSF Related
  86#define MAC_REG_TSFCNTR     0x30        //
  87#define MAC_REG_NEXTTBTT    0x38        //
  88#define MAC_REG_TSFOFST     0x40        //
  89#define MAC_REG_TFTCTL      0x48        //
  90// WMAC Control/Status Related
  91#define MAC_REG_ENCFG0      0x4C        //
  92#define MAC_REG_ENCFG1      0x4D        //
  93#define MAC_REG_ENCFG2      0x4E        //
  94
  95#define MAC_REG_CFG         0x50        //
  96#define MAC_REG_TEST        0x52        //
  97#define MAC_REG_HOSTCR      0x54        //
  98#define MAC_REG_MACCR       0x55        //
  99#define MAC_REG_RCR         0x56        //
 100#define MAC_REG_TCR         0x57        //
 101#define MAC_REG_IMR         0x58        //
 102#define MAC_REG_ISR         0x5C
 103#define MAC_REG_ISR1        0x5D
 104// Power Saving Related
 105#define MAC_REG_PSCFG       0x60        //
 106#define MAC_REG_PSCTL       0x61        //
 107#define MAC_REG_PSPWRSIG    0x62        //
 108#define MAC_REG_BBCR13      0x63
 109#define MAC_REG_AIDATIM     0x64
 110#define MAC_REG_PWBT        0x66
 111#define MAC_REG_WAKEOKTMR   0x68
 112#define MAC_REG_CALTMR      0x69
 113#define MAC_REG_SYNSPACCNT  0x6A
 114#define MAC_REG_WAKSYNOPT   0x6B
 115// Baseband/IF Control Group
 116#define MAC_REG_BBREGCTL    0x6C        //
 117#define MAC_REG_CHANNEL     0x6D
 118#define MAC_REG_BBREGADR    0x6E
 119#define MAC_REG_BBREGDATA   0x6F
 120#define MAC_REG_IFREGCTL    0x70        //
 121#define MAC_REG_IFDATA      0x71        //
 122#define MAC_REG_ITRTMSET    0x74        //
 123#define MAC_REG_PAPEDELAY   0x77
 124#define MAC_REG_SOFTPWRCTL  0x78        //
 125#define MAC_REG_SOFTPWRCTL2 0x79        //
 126#define MAC_REG_GPIOCTL0    0x7A        //
 127#define MAC_REG_GPIOCTL1    0x7B        //
 128
 129// MiscFF PIO related
 130#define MAC_REG_MISCFFNDEX  0xBC
 131#define MAC_REG_MISCFFCTL   0xBE
 132#define MAC_REG_MISCFFDATA  0xC0
 133
 134// MAC Configuration Group
 135#define MAC_REG_PAR0        0xC4
 136#define MAC_REG_PAR4        0xC8
 137#define MAC_REG_BSSID0      0xCC
 138#define MAC_REG_BSSID4      0xD0
 139#define MAC_REG_MAR0        0xD4
 140#define MAC_REG_MAR4        0xD8
 141// MAC RSPPKT INFO Group
 142#define MAC_REG_RSPINF_B_1  0xDC
 143#define MAC_REG_RSPINF_B_2  0xE0
 144#define MAC_REG_RSPINF_B_5  0xE4
 145#define MAC_REG_RSPINF_B_11 0xE8
 146#define MAC_REG_RSPINF_A_6  0xEC
 147#define MAC_REG_RSPINF_A_9  0xEE
 148#define MAC_REG_RSPINF_A_12 0xF0
 149#define MAC_REG_RSPINF_A_18 0xF2
 150#define MAC_REG_RSPINF_A_24 0xF4
 151#define MAC_REG_RSPINF_A_36 0xF6
 152#define MAC_REG_RSPINF_A_48 0xF8
 153#define MAC_REG_RSPINF_A_54 0xFA
 154#define MAC_REG_RSPINF_A_72 0xFC
 155
 156//
 157// Bits in the I2MCFG EEPROM register
 158//
 159#define I2MCFG_BOUNDCTL     0x80
 160#define I2MCFG_WAITCTL      0x20
 161#define I2MCFG_SCLOECTL     0x10
 162#define I2MCFG_WBUSYCTL     0x08
 163#define I2MCFG_NORETRY      0x04
 164#define I2MCFG_I2MLDSEQ     0x02
 165#define I2MCFG_I2CMFAST     0x01
 166
 167//
 168// Bits in the I2MCSR EEPROM register
 169//
 170#define I2MCSR_EEMW         0x80
 171#define I2MCSR_EEMR         0x40
 172#define I2MCSR_AUTOLD       0x08
 173#define I2MCSR_NACK         0x02
 174#define I2MCSR_DONE         0x01
 175
 176//
 177// Bits in the TMCTL register
 178//
 179#define TMCTL_TSUSP         0x04
 180#define TMCTL_TMD           0x02
 181#define TMCTL_TE            0x01
 182
 183//
 184// Bits in the TFTCTL register
 185//
 186#define TFTCTL_HWUTSF       0x80        //
 187#define TFTCTL_TBTTSYNC     0x40
 188#define TFTCTL_HWUTSFEN     0x20
 189#define TFTCTL_TSFCNTRRD    0x10        //
 190#define TFTCTL_TBTTSYNCEN   0x08        //
 191#define TFTCTL_TSFSYNCEN    0x04        //
 192#define TFTCTL_TSFCNTRST    0x02        //
 193#define TFTCTL_TSFCNTREN    0x01        //
 194
 195//
 196// Bits in the EnhanceCFG_0 register
 197//
 198#define EnCFG_BBType_a      0x00
 199#define EnCFG_BBType_b      0x01
 200#define EnCFG_BBType_g      0x02
 201#define EnCFG_BBType_MASK   0x03
 202#define EnCFG_ProtectMd     0x20
 203
 204//
 205// Bits in the EnhanceCFG_1 register
 206//
 207#define EnCFG_BcnSusInd     0x01
 208#define EnCFG_BcnSusClr     0x02
 209
 210//
 211// Bits in the EnhanceCFG_2 register
 212//
 213#define EnCFG_NXTBTTCFPSTR  0x01
 214#define EnCFG_BarkerPream   0x02
 215#define EnCFG_PktBurstMode  0x04
 216
 217//
 218// Bits in the CFG register
 219//
 220#define CFG_TKIPOPT         0x80
 221#define CFG_RXDMAOPT        0x40
 222#define CFG_TMOT_SW         0x20
 223#define CFG_TMOT_HWLONG     0x10
 224#define CFG_TMOT_HW         0x00
 225#define CFG_CFPENDOPT       0x08
 226#define CFG_BCNSUSEN        0x04
 227#define CFG_NOTXTIMEOUT     0x02
 228#define CFG_NOBUFOPT        0x01
 229
 230//
 231// Bits in the TEST register
 232//
 233#define TEST_LBEXT          0x80        //
 234#define TEST_LBINT          0x40        //
 235#define TEST_LBNONE         0x00        //
 236#define TEST_SOFTINT        0x20        //
 237#define TEST_CONTTX         0x10        //
 238#define TEST_TXPE           0x08        //
 239#define TEST_NAVDIS         0x04        //
 240#define TEST_NOCTS          0x02        //
 241#define TEST_NOACK          0x01        //
 242
 243//
 244// Bits in the HOSTCR register
 245//
 246#define HOSTCR_TXONST       0x80        //
 247#define HOSTCR_RXONST       0x40        //
 248#define HOSTCR_ADHOC        0x20        // Network Type 1 = Ad-hoc
 249#define HOSTCR_AP           0x10        // Port Type 1 = AP
 250#define HOSTCR_TXON         0x08        //0000 1000
 251#define HOSTCR_RXON         0x04        //0000 0100
 252#define HOSTCR_MACEN        0x02        //0000 0010
 253#define HOSTCR_SOFTRST      0x01        //0000 0001
 254
 255//
 256// Bits in the MACCR register
 257//
 258#define MACCR_SYNCFLUSHOK   0x04        //
 259#define MACCR_SYNCFLUSH     0x02        //
 260#define MACCR_CLRNAV        0x01        //
 261
 262//
 263// Bits in the RCR register
 264//
 265#define RCR_SSID            0x80
 266#define RCR_RXALLTYPE       0x40        //
 267#define RCR_UNICAST         0x20        //
 268#define RCR_BROADCAST       0x10        //
 269#define RCR_MULTICAST       0x08        //
 270#define RCR_WPAERR          0x04        //
 271#define RCR_ERRCRC          0x02        //
 272#define RCR_BSSID           0x01        //
 273
 274//
 275// Bits in the TCR register
 276//
 277#define TCR_SYNCDCFOPT      0x02        //
 278#define TCR_AUTOBCNTX       0x01        // Beacon automatically transmit enable
 279
 280//ISR1
 281#define ISR_GPIO3           0x40
 282#define ISR_RXNOBUF         0x08
 283#define ISR_MIBNEARFULL     0x04
 284#define ISR_SOFTINT         0x02
 285#define ISR_FETALERR        0x01
 286
 287#define LEDSTS_STS          0x06
 288#define LEDSTS_TMLEN        0x78
 289#define LEDSTS_OFF          0x00
 290#define LEDSTS_ON           0x02
 291#define LEDSTS_SLOW         0x04
 292#define LEDSTS_INTER        0x06
 293
 294//ISR0
 295#define ISR_WATCHDOG        0x80
 296#define ISR_SOFTTIMER       0x40
 297#define ISR_GPIO0           0x20
 298#define ISR_TBTT            0x10
 299#define ISR_RXDMA0          0x08
 300#define ISR_BNTX            0x04
 301#define ISR_ACTX            0x01
 302
 303//
 304// Bits in the PSCFG register
 305//
 306#define PSCFG_PHILIPMD      0x40        //
 307#define PSCFG_WAKECALEN     0x20        //
 308#define PSCFG_WAKETMREN     0x10        //
 309#define PSCFG_BBPSPROG      0x08        //
 310#define PSCFG_WAKESYN       0x04        //
 311#define PSCFG_SLEEPSYN      0x02        //
 312#define PSCFG_AUTOSLEEP     0x01        //
 313
 314//
 315// Bits in the PSCTL register
 316//
 317#define PSCTL_WAKEDONE      0x20        //
 318#define PSCTL_PS            0x10        //
 319#define PSCTL_GO2DOZE       0x08        //
 320#define PSCTL_LNBCN         0x04        //
 321#define PSCTL_ALBCN         0x02        //
 322#define PSCTL_PSEN          0x01        //
 323
 324//
 325// Bits in the PSPWSIG register
 326//
 327#define PSSIG_WPE3          0x80        //
 328#define PSSIG_WPE2          0x40        //
 329#define PSSIG_WPE1          0x20        //
 330#define PSSIG_WRADIOPE      0x10        //
 331#define PSSIG_SPE3          0x08        //
 332#define PSSIG_SPE2          0x04        //
 333#define PSSIG_SPE1          0x02        //
 334#define PSSIG_SRADIOPE      0x01        //
 335
 336//
 337// Bits in the BBREGCTL register
 338//
 339#define BBREGCTL_DONE       0x04        //
 340#define BBREGCTL_REGR       0x02        //
 341#define BBREGCTL_REGW       0x01        //
 342
 343//
 344// Bits in the IFREGCTL register
 345//
 346#define IFREGCTL_DONE       0x04        //
 347#define IFREGCTL_IFRF       0x02        //
 348#define IFREGCTL_REGW       0x01        //
 349
 350//
 351// Bits in the SOFTPWRCTL register
 352//
 353#define SOFTPWRCTL_RFLEOPT      0x08  //
 354#define SOFTPWRCTL_TXPEINV      0x02  //
 355#define SOFTPWRCTL_SWPECTI      0x01  //
 356#define SOFTPWRCTL_SWPAPE       0x20  //
 357#define SOFTPWRCTL_SWCALEN      0x10  //
 358#define SOFTPWRCTL_SWRADIO_PE   0x08  //
 359#define SOFTPWRCTL_SWPE2        0x04  //
 360#define SOFTPWRCTL_SWPE1        0x02  //
 361#define SOFTPWRCTL_SWPE3        0x01  //
 362
 363//
 364// Bits in the GPIOCTL1 register
 365//
 366#define GPIO3_MD                0x20    //
 367#define GPIO3_DATA              0x40    //
 368#define GPIO3_INTMD             0x80    //
 369
 370//
 371// Bits in the MISCFFCTL register
 372//
 373#define MISCFFCTL_WRITE     0x0001      //
 374
 375// Loopback mode
 376#define MAC_LB_EXT          0x02        //
 377#define MAC_LB_INTERNAL     0x01        //
 378#define MAC_LB_NONE         0x00        //
 379
 380// Ethernet address filter type
 381#define PKT_TYPE_NONE           0x00    // turn off receiver
 382#define PKT_TYPE_ALL_MULTICAST  0x80
 383#define PKT_TYPE_PROMISCUOUS    0x40
 384#define PKT_TYPE_DIRECTED       0x20    // obselete, directed address is always accepted
 385#define PKT_TYPE_BROADCAST      0x10
 386#define PKT_TYPE_MULTICAST      0x08
 387#define PKT_TYPE_ERROR_WPA      0x04
 388#define PKT_TYPE_ERROR_CRC      0x02
 389#define PKT_TYPE_BSSID          0x01
 390
 391#define Default_BI              0x200
 392
 393// MiscFIFO Offset
 394#define MISCFIFO_KEYETRY0       32
 395#define MISCFIFO_KEYENTRYSIZE   22
 396
 397// max time out delay time
 398#define W_MAX_TIMEOUT       0xFFF0U     //
 399
 400// wait time within loop
 401#define CB_DELAY_LOOP_WAIT  10          // 10ms
 402
 403#define MAC_REVISION_A0     0x00
 404#define MAC_REVISION_A1     0x01
 405
 406void MACvWriteMultiAddr(struct vnt_private *, u32, u8);
 407void MACbShutdown(struct vnt_private *);
 408void MACvSetBBType(struct vnt_private *, u8);
 409void MACvDisableKeyEntry(struct vnt_private *, u32);
 410void MACvSetKeyEntry(struct vnt_private *, u16, u32, u32, u8 *, u32 *);
 411void MACvRegBitsOff(struct vnt_private *, u8, u8);
 412void MACvRegBitsOn(struct vnt_private *, u8, u8);
 413void MACvWriteWord(struct vnt_private *, u8, u16);
 414void MACvWriteBSSIDAddress(struct vnt_private *, u8 *);
 415void MACvEnableProtectMD(struct vnt_private *);
 416void MACvDisableProtectMD(struct vnt_private *);
 417void MACvEnableBarkerPreambleMd(struct vnt_private *);
 418void MACvDisableBarkerPreambleMd(struct vnt_private *);
 419void MACvWriteBeaconInterval(struct vnt_private *, u16);
 420
 421#endif /* __MAC_H__ */
 422