1/* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10#ifndef __DW_HDMI__ 11#define __DW_HDMI__ 12 13#include <drm/drmP.h> 14 15struct dw_hdmi; 16 17/** 18 * DOC: Supported input formats and encodings 19 * 20 * Depending on the Hardware configuration of the Controller IP, it supports 21 * a subset of the following input formats and encodings on its internal 22 * 48bit bus. 23 * 24 * +----------------------+----------------------------------+------------------------------+ 25 * | Format Name | Format Code | Encodings | 26 * +----------------------+----------------------------------+------------------------------+ 27 * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 28 * +----------------------+----------------------------------+------------------------------+ 29 * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 30 * +----------------------+----------------------------------+------------------------------+ 31 * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 32 * +----------------------+----------------------------------+------------------------------+ 33 * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 34 * +----------------------+----------------------------------+------------------------------+ 35 * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` | 36 * | | | or ``V4L2_YCBCR_ENC_709`` | 37 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 38 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 39 * +----------------------+----------------------------------+------------------------------+ 40 * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` | 41 * | | | or ``V4L2_YCBCR_ENC_709`` | 42 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 43 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 44 * +----------------------+----------------------------------+------------------------------+ 45 * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` | 46 * | | | or ``V4L2_YCBCR_ENC_709`` | 47 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 48 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 49 * +----------------------+----------------------------------+------------------------------+ 50 * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` | 51 * | | | or ``V4L2_YCBCR_ENC_709`` | 52 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 53 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 54 * +----------------------+----------------------------------+------------------------------+ 55 * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` | 56 * | | | or ``V4L2_YCBCR_ENC_709`` | 57 * +----------------------+----------------------------------+------------------------------+ 58 * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` | 59 * | | | or ``V4L2_YCBCR_ENC_709`` | 60 * +----------------------+----------------------------------+------------------------------+ 61 * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` | 62 * | | | or ``V4L2_YCBCR_ENC_709`` | 63 * +----------------------+----------------------------------+------------------------------+ 64 * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` | 65 * | | | or ``V4L2_YCBCR_ENC_709`` | 66 * +----------------------+----------------------------------+------------------------------+ 67 * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` | 68 * | | | or ``V4L2_YCBCR_ENC_709`` | 69 * +----------------------+----------------------------------+------------------------------+ 70 * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` | 71 * | | | or ``V4L2_YCBCR_ENC_709`` | 72 * +----------------------+----------------------------------+------------------------------+ 73 * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` | 74 * | | | or ``V4L2_YCBCR_ENC_709`` | 75 * +----------------------+----------------------------------+------------------------------+ 76 */ 77 78enum { 79 DW_HDMI_RES_8, 80 DW_HDMI_RES_10, 81 DW_HDMI_RES_12, 82 DW_HDMI_RES_MAX, 83}; 84 85enum dw_hdmi_phy_type { 86 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 87 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 88 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 89 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 90 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 91 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 92 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 93}; 94 95struct dw_hdmi_mpll_config { 96 unsigned long mpixelclock; 97 struct { 98 u16 cpce; 99 u16 gmp; 100 } res[DW_HDMI_RES_MAX]; 101}; 102 103struct dw_hdmi_curr_ctrl { 104 unsigned long mpixelclock; 105 u16 curr[DW_HDMI_RES_MAX]; 106}; 107 108struct dw_hdmi_phy_config { 109 unsigned long mpixelclock; 110 u16 sym_ctr; /*clock symbol and transmitter control*/ 111 u16 term; /*transmission termination value*/ 112 u16 vlev_ctr; /* voltage level control */ 113}; 114 115struct dw_hdmi_phy_ops { 116 int (*init)(struct dw_hdmi *hdmi, void *data, 117 struct drm_display_mode *mode); 118 void (*disable)(struct dw_hdmi *hdmi, void *data); 119 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); 120 void (*update_hpd)(struct dw_hdmi *hdmi, void *data, 121 bool force, bool disabled, bool rxsense); 122 void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); 123}; 124 125struct dw_hdmi_plat_data { 126 struct regmap *regm; 127 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, 128 const struct drm_display_mode *mode); 129 unsigned long input_bus_format; 130 unsigned long input_bus_encoding; 131 132 /* Vendor PHY support */ 133 const struct dw_hdmi_phy_ops *phy_ops; 134 const char *phy_name; 135 void *phy_data; 136 unsigned int phy_force_vendor; 137 138 /* Synopsys PHY support */ 139 const struct dw_hdmi_mpll_config *mpll_cfg; 140 const struct dw_hdmi_curr_ctrl *cur_ctr; 141 const struct dw_hdmi_phy_config *phy_config; 142 int (*configure_phy)(struct dw_hdmi *hdmi, 143 const struct dw_hdmi_plat_data *pdata, 144 unsigned long mpixelclock); 145}; 146 147struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 148 const struct dw_hdmi_plat_data *plat_data); 149void dw_hdmi_remove(struct dw_hdmi *hdmi); 150void dw_hdmi_unbind(struct dw_hdmi *hdmi); 151struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 152 struct drm_encoder *encoder, 153 const struct dw_hdmi_plat_data *plat_data); 154 155void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); 156 157void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); 158void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); 159void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); 160 161/* PHY configuration */ 162void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); 163void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 164 unsigned char addr); 165 166void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); 167void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); 168void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); 169 170enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 171 void *data); 172void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 173 bool force, bool disabled, bool rxsense); 174void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); 175 176#endif /* __IMX_HDMI_H__ */ 177